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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-apple-darwin -run-pass=instruction-select -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s3 4...5---6name: select_f327alignment: 48legalized: true9regBankSelected: true10tracksRegLiveness: true11machineFunctionInfo: {}12body: |13 bb.0:14 liveins: $s0, $s1, $w015 16 ; CHECK-LABEL: name: select_f3217 ; CHECK: liveins: $s0, $s1, $w018 ; CHECK-NEXT: {{ $}}19 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w020 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s021 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s122 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv23 ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[COPY2]], 1, implicit $nzcv24 ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]25 ; CHECK-NEXT: RET_ReallyLR implicit $s026 %0:gpr(s32) = COPY $w027 %1:fpr(s32) = COPY $s028 %2:fpr(s32) = COPY $s129 %4:fpr(s32) = G_SELECT %0, %1, %230 $s0 = COPY %4(s32)31 RET_ReallyLR implicit $s032 33...34---35name: select_f6436alignment: 437legalized: true38regBankSelected: true39tracksRegLiveness: true40machineFunctionInfo: {}41body: |42 bb.0:43 liveins: $d0, $d1, $w044 45 ; CHECK-LABEL: name: select_f6446 ; CHECK: liveins: $d0, $d1, $w047 ; CHECK-NEXT: {{ $}}48 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w049 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d050 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d151 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv52 ; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[COPY2]], 1, implicit $nzcv53 ; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]54 ; CHECK-NEXT: RET_ReallyLR implicit $d055 %0:gpr(s32) = COPY $w056 %1:fpr(s64) = COPY $d057 %2:fpr(s64) = COPY $d158 %4:fpr(s64) = G_SELECT %0, %1, %259 $d0 = COPY %4(s64)60 RET_ReallyLR implicit $d061...62---63name: csel64legalized: true65regBankSelected: true66tracksRegLiveness: true67body: |68 bb.0:69 liveins: $w0, $w1, $w2, $w370 ; CHECK-LABEL: name: csel71 ; CHECK: liveins: $w0, $w1, $w2, $w372 ; CHECK-NEXT: {{ $}}73 ; CHECK-NEXT: %reg0:gpr32 = COPY $w074 ; CHECK-NEXT: %reg1:gpr32 = COPY $w175 ; CHECK-NEXT: %t:gpr32 = COPY $w276 ; CHECK-NEXT: %f:gpr32 = COPY $w377 ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv78 ; CHECK-NEXT: %select:gpr32 = CSELWr %t, %f, 1, implicit $nzcv79 ; CHECK-NEXT: $w0 = COPY %select80 ; CHECK-NEXT: RET_ReallyLR implicit $w081 %reg0:gpr(s32) = COPY $w082 %reg1:gpr(s32) = COPY $w183 %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg184 %t:gpr(s32) = COPY $w285 %f:gpr(s32) = COPY $w386 %select:gpr(s32) = G_SELECT %cmp, %t, %f87 $w0 = COPY %select(s32)88 RET_ReallyLR implicit $w089...90---91name: csinc_t_0_f_192legalized: true93regBankSelected: true94tracksRegLiveness: true95body: |96 bb.0:97 liveins: $w0, $w198 ; G_SELECT cc, 0, 1 -> CSINC zreg, zreg, cc99 100 ; CHECK-LABEL: name: csinc_t_0_f_1101 ; CHECK: liveins: $w0, $w1102 ; CHECK-NEXT: {{ $}}103 ; CHECK-NEXT: %reg0:gpr32 = COPY $w0104 ; CHECK-NEXT: %reg1:gpr32 = COPY $w1105 ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv106 ; CHECK-NEXT: %select:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv107 ; CHECK-NEXT: $w0 = COPY %select108 ; CHECK-NEXT: RET_ReallyLR implicit $w0109 %reg0:gpr(s32) = COPY $w0110 %reg1:gpr(s32) = COPY $w1111 %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1112 %t:gpr(s32) = G_CONSTANT i32 0113 %f:gpr(s32) = G_CONSTANT i32 1114 %select:gpr(s32) = G_SELECT %cmp, %t, %f115 $w0 = COPY %select(s32)116 RET_ReallyLR implicit $w0117...118---119name: csinv_t_0_f_neg_1120legalized: true121regBankSelected: true122tracksRegLiveness: true123body: |124 bb.0:125 liveins: $w0, $w1126 ; G_SELECT cc 0, -1 -> CSINV zreg, zreg cc127 128 ; CHECK-LABEL: name: csinv_t_0_f_neg_1129 ; CHECK: liveins: $w0, $w1130 ; CHECK-NEXT: {{ $}}131 ; CHECK-NEXT: %reg0:gpr32 = COPY $w0132 ; CHECK-NEXT: %reg1:gpr32 = COPY $w1133 ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv134 ; CHECK-NEXT: %select:gpr32 = CSINVWr $wzr, $wzr, 1, implicit $nzcv135 ; CHECK-NEXT: $w0 = COPY %select136 ; CHECK-NEXT: RET_ReallyLR implicit $w0137 %reg0:gpr(s32) = COPY $w0138 %reg1:gpr(s32) = COPY $w1139 %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1140 %t:gpr(s32) = G_CONSTANT i32 0141 %f:gpr(s32) = G_CONSTANT i32 -1142 %select:gpr(s32) = G_SELECT %cmp, %t, %f143 $w0 = COPY %select(s32)144 RET_ReallyLR implicit $w0145...146---147name: csinc_t_1148legalized: true149regBankSelected: true150tracksRegLiveness: true151body: |152 bb.0:153 liveins: $w0, $w1, $w2154 ; G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc155 156 ; CHECK-LABEL: name: csinc_t_1157 ; CHECK: liveins: $w0, $w1, $w2158 ; CHECK-NEXT: {{ $}}159 ; CHECK-NEXT: %reg0:gpr32 = COPY $w0160 ; CHECK-NEXT: %reg1:gpr32 = COPY $w1161 ; CHECK-NEXT: %f:gpr32 = COPY $w2162 ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv163 ; CHECK-NEXT: %select:gpr32 = CSINCWr %f, $wzr, 0, implicit $nzcv164 ; CHECK-NEXT: $w0 = COPY %select165 ; CHECK-NEXT: RET_ReallyLR implicit $w0166 %reg0:gpr(s32) = COPY $w0167 %reg1:gpr(s32) = COPY $w1168 %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1169 %t:gpr(s32) = G_CONSTANT i32 1170 %f:gpr(s32) = COPY $w2171 %select:gpr(s32) = G_SELECT %cmp, %t, %f172 $w0 = COPY %select(s32)173 RET_ReallyLR implicit $w0174...175---176name: csinv_t_neg_1177legalized: true178regBankSelected: true179tracksRegLiveness: true180body: |181 bb.0:182 liveins: $w0, $w1, $w2183 ; G_SELECT cc, -1, f -> CSINV f, zreg, inv_cc184 185 ; CHECK-LABEL: name: csinv_t_neg_1186 ; CHECK: liveins: $w0, $w1, $w2187 ; CHECK-NEXT: {{ $}}188 ; CHECK-NEXT: %reg0:gpr32 = COPY $w0189 ; CHECK-NEXT: %reg1:gpr32 = COPY $w1190 ; CHECK-NEXT: %f:gpr32 = COPY $w2191 ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv192 ; CHECK-NEXT: %select:gpr32 = CSINVWr %f, $wzr, 0, implicit $nzcv193 ; CHECK-NEXT: $w0 = COPY %select194 ; CHECK-NEXT: RET_ReallyLR implicit $w0195 %reg0:gpr(s32) = COPY $w0196 %reg1:gpr(s32) = COPY $w1197 %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1198 %t:gpr(s32) = G_CONSTANT i32 -1199 %f:gpr(s32) = COPY $w2200 %select:gpr(s32) = G_SELECT %cmp, %t, %f201 $w0 = COPY %select(s32)202 RET_ReallyLR implicit $w0203...204---205name: csinc_f_1206legalized: true207regBankSelected: true208tracksRegLiveness: true209body: |210 bb.0:211 liveins: $w0, $w1, $w2212 ; G_SELECT cc, t, 1 -> CSINC t, zreg, cc213 214 ; CHECK-LABEL: name: csinc_f_1215 ; CHECK: liveins: $w0, $w1, $w2216 ; CHECK-NEXT: {{ $}}217 ; CHECK-NEXT: %reg0:gpr32 = COPY $w0218 ; CHECK-NEXT: %reg1:gpr32 = COPY $w1219 ; CHECK-NEXT: %t:gpr32 = COPY $w2220 ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv221 ; CHECK-NEXT: %select:gpr32 = CSINCWr %t, $wzr, 1, implicit $nzcv222 ; CHECK-NEXT: $w0 = COPY %select223 ; CHECK-NEXT: RET_ReallyLR implicit $w0224 %reg0:gpr(s32) = COPY $w0225 %reg1:gpr(s32) = COPY $w1226 %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1227 %t:gpr(s32) = COPY $w2228 %f:gpr(s32) = G_CONSTANT i32 1229 %select:gpr(s32) = G_SELECT %cmp, %t, %f230 $w0 = COPY %select(s32)231 RET_ReallyLR implicit $w0232...233---234name: csinc_f_neg_1235legalized: true236regBankSelected: true237tracksRegLiveness: true238body: |239 bb.0:240 liveins: $w0, $w1, $w2241 ; G_SELECT cc, t, -1 -> CSINC t, zreg, cc242 243 ; CHECK-LABEL: name: csinc_f_neg_1244 ; CHECK: liveins: $w0, $w1, $w2245 ; CHECK-NEXT: {{ $}}246 ; CHECK-NEXT: %reg0:gpr32 = COPY $w0247 ; CHECK-NEXT: %reg1:gpr32 = COPY $w1248 ; CHECK-NEXT: %t:gpr32 = COPY $w2249 ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv250 ; CHECK-NEXT: %select:gpr32 = CSINVWr %t, $wzr, 1, implicit $nzcv251 ; CHECK-NEXT: $w0 = COPY %select252 ; CHECK-NEXT: RET_ReallyLR implicit $w0253 %reg0:gpr(s32) = COPY $w0254 %reg1:gpr(s32) = COPY $w1255 %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1256 %t:gpr(s32) = COPY $w2257 %f:gpr(s32) = G_CONSTANT i32 -1258 %select:gpr(s32) = G_SELECT %cmp, %t, %f259 $w0 = COPY %select(s32)260 RET_ReallyLR implicit $w0261...262---263name: csinc_t_1_no_cmp264legalized: true265regBankSelected: true266tracksRegLiveness: true267body: |268 bb.0:269 liveins: $w0, $w1270 ; G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc271 272 ; CHECK-LABEL: name: csinc_t_1_no_cmp273 ; CHECK: liveins: $w0, $w1274 ; CHECK-NEXT: {{ $}}275 ; CHECK-NEXT: %reg0:gpr32 = COPY $w0276 ; CHECK-NEXT: %f:gpr32 = COPY $w1277 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv278 ; CHECK-NEXT: %select:gpr32 = CSINCWr %f, $wzr, 0, implicit $nzcv279 ; CHECK-NEXT: $w0 = COPY %select280 ; CHECK-NEXT: RET_ReallyLR implicit $w0281 %reg0:gpr(s32) = COPY $w0282 %t:gpr(s32) = G_CONSTANT i32 1283 %f:gpr(s32) = COPY $w1284 %select:gpr(s32) = G_SELECT %reg0, %t, %f285 $w0 = COPY %select(s32)286 RET_ReallyLR implicit $w0287 288...289---290name: csinc_f_1_no_cmp291legalized: true292regBankSelected: true293tracksRegLiveness: true294body: |295 bb.0:296 liveins: $w0, $w1297 ; G_SELECT cc, t, 1 -> CSINC t, zreg, cc298 299 ; CHECK-LABEL: name: csinc_f_1_no_cmp300 ; CHECK: liveins: $w0, $w1301 ; CHECK-NEXT: {{ $}}302 ; CHECK-NEXT: %reg0:gpr32 = COPY $w0303 ; CHECK-NEXT: %t:gpr32 = COPY $w1304 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv305 ; CHECK-NEXT: %select:gpr32 = CSINCWr %t, $wzr, 1, implicit $nzcv306 ; CHECK-NEXT: $w0 = COPY %select307 ; CHECK-NEXT: RET_ReallyLR implicit $w0308 %reg0:gpr(s32) = COPY $w0309 %t:gpr(s32) = COPY $w1310 %f:gpr(s32) = G_CONSTANT i32 1311 %select:gpr(s32) = G_SELECT %reg0, %t, %f312 $w0 = COPY %select(s32)313 RET_ReallyLR implicit $w0314 315...316---317name: csinc_t_1_no_cmp_s64318legalized: true319regBankSelected: true320tracksRegLiveness: true321body: |322 bb.0:323 liveins: $x0, $x1324 ; G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc325 326 ; CHECK-LABEL: name: csinc_t_1_no_cmp_s64327 ; CHECK: liveins: $x0, $x1328 ; CHECK-NEXT: {{ $}}329 ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0330 ; CHECK-NEXT: %cond:gpr32common = COPY %reg0.sub_32331 ; CHECK-NEXT: %f:gpr64 = COPY $x1332 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv333 ; CHECK-NEXT: %select:gpr64 = CSINCXr %f, $xzr, 0, implicit $nzcv334 ; CHECK-NEXT: $x0 = COPY %select335 ; CHECK-NEXT: RET_ReallyLR implicit $x0336 %reg0:gpr(s64) = COPY $x0337 %cond:gpr(s32) = G_TRUNC %reg0(s64)338 %t:gpr(s64) = G_CONSTANT i64 1339 %f:gpr(s64) = COPY $x1340 %select:gpr(s64) = G_SELECT %cond, %t, %f341 $x0 = COPY %select(s64)342 RET_ReallyLR implicit $x0343 344...345---346name: csneg_s32347legalized: true348regBankSelected: true349tracksRegLiveness: true350body: |351 bb.0:352 liveins: $w0, $w1, $w2353 ; G_SELECT cc, true, (G_SUB 0, x) -> CSNEG true, x, cc354 355 ; CHECK-LABEL: name: csneg_s32356 ; CHECK: liveins: $w0, $w1, $w2357 ; CHECK-NEXT: {{ $}}358 ; CHECK-NEXT: %reg0:gpr32 = COPY $w0359 ; CHECK-NEXT: %reg1:gpr32 = COPY $w1360 ; CHECK-NEXT: %t:gpr32 = COPY $w2361 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv362 ; CHECK-NEXT: %select:gpr32 = CSNEGWr %t, %reg1, 1, implicit $nzcv363 ; CHECK-NEXT: $w0 = COPY %select364 ; CHECK-NEXT: RET_ReallyLR implicit $w0365 %reg0:gpr(s32) = COPY $w0366 %reg1:gpr(s32) = COPY $w1367 %t:gpr(s32) = COPY $w2368 %zero:gpr(s32) = G_CONSTANT i32 0369 %sub:gpr(s32) = G_SUB %zero(s32), %reg1370 %select:gpr(s32) = G_SELECT %reg0, %t, %sub371 $w0 = COPY %select(s32)372 RET_ReallyLR implicit $w0373 374...375---376name: csneg_inverted_cc377legalized: true378regBankSelected: true379tracksRegLiveness: true380body: |381 bb.0:382 liveins: $w0, $w1, $w2383 ; G_SELECT cc, (G_SUB 0, %x), %false -> CSNEG %x, %false, inv_cc384 385 ; CHECK-LABEL: name: csneg_inverted_cc386 ; CHECK: liveins: $w0, $w1, $w2387 ; CHECK-NEXT: {{ $}}388 ; CHECK-NEXT: %reg0:gpr32 = COPY $w0389 ; CHECK-NEXT: %reg1:gpr32 = COPY $w1390 ; CHECK-NEXT: %f:gpr32 = COPY $w2391 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv392 ; CHECK-NEXT: %select:gpr32 = CSNEGWr %f, %reg1, 0, implicit $nzcv393 ; CHECK-NEXT: $w0 = COPY %select394 ; CHECK-NEXT: RET_ReallyLR implicit $w0395 %reg0:gpr(s32) = COPY $w0396 %reg1:gpr(s32) = COPY $w1397 %f:gpr(s32) = COPY $w2398 %zero:gpr(s32) = G_CONSTANT i32 0399 %sub:gpr(s32) = G_SUB %zero(s32), %reg1400 %select:gpr(s32) = G_SELECT %reg0, %sub, %f401 $w0 = COPY %select(s32)402 RET_ReallyLR implicit $w0403 404...405---406name: csneg_s64407legalized: true408regBankSelected: true409tracksRegLiveness: true410body: |411 bb.0:412 liveins: $x0, $x1, $x2413 ; G_SELECT cc, true, (G_SUB 0, x) -> CSNEG true, x, cc414 415 ; CHECK-LABEL: name: csneg_s64416 ; CHECK: liveins: $x0, $x1, $x2417 ; CHECK-NEXT: {{ $}}418 ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0419 ; CHECK-NEXT: %cond:gpr32common = COPY %reg0.sub_32420 ; CHECK-NEXT: %reg1:gpr64 = COPY $x1421 ; CHECK-NEXT: %t:gpr64 = COPY $x2422 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv423 ; CHECK-NEXT: %select:gpr64 = CSNEGXr %t, %reg1, 1, implicit $nzcv424 ; CHECK-NEXT: $x0 = COPY %select425 ; CHECK-NEXT: RET_ReallyLR implicit $x0426 %reg0:gpr(s64) = COPY $x0427 %cond:gpr(s32) = G_TRUNC %reg0(s64)428 %reg1:gpr(s64) = COPY $x1429 %t:gpr(s64) = COPY $x2430 %zero:gpr(s64) = G_CONSTANT i64 0431 %sub:gpr(s64) = G_SUB %zero(s64), %reg1432 %select:gpr(s64) = G_SELECT %cond, %t, %sub433 $x0 = COPY %select(s64)434 RET_ReallyLR implicit $x0435...436---437name: csneg_with_true_cst438legalized: true439regBankSelected: true440tracksRegLiveness: true441body: |442 bb.0:443 liveins: $w0, $w1, $w2444 ; We should prefer eliminating the G_SUB over eliminating the constant true445 ; value.446 447 ; CHECK-LABEL: name: csneg_with_true_cst448 ; CHECK: liveins: $w0, $w1, $w2449 ; CHECK-NEXT: {{ $}}450 ; CHECK-NEXT: %reg0:gpr32 = COPY $w0451 ; CHECK-NEXT: %t:gpr32 = MOVi32imm 1452 ; CHECK-NEXT: %reg2:gpr32 = COPY $w2453 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv454 ; CHECK-NEXT: %select:gpr32 = CSNEGWr %t, %reg2, 1, implicit $nzcv455 ; CHECK-NEXT: $w0 = COPY %select456 ; CHECK-NEXT: RET_ReallyLR implicit $w0457 %reg0:gpr(s32) = COPY $w0458 %reg1:gpr(s32) = COPY $w1459 %t:gpr(s32) = G_CONSTANT i32 1460 %zero:gpr(s32) = G_CONSTANT i32 0461 %reg2:gpr(s32) = COPY $w2462 %sub:gpr(s32) = G_SUB %zero(s32), %reg2463 %select:gpr(s32) = G_SELECT %reg0, %t, %sub464 $w0 = COPY %select(s32)465 RET_ReallyLR implicit $w0466...467---468name: csinv_s32469legalized: true470regBankSelected: true471tracksRegLiveness: true472body: |473 bb.0:474 liveins: $w0, $w1, $w2475 ; G_SELECT cc, true, (G_XOR x, -1) -> CSINV true, x, cc476 477 ; CHECK-LABEL: name: csinv_s32478 ; CHECK: liveins: $w0, $w1, $w2479 ; CHECK-NEXT: {{ $}}480 ; CHECK-NEXT: %reg0:gpr32 = COPY $w0481 ; CHECK-NEXT: %reg1:gpr32 = COPY $w1482 ; CHECK-NEXT: %t:gpr32 = COPY $w2483 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv484 ; CHECK-NEXT: %select:gpr32 = CSINVWr %t, %reg1, 1, implicit $nzcv485 ; CHECK-NEXT: $w0 = COPY %select486 ; CHECK-NEXT: RET_ReallyLR implicit $w0487 %reg0:gpr(s32) = COPY $w0488 %reg1:gpr(s32) = COPY $w1489 %t:gpr(s32) = COPY $w2490 %negative_one:gpr(s32) = G_CONSTANT i32 -1491 %xor:gpr(s32) = G_XOR %reg1(s32), %negative_one492 %select:gpr(s32) = G_SELECT %reg0, %t, %xor493 $w0 = COPY %select(s32)494 RET_ReallyLR implicit $w0495 496...497---498name: csinv_inverted_cc499legalized: true500regBankSelected: true501tracksRegLiveness: true502body: |503 bb.0:504 liveins: $w0, $w1, $w2505 ; G_SELECT cc, (G_XOR x, -1), %false -> CSINV %x, %false, inv_cc506 507 ; CHECK-LABEL: name: csinv_inverted_cc508 ; CHECK: liveins: $w0, $w1, $w2509 ; CHECK-NEXT: {{ $}}510 ; CHECK-NEXT: %reg0:gpr32 = COPY $w0511 ; CHECK-NEXT: %reg1:gpr32 = COPY $w1512 ; CHECK-NEXT: %f:gpr32 = COPY $w2513 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv514 ; CHECK-NEXT: %select:gpr32 = CSINVWr %f, %reg1, 0, implicit $nzcv515 ; CHECK-NEXT: $w0 = COPY %select516 ; CHECK-NEXT: RET_ReallyLR implicit $w0517 %reg0:gpr(s32) = COPY $w0518 %reg1:gpr(s32) = COPY $w1519 %f:gpr(s32) = COPY $w2520 %negative_one:gpr(s32) = G_CONSTANT i32 -1521 %xor:gpr(s32) = G_XOR %reg1(s32), %negative_one522 %select:gpr(s32) = G_SELECT %reg0, %xor, %f523 $w0 = COPY %select(s32)524 RET_ReallyLR implicit $w0525 526...527---528name: csinv_s64529legalized: true530regBankSelected: true531tracksRegLiveness: true532body: |533 bb.0:534 liveins: $x0, $x1, $x2535 ; G_SELECT cc, true, (G_XOR x, -1) -> CSINV true, x, cc536 537 ; CHECK-LABEL: name: csinv_s64538 ; CHECK: liveins: $x0, $x1, $x2539 ; CHECK-NEXT: {{ $}}540 ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0541 ; CHECK-NEXT: %reg1:gpr64 = COPY $x1542 ; CHECK-NEXT: %cond:gpr32common = COPY %reg0.sub_32543 ; CHECK-NEXT: %t:gpr64 = COPY $x2544 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv545 ; CHECK-NEXT: %select:gpr64 = CSINVXr %t, %reg1, 1, implicit $nzcv546 ; CHECK-NEXT: $x0 = COPY %select547 ; CHECK-NEXT: RET_ReallyLR implicit $x0548 %reg0:gpr(s64) = COPY $x0549 %reg1:gpr(s64) = COPY $x1550 %cond:gpr(s32) = G_TRUNC %reg0(s64)551 %t:gpr(s64) = COPY $x2552 %negative_one:gpr(s64) = G_CONSTANT i64 -1553 %xor:gpr(s64) = G_XOR %reg1(s64), %negative_one554 %select:gpr(s64) = G_SELECT %cond, %t, %xor555 $x0 = COPY %select(s64)556 RET_ReallyLR implicit $x0557 558...559---560name: xor_not_negative_one561legalized: true562regBankSelected: true563tracksRegLiveness: true564body: |565 bb.0:566 liveins: $x0, $x1, $x2567 ; zext(s32 -1) != s64 -1, so we can't fold it away.568 569 ; CHECK-LABEL: name: xor_not_negative_one570 ; CHECK: liveins: $x0, $x1, $x2571 ; CHECK-NEXT: {{ $}}572 ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0573 ; CHECK-NEXT: %reg1:gpr64 = COPY $x1574 ; CHECK-NEXT: %cond:gpr32common = COPY %reg0.sub_32575 ; CHECK-NEXT: %t:gpr64 = COPY $x2576 ; CHECK-NEXT: %negative_one:gpr32 = MOVi32imm -1577 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %negative_one, 0578 ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32579 ; CHECK-NEXT: %xor:gpr64 = EORXrr %reg1, %zext580 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv581 ; CHECK-NEXT: %select:gpr64 = CSELXr %t, %xor, 1, implicit $nzcv582 ; CHECK-NEXT: $x0 = COPY %select583 ; CHECK-NEXT: RET_ReallyLR implicit $x0584 %reg0:gpr(s64) = COPY $x0585 %reg1:gpr(s64) = COPY $x1586 %cond:gpr(s32) = G_TRUNC %reg0(s64)587 %t:gpr(s64) = COPY $x2588 %negative_one:gpr(s32) = G_CONSTANT i32 -1589 %zext:gpr(s64) = G_ZEXT %negative_one(s32)590 %xor:gpr(s64) = G_XOR %reg1(s64), %zext591 %select:gpr(s64) = G_SELECT %cond(s32), %t, %xor592 $x0 = COPY %select(s64)593 RET_ReallyLR implicit $x0594 595...596---597name: csinc_s32598legalized: true599regBankSelected: true600tracksRegLiveness: true601body: |602 bb.0:603 liveins: $w0, $w1, $w2604 ; G_SELECT cc, %true, (G_ADD %x, 1) -> CSINC %true, %x, cc605 ; CHECK-LABEL: name: csinc_s32606 ; CHECK: liveins: $w0, $w1, $w2607 ; CHECK-NEXT: {{ $}}608 ; CHECK-NEXT: %reg0:gpr32 = COPY $w0609 ; CHECK-NEXT: %reg1:gpr32 = COPY $w1610 ; CHECK-NEXT: %t:gpr32 = COPY $w2611 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv612 ; CHECK-NEXT: %select:gpr32 = CSINCWr %t, %reg1, 1, implicit $nzcv613 ; CHECK-NEXT: $w0 = COPY %select614 ; CHECK-NEXT: RET_ReallyLR implicit $w0615 %reg0:gpr(s32) = COPY $w0616 %reg1:gpr(s32) = COPY $w1617 %t:gpr(s32) = COPY $w2618 %one:gpr(s32) = G_CONSTANT i32 1619 %add:gpr(s32) = G_ADD %reg1(s32), %one620 %select:gpr(s32) = G_SELECT %reg0, %t, %add621 $w0 = COPY %select(s32)622 RET_ReallyLR implicit $w0623 624...625---626name: csinc_s32_inverted_cc627legalized: true628regBankSelected: true629tracksRegLiveness: true630body: |631 bb.0:632 liveins: $w0, $w1, $w2633 ; G_SELECT cc, (G_ADD %x, 1), %false -> CSINC %x, %false, inv_cc634 ; CHECK-LABEL: name: csinc_s32_inverted_cc635 ; CHECK: liveins: $w0, $w1, $w2636 ; CHECK-NEXT: {{ $}}637 ; CHECK-NEXT: %reg0:gpr32 = COPY $w0638 ; CHECK-NEXT: %reg1:gpr32 = COPY $w1639 ; CHECK-NEXT: %f:gpr32 = COPY $w2640 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv641 ; CHECK-NEXT: %select:gpr32 = CSINCWr %f, %reg1, 0, implicit $nzcv642 ; CHECK-NEXT: $w0 = COPY %select643 ; CHECK-NEXT: RET_ReallyLR implicit $w0644 %reg0:gpr(s32) = COPY $w0645 %reg1:gpr(s32) = COPY $w1646 %f:gpr(s32) = COPY $w2647 %one:gpr(s32) = G_CONSTANT i32 1648 %add:gpr(s32) = G_ADD %reg1(s32), %one649 %select:gpr(s32) = G_SELECT %reg0, %add, %f650 $w0 = COPY %select(s32)651 RET_ReallyLR implicit $w0652 653...654---655name: csinc_ptr_add656legalized: true657regBankSelected: true658tracksRegLiveness: true659body: |660 bb.0:661 liveins: $x0, $x1, $x2662 ; G_SELECT cc, %true, (G_PTR_ADD %x, 1) -> CSINC %true, %x, cc663 664 ; CHECK-LABEL: name: csinc_ptr_add665 ; CHECK: liveins: $x0, $x1, $x2666 ; CHECK-NEXT: {{ $}}667 ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0668 ; CHECK-NEXT: %reg1:gpr64 = COPY $x1669 ; CHECK-NEXT: %cond:gpr32common = COPY %reg0.sub_32670 ; CHECK-NEXT: %t:gpr64 = COPY $x2671 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv672 ; CHECK-NEXT: %select:gpr64 = CSINCXr %t, %reg1, 1, implicit $nzcv673 ; CHECK-NEXT: $x0 = COPY %select674 ; CHECK-NEXT: RET_ReallyLR implicit $x0675 %reg0:gpr(s64) = COPY $x0676 %reg1:gpr(p0) = COPY $x1677 %cond:gpr(s32) = G_TRUNC %reg0(s64)678 %t:gpr(p0) = COPY $x2679 %one:gpr(s64) = G_CONSTANT i64 1680 %ptr_add:gpr(p0) = G_PTR_ADD %reg1(p0), %one681 %select:gpr(p0) = G_SELECT %cond(s32), %t, %ptr_add682 $x0 = COPY %select(p0)683 RET_ReallyLR implicit $x0684 685...686---687name: binop_dont_optimize_twice688legalized: true689regBankSelected: true690tracksRegLiveness: true691body: |692 bb.0:693 liveins: $w0, $w1, $w2694 ; CHECK-LABEL: name: binop_dont_optimize_twice695 ; CHECK: liveins: $w0, $w1, $w2696 ; CHECK-NEXT: {{ $}}697 ; CHECK-NEXT: %reg0:gpr32 = COPY $w0698 ; CHECK-NEXT: %reg1:gpr32 = COPY $w1699 ; CHECK-NEXT: %reg2:gpr32 = COPY $w2700 ; CHECK-NEXT: %xor:gpr32 = ORNWrr $wzr, %reg1701 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv702 ; CHECK-NEXT: %select:gpr32 = CSNEGWr %xor, %reg2, 1, implicit $nzcv703 ; CHECK-NEXT: $w0 = COPY %select704 ; CHECK-NEXT: RET_ReallyLR implicit $w0705 %reg0:gpr(s32) = COPY $w0706 %reg1:gpr(s32) = COPY $w1707 %reg2:gpr(s32) = COPY $w2708 %f:gpr(s32) = COPY $w2709 %negative_one:gpr(s32) = G_CONSTANT i32 -1710 %xor:gpr(s32) = G_XOR %reg1(s32), %negative_one711 %zero:gpr(s32) = G_CONSTANT i32 0712 %sub:gpr(s32) = G_SUB %zero(s32), %reg2713 %select:gpr(s32) = G_SELECT %reg0, %xor, %sub714 $w0 = COPY %select(s32)715 RET_ReallyLR implicit $w0716