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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4--- |5 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"6 7 define void @sextload_s32_from_s16(ptr %addr) { ret void }8 define void @sextload_s32_from_s16_not_combined(ptr %addr) { ret void }9...10 11---12name: sextload_s32_from_s1613legalized: true14regBankSelected: true15 16body: |17 bb.0:18 liveins: $x019 20 ; CHECK-LABEL: name: sextload_s32_from_s1621 ; CHECK: liveins: $x022 ; CHECK-NEXT: {{ $}}23 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x024 ; CHECK-NEXT: [[LDRSHWui:%[0-9]+]]:gpr32 = LDRSHWui [[COPY]], 0 :: (load (s16) from %ir.addr)25 ; CHECK-NEXT: $w0 = COPY [[LDRSHWui]]26 %0:gpr(p0) = COPY $x027 %1:gpr(s32) = G_SEXTLOAD %0 :: (load (s16) from %ir.addr)28 $w0 = COPY %1(s32)29...30 31---32name: sextload_s32_from_s16_not_combined33legalized: true34regBankSelected: true35 36body: |37 bb.0:38 liveins: $x039 40 ; CHECK-LABEL: name: sextload_s32_from_s16_not_combined41 ; CHECK: liveins: $x042 ; CHECK-NEXT: {{ $}}43 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x044 ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.addr)45 ; CHECK-NEXT: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[LDRHHui]], 0, 1546 ; CHECK-NEXT: $w0 = COPY [[SBFMWri]]47 %0:gpr(p0) = COPY $x048 %1:gpr(s16) = G_LOAD %0 :: (load (s16) from %ir.addr)49 %2:gpr(s32) = G_SEXT %150 $w0 = COPY %2(s32)51...52