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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# WARNING: update_mir_test_checks.py does not include the constant pools output,3# so this test requires manual fixing up after running the script.4 5# RUN: llc -mtriple=aarch64-- -O0 -run-pass=instruction-select -verify-machineinstrs %s -global-isel-abort=1 -o - | FileCheck %s6--- |7 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"8 target triple = "aarch64"9 10 define <2 x float> @shuffle_v2f32(<2 x float> %a, <2 x float> %b) {11 %shuf = shufflevector <2 x float> %a, <2 x float> %b, <2 x i32> <i32 1, i32 0>12 ret <2 x float> %shuf13 }14 15 define <4 x i32> @shuffle_v4i32(<4 x i32> %a, <4 x i32> %b) {16 %shuf = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 3, i32 0>17 ret <4 x i32> %shuf18 }19 20 define <4 x i32> @shuffle_tbl_v4i32(<4 x i32> %a, <4 x i32> %b) {21 %shuf = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 7, i32 1, i32 0>22 ret <4 x i32> %shuf23 }24 25 define <2 x i64> @shuffle_v2i64(<2 x i64> %a, <2 x i64> %b) {26 %shuf = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> zeroinitializer27 ret <2 x i64> %shuf28 }29 30...31---32name: shuffle_v2f3233alignment: 434legalized: true35regBankSelected: true36tracksRegLiveness: true37body: |38 bb.1 (%ir-block.0):39 liveins: $d0, $d140 41 ; CHECK-LABEL: name: shuffle_v2f3242 ; CHECK: constants:43 ; CHECK: - id: 044 ; CHECK: value: '<8 x i8> <i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3>'45 ; CHECK: alignment: 846 ; CHECK: liveins: $d0, $d147 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d048 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d149 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.050 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.051 ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF52 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub53 ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF54 ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.dsub55 ; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 056 ; CHECK: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF57 ; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[LDRDui]], %subreg.dsub58 ; CHECK: [[TBLv16i8One:%[0-9]+]]:fpr128 = TBLv16i8One [[INSvi64lane]], [[INSERT_SUBREG2]]59 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[TBLv16i8One]].dsub60 ; CHECK: $d0 = COPY [[COPY2]]61 ; CHECK: RET_ReallyLR implicit $d062 %0:fpr(<2 x s32>) = COPY $d063 %1:fpr(<2 x s32>) = COPY $d164 %2:fpr(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(1, 0)65 $d0 = COPY %2(<2 x s32>)66 RET_ReallyLR implicit $d067 68...69---70name: shuffle_v4i3271alignment: 472legalized: true73regBankSelected: true74tracksRegLiveness: true75body: |76 bb.1 (%ir-block.0):77 liveins: $q0, $q178 79 ; CHECK-LABEL: name: shuffle_v4i3280 ; CHECK: constants:81 ; CHECK: value: '<16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 12, i8 13, i8 14, i8 15, i8 0, i8 1, i8 2, i8 3>'82 ; CHECK: alignment: 1683 ; CHECK: isTargetSpecific: false84 ; CHECK: liveins: $q0, $q185 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q086 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q187 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.088 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.089 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE [[COPY]], %subreg.qsub0, [[COPY1]], %subreg.qsub190 ; CHECK: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]]91 ; CHECK: $q0 = COPY [[TBLv16i8Two]]92 ; CHECK: RET_ReallyLR implicit $q093 %0:fpr(<4 x s32>) = COPY $q094 %1:fpr(<4 x s32>) = COPY $q195 %2:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(0, 1, 3, 0)96 $q0 = COPY %2(<4 x s32>)97 RET_ReallyLR implicit $q098 99...100---101name: shuffle_tbl_v4i32102alignment: 4103legalized: true104regBankSelected: true105tracksRegLiveness: true106body: |107 bb.1 (%ir-block.0):108 liveins: $q0, $q1109 110 ; CHECK-LABEL: name: shuffle_tbl_v4i32111 ; CHECK: constants:112 ; CHECK: value: '<16 x i8> <i8 20, i8 21, i8 22, i8 23, i8 28, i8 29, i8 30, i8 31, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3>'113 ; CHECK: alignment: 16114 ; CHECK: isTargetSpecific: false115 ; CHECK: liveins: $q0, $q1116 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0117 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1118 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0119 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0120 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE [[COPY]], %subreg.qsub0, [[COPY1]], %subreg.qsub1121 ; CHECK: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]]122 ; CHECK: $q0 = COPY [[TBLv16i8Two]]123 ; CHECK: RET_ReallyLR implicit $q0124 %0:fpr(<4 x s32>) = COPY $q0125 %1:fpr(<4 x s32>) = COPY $q1126 %2:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(5, 7, 1, 0)127 $q0 = COPY %2(<4 x s32>)128 RET_ReallyLR implicit $q0129 130...131---132name: shuffle_v2i64133alignment: 4134legalized: true135regBankSelected: true136tracksRegLiveness: true137body: |138 bb.1 (%ir-block.0):139 liveins: $q0, $q1140 141 ; CHECK-LABEL: name: shuffle_v2i64142 ; CHECK: constants:143 ; CHECK: value: '<16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>'144 ; CHECK: alignment: 16145 ; CHECK: isTargetSpecific: false146 ; CHECK: liveins: $q0, $q1147 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0148 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1149 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0150 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0151 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE [[COPY]], %subreg.qsub0, [[COPY1]], %subreg.qsub1152 ; CHECK: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]]153 ; CHECK: $q0 = COPY [[TBLv16i8Two]]154 ; CHECK: RET_ReallyLR implicit $q0155 %0:fpr(<2 x s64>) = COPY $q0156 %1:fpr(<2 x s64>) = COPY $q1157 %2:fpr(<2 x s64>) = G_SHUFFLE_VECTOR %0(<2 x s64>), %1, shufflemask(1, 0)158 $q0 = COPY %2(<2 x s64>)159 RET_ReallyLR implicit $q0160 161...162