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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4...5---6name: v8i8_ST2Twov8b7legalized: true8regBankSelected: true9tracksRegLiveness: true10body: |11 bb.0:12 liveins: $d0, $d1, $x013 14 ; CHECK-LABEL: name: v8i8_ST2Twov8b15 ; CHECK: liveins: $d0, $d1, $x016 ; CHECK-NEXT: {{ $}}17 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x018 ; CHECK-NEXT: %src1:fpr64 = COPY $d019 ; CHECK-NEXT: %src2:fpr64 = COPY $d120 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:dd = REG_SEQUENCE %src1, %subreg.dsub0, %src2, %subreg.dsub121 ; CHECK-NEXT: ST2Twov8b [[REG_SEQUENCE]], %ptr :: (store (<2 x s64>))22 ; CHECK-NEXT: RET_ReallyLR23 %ptr:gpr(p0) = COPY $x024 %src1:fpr(<8 x s8>) = COPY $d025 %src2:fpr(<8 x s8>) = COPY $d126 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<8 x s8>), %src2(<8 x s8>), %ptr(p0) :: (store (<2 x s64>))27 RET_ReallyLR28 29...30---31name: v16i8_ST2Twov16b32 33legalized: true34regBankSelected: true35tracksRegLiveness: true36body: |37 bb.0:38 liveins: $q0, $q1, $x039 40 ; CHECK-LABEL: name: v16i8_ST2Twov16b41 ; CHECK: liveins: $q0, $q1, $x042 ; CHECK-NEXT: {{ $}}43 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x044 ; CHECK-NEXT: %src1:fpr128 = COPY $q045 ; CHECK-NEXT: %src2:fpr128 = COPY $q146 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE %src1, %subreg.qsub0, %src2, %subreg.qsub147 ; CHECK-NEXT: ST2Twov16b [[REG_SEQUENCE]], %ptr :: (store (<4 x s64>))48 ; CHECK-NEXT: RET_ReallyLR49 %ptr:gpr(p0) = COPY $x050 %src1:fpr(<16 x s8>) = COPY $q051 %src2:fpr(<16 x s8>) = COPY $q152 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<16 x s8>), %src2(<16 x s8>), %ptr(p0) :: (store (<4 x s64>))53 RET_ReallyLR54 55...56---57name: v4i16_ST2Twov4h58 59legalized: true60regBankSelected: true61tracksRegLiveness: true62body: |63 bb.0:64 liveins: $d0, $d1, $x065 66 ; CHECK-LABEL: name: v4i16_ST2Twov4h67 ; CHECK: liveins: $d0, $d1, $x068 ; CHECK-NEXT: {{ $}}69 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x070 ; CHECK-NEXT: %src1:fpr64 = COPY $d071 ; CHECK-NEXT: %src2:fpr64 = COPY $d172 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:dd = REG_SEQUENCE %src1, %subreg.dsub0, %src2, %subreg.dsub173 ; CHECK-NEXT: ST2Twov4h [[REG_SEQUENCE]], %ptr :: (store (<2 x s64>))74 ; CHECK-NEXT: RET_ReallyLR75 %ptr:gpr(p0) = COPY $x076 %src1:fpr(<4 x s16>) = COPY $d077 %src2:fpr(<4 x s16>) = COPY $d178 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<4 x s16>), %src2(<4 x s16>), %ptr(p0) :: (store (<2 x s64>))79 RET_ReallyLR80 81...82---83name: v8i16_ST2Twov8h84 85legalized: true86regBankSelected: true87tracksRegLiveness: true88body: |89 bb.0:90 liveins: $q0, $q1, $x091 92 ; CHECK-LABEL: name: v8i16_ST2Twov8h93 ; CHECK: liveins: $q0, $q1, $x094 ; CHECK-NEXT: {{ $}}95 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x096 ; CHECK-NEXT: %src1:fpr128 = COPY $q097 ; CHECK-NEXT: %src2:fpr128 = COPY $q198 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE %src1, %subreg.qsub0, %src2, %subreg.qsub199 ; CHECK-NEXT: ST2Twov8h [[REG_SEQUENCE]], %ptr :: (store (<4 x s64>))100 ; CHECK-NEXT: RET_ReallyLR101 %ptr:gpr(p0) = COPY $x0102 %src1:fpr(<8 x s16>) = COPY $q0103 %src2:fpr(<8 x s16>) = COPY $q1104 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<8 x s16>), %src2(<8 x s16>), %ptr(p0) :: (store (<4 x s64>))105 RET_ReallyLR106 107...108---109name: v2i32_ST2Twov2s110legalized: true111regBankSelected: true112tracksRegLiveness: true113body: |114 bb.0:115 liveins: $d0, $d1, $x0116 117 ; CHECK-LABEL: name: v2i32_ST2Twov2s118 ; CHECK: liveins: $d0, $d1, $x0119 ; CHECK-NEXT: {{ $}}120 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x0121 ; CHECK-NEXT: %src1:fpr64 = COPY $d0122 ; CHECK-NEXT: %src2:fpr64 = COPY $d1123 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:dd = REG_SEQUENCE %src1, %subreg.dsub0, %src2, %subreg.dsub1124 ; CHECK-NEXT: ST2Twov2s [[REG_SEQUENCE]], %ptr :: (store (<2 x s64>))125 ; CHECK-NEXT: RET_ReallyLR126 %ptr:gpr(p0) = COPY $x0127 %src1:fpr(<2 x s32>) = COPY $d0128 %src2:fpr(<2 x s32>) = COPY $d1129 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<2 x s32>), %src2(<2 x s32>), %ptr(p0) :: (store (<2 x s64>))130 RET_ReallyLR131 132...133---134name: v4i32_ST2Twov4s135legalized: true136regBankSelected: true137tracksRegLiveness: true138body: |139 bb.0:140 liveins: $q0, $q1, $x0141 142 ; CHECK-LABEL: name: v4i32_ST2Twov4s143 ; CHECK: liveins: $q0, $q1, $x0144 ; CHECK-NEXT: {{ $}}145 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x0146 ; CHECK-NEXT: %src1:fpr128 = COPY $q0147 ; CHECK-NEXT: %src2:fpr128 = COPY $q1148 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE %src1, %subreg.qsub0, %src2, %subreg.qsub1149 ; CHECK-NEXT: ST2Twov4s [[REG_SEQUENCE]], %ptr :: (store (<4 x s64>))150 ; CHECK-NEXT: RET_ReallyLR151 %ptr:gpr(p0) = COPY $x0152 %src1:fpr(<4 x s32>) = COPY $q0153 %src2:fpr(<4 x s32>) = COPY $q1154 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<4 x s32>), %src2(<4 x s32>), %ptr(p0) :: (store (<4 x s64>))155 RET_ReallyLR156 157...158---159name: v2i64_ST2Twov2d_s64_elts160legalized: true161regBankSelected: true162tracksRegLiveness: true163body: |164 bb.0:165 liveins: $q0, $q1, $x0166 167 ; CHECK-LABEL: name: v2i64_ST2Twov2d_s64_elts168 ; CHECK: liveins: $q0, $q1, $x0169 ; CHECK-NEXT: {{ $}}170 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x0171 ; CHECK-NEXT: %src1:fpr128 = COPY $q0172 ; CHECK-NEXT: %src2:fpr128 = COPY $q1173 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE %src1, %subreg.qsub0, %src2, %subreg.qsub1174 ; CHECK-NEXT: ST2Twov2d [[REG_SEQUENCE]], %ptr :: (store (<4 x s64>))175 ; CHECK-NEXT: RET_ReallyLR176 %ptr:gpr(p0) = COPY $x0177 %src1:fpr(<2 x s64>) = COPY $q0178 %src2:fpr(<2 x s64>) = COPY $q1179 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<2 x s64>), %src2(<2 x s64>), %ptr(p0) :: (store (<4 x s64>))180 RET_ReallyLR181 182...183---184name: v2i64_ST2Twov2d_s64_p0_elts185legalized: true186regBankSelected: true187tracksRegLiveness: true188body: |189 bb.0:190 liveins: $q0, $q1, $x0191 192 ; CHECK-LABEL: name: v2i64_ST2Twov2d_s64_p0_elts193 ; CHECK: liveins: $q0, $q1, $x0194 ; CHECK-NEXT: {{ $}}195 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x0196 ; CHECK-NEXT: %src1:fpr128 = COPY $q0197 ; CHECK-NEXT: %src2:fpr128 = COPY $q1198 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE %src1, %subreg.qsub0, %src2, %subreg.qsub1199 ; CHECK-NEXT: ST2Twov2d [[REG_SEQUENCE]], %ptr :: (store (<4 x s64>))200 ; CHECK-NEXT: RET_ReallyLR201 %ptr:gpr(p0) = COPY $x0202 %src1:fpr(<2 x p0>) = COPY $q0203 %src2:fpr(<2 x p0>) = COPY $q1204 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<2 x p0>), %src2(<2 x p0>), %ptr(p0) :: (store (<4 x s64>))205 RET_ReallyLR206 207...208---209name: v1i64_ST1Twov1d_s64210legalized: true211regBankSelected: true212tracksRegLiveness: true213body: |214 bb.0:215 liveins: $x0, $x1, $x2216 217 ; CHECK-LABEL: name: v1i64_ST1Twov1d_s64218 ; CHECK: liveins: $x0, $x1, $x2219 ; CHECK-NEXT: {{ $}}220 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x0221 ; CHECK-NEXT: %src1:gpr64all = COPY $x0222 ; CHECK-NEXT: %src2:gpr64all = COPY $x1223 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:dd = REG_SEQUENCE %src1, %subreg.dsub0, %src2, %subreg.dsub1224 ; CHECK-NEXT: ST1Twov1d [[REG_SEQUENCE]], %ptr :: (store (<2 x s64>))225 ; CHECK-NEXT: RET_ReallyLR226 %ptr:gpr(p0) = COPY $x0227 %src1:gpr(s64) = COPY $x0228 %src2:gpr(s64) = COPY $x1229 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(s64), %src2(s64), %ptr(p0) :: (store (<2 x s64>))230 RET_ReallyLR231 232...233---234name: v1i64_ST1Twov1d_p0235legalized: true236regBankSelected: true237tracksRegLiveness: true238body: |239 bb.0:240 liveins: $x0, $x1, $x2241 242 ; CHECK-LABEL: name: v1i64_ST1Twov1d_p0243 ; CHECK: liveins: $x0, $x1, $x2244 ; CHECK-NEXT: {{ $}}245 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x0246 ; CHECK-NEXT: %src1:gpr64all = COPY $x0247 ; CHECK-NEXT: %src2:gpr64all = COPY $x1248 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:dd = REG_SEQUENCE %src1, %subreg.dsub0, %src2, %subreg.dsub1249 ; CHECK-NEXT: ST1Twov1d [[REG_SEQUENCE]], %ptr :: (store (<2 x s64>))250 ; CHECK-NEXT: RET_ReallyLR251 %ptr:gpr(p0) = COPY $x0252 %src1:gpr(p0) = COPY $x0253 %src2:gpr(p0) = COPY $x1254 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(p0), %src2(p0), %ptr(p0) :: (store (<2 x s64>))255 RET_ReallyLR256 257...258