126 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4--- |5 define i32 @test_store_release_i64(i32 %a, ptr %addr) {6 ret i32 %a7 }8 9 define i32 @test_store_release_i32(i32 %a, ptr %addr) {10 ret i32 %a11 }12 13 define void @test_store_release_i8(i32, i8 %val, ptr %addr) { ret void }14 define void @test_store_release_i16(i32, i16 %val, ptr %addr) { ret void }15...16---17name: test_store_release_i6418alignment: 419legalized: true20regBankSelected: true21tracksRegLiveness: true22body: |23 bb.0:24 liveins: $w0, $x1, $x225 26 ; CHECK-LABEL: name: test_store_release_i6427 ; CHECK: liveins: $w0, $x1, $x228 ; CHECK-NEXT: {{ $}}29 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x130 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x231 ; CHECK-NEXT: early-clobber %2:gpr32 = STLXRX [[COPY]], [[COPY1]] :: (volatile store (s64) into %ir.addr)32 ; CHECK-NEXT: $w0 = COPY %233 ; CHECK-NEXT: RET_ReallyLR implicit $w034 %1:gpr(s64) = COPY $x135 %2:gpr(p0) = COPY $x236 %3:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %1(s64), %2(p0) :: (volatile store (s64) into %ir.addr)37 $w0 = COPY %3(s32)38 RET_ReallyLR implicit $w039 40...41---42name: test_store_release_i3243alignment: 444legalized: true45regBankSelected: true46tracksRegLiveness: true47body: |48 bb.0:49 liveins: $w0, $w1, $x250 ; CHECK-LABEL: name: test_store_release_i3251 ; CHECK: liveins: $w0, $w1, $x252 ; CHECK-NEXT: {{ $}}53 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w154 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x255 ; CHECK-NEXT: early-clobber %3:gpr32 = STLXRW [[COPY]], [[COPY1]] :: (volatile store (s32) into %ir.addr)56 ; CHECK-NEXT: $w0 = COPY %357 ; CHECK-NEXT: RET_ReallyLR implicit $w058 %1:gpr(s32) = COPY $w159 %2:gpr(p0) = COPY $x260 %3:gpr(s64) = G_ZEXT %1(s32)61 %4:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %3(s64), %2(p0) :: (volatile store (s32) into %ir.addr)62 $w0 = COPY %4(s32)63 RET_ReallyLR implicit $w064 65...66---67name: test_store_release_i868alignment: 469legalized: true70regBankSelected: true71tracksRegLiveness: true72body: |73 bb.0:74 liveins: $w0, $w1, $x275 76 ; CHECK-LABEL: name: test_store_release_i877 ; CHECK: liveins: $w0, $w1, $x278 ; CHECK-NEXT: {{ $}}79 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w180 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x281 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF82 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_3283 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_3284 ; CHECK-NEXT: early-clobber %5:gpr32 = STLXRB [[COPY2]], [[COPY1]] :: (volatile store (s8) into %ir.addr)85 ; CHECK-NEXT: $w0 = COPY %586 ; CHECK-NEXT: RET_ReallyLR implicit $w087 %3:gpr(s32) = COPY $w188 %2:gpr(p0) = COPY $x289 %6:gpr(s64) = G_CONSTANT i64 25590 %7:gpr(s64) = G_ANYEXT %3(s32)91 %4:gpr(s64) = G_AND %7, %692 %5:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %4(s64), %2(p0) :: (volatile store (s8) into %ir.addr)93 $w0 = COPY %5(s32)94 RET_ReallyLR implicit $w095 96...97---98name: test_store_release_i1699alignment: 4100legalized: true101regBankSelected: true102tracksRegLiveness: true103body: |104 bb.0:105 liveins: $w0, $w1, $x2106 107 ; CHECK-LABEL: name: test_store_release_i16108 ; CHECK: liveins: $w0, $w1, $x2109 ; CHECK-NEXT: {{ $}}110 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1111 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2112 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF113 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32114 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_32115 ; CHECK-NEXT: early-clobber %5:gpr32 = STLXRH [[COPY2]], [[COPY1]] :: (volatile store (s16) into %ir.addr)116 ; CHECK-NEXT: $w0 = COPY %5117 ; CHECK-NEXT: RET_ReallyLR implicit $w0118 %3:gpr(s32) = COPY $w1119 %2:gpr(p0) = COPY $x2120 %6:gpr(s64) = G_CONSTANT i64 65535121 %7:gpr(s64) = G_ANYEXT %3(s32)122 %4:gpr(s64) = G_AND %7, %6123 %5:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %4(s64), %2(p0) :: (volatile store (s16) into %ir.addr)124 $w0 = COPY %5(s32)125 RET_ReallyLR implicit $w0126