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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4--- |5 define void @test_store_i8(i32, i8 %val, ptr %addr) { ret void }6 define void @test_store_i16(i32, i16 %val, ptr %addr) { ret void }7 define void @test_store_i32(i32, i32 %val, ptr %addr) { ret void }8 define void @test_store_i64(i32, i64 %val, ptr %addr) { ret void }9...10---11name: test_store_i812alignment: 413legalized: true14regBankSelected: true15tracksRegLiveness: true16machineFunctionInfo: {}17body: |18 bb.0:19 liveins: $w0, $w1, $x220 21 ; CHECK-LABEL: name: test_store_i822 ; CHECK: liveins: $w0, $w1, $x223 ; CHECK-NEXT: {{ $}}24 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w125 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x226 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF27 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_3228 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_3229 ; CHECK-NEXT: early-clobber %5:gpr32 = STXRB [[COPY2]], [[COPY1]] :: (volatile store (s8) into %ir.addr)30 ; CHECK-NEXT: $w0 = COPY %531 ; CHECK-NEXT: RET_ReallyLR implicit $w032 %3:gpr(s32) = COPY $w133 %2:gpr(p0) = COPY $x234 %6:gpr(s64) = G_CONSTANT i64 25535 %7:gpr(s64) = G_ANYEXT %3(s32)36 %4:gpr(s64) = G_AND %7, %637 %5:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %4(s64), %2(p0) :: (volatile store (s8) into %ir.addr)38 $w0 = COPY %5(s32)39 RET_ReallyLR implicit $w040 41...42---43name: test_store_i1644alignment: 445legalized: true46regBankSelected: true47tracksRegLiveness: true48machineFunctionInfo: {}49body: |50 bb.0:51 liveins: $w0, $w1, $x252 53 ; CHECK-LABEL: name: test_store_i1654 ; CHECK: liveins: $w0, $w1, $x255 ; CHECK-NEXT: {{ $}}56 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w157 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x258 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF59 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_3260 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_3261 ; CHECK-NEXT: early-clobber %5:gpr32 = STXRH [[COPY2]], [[COPY1]] :: (volatile store (s16) into %ir.addr)62 ; CHECK-NEXT: $w0 = COPY %563 ; CHECK-NEXT: RET_ReallyLR implicit $w064 %3:gpr(s32) = COPY $w165 %2:gpr(p0) = COPY $x266 %6:gpr(s64) = G_CONSTANT i64 6553567 %7:gpr(s64) = G_ANYEXT %3(s32)68 %4:gpr(s64) = G_AND %7, %669 %5:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %4(s64), %2(p0) :: (volatile store (s16) into %ir.addr)70 $w0 = COPY %5(s32)71 RET_ReallyLR implicit $w072 73...74---75name: test_store_i3276alignment: 477legalized: true78regBankSelected: true79tracksRegLiveness: true80machineFunctionInfo: {}81body: |82 bb.0:83 liveins: $w0, $w1, $x284 85 ; CHECK-LABEL: name: test_store_i3286 ; CHECK: liveins: $w0, $w1, $x287 ; CHECK-NEXT: {{ $}}88 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w189 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x290 ; CHECK-NEXT: early-clobber %3:gpr32 = STXRW [[COPY]], [[COPY1]] :: (volatile store (s32) into %ir.addr)91 ; CHECK-NEXT: $w0 = COPY %392 ; CHECK-NEXT: RET_ReallyLR implicit $w093 %1:gpr(s32) = COPY $w194 %2:gpr(p0) = COPY $x295 %3:gpr(s64) = G_ZEXT %1(s32)96 %4:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %3(s64), %2(p0) :: (volatile store (s32) into %ir.addr)97 $w0 = COPY %4(s32)98 RET_ReallyLR implicit $w099 100...101---102name: test_store_i64103alignment: 4104legalized: true105regBankSelected: true106tracksRegLiveness: true107machineFunctionInfo: {}108body: |109 bb.0:110 liveins: $w0, $x1, $x2111 112 ; CHECK-LABEL: name: test_store_i64113 ; CHECK: liveins: $w0, $x1, $x2114 ; CHECK-NEXT: {{ $}}115 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x1116 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2117 ; CHECK-NEXT: early-clobber %2:gpr32 = STXRX [[COPY]], [[COPY1]] :: (volatile store (s64) into %ir.addr)118 ; CHECK-NEXT: $w0 = COPY %2119 ; CHECK-NEXT: RET_ReallyLR implicit $w0120 %1:gpr(s64) = COPY $x1121 %2:gpr(p0) = COPY $x2122 %3:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %1(s64), %2(p0) :: (volatile store (s64) into %ir.addr)123 $w0 = COPY %3(s32)124 RET_ReallyLR implicit $w0125 126...127