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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3#4# Test that we can produce a TBNZ when we have a slt compare against 0.5#6# The bit tested should be the size of the test register minus 1.7#8 9...10---11name: tbnzx_slt12alignment: 413legalized: true14regBankSelected: true15body: |16 ; CHECK-LABEL: name: tbnzx_slt17 ; CHECK: bb.0:18 ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)19 ; CHECK-NEXT: liveins: $x020 ; CHECK-NEXT: {{ $}}21 ; CHECK-NEXT: %copy:gpr64 = COPY $x022 ; CHECK-NEXT: TBNZX %copy, 63, %bb.123 ; CHECK-NEXT: B %bb.024 ; CHECK-NEXT: {{ $}}25 ; CHECK-NEXT: bb.1:26 ; CHECK-NEXT: RET_ReallyLR27 bb.0:28 successors: %bb.0, %bb.129 liveins: $x030 %copy:gpr(s64) = COPY $x031 %zero:gpr(s64) = G_CONSTANT i64 032 %cmp:gpr(s32) = G_ICMP intpred(slt), %copy(s64), %zero33 G_BRCOND %cmp, %bb.134 G_BR %bb.035 bb.1:36 RET_ReallyLR37 38...39---40name: tbnzw_slt41alignment: 442legalized: true43regBankSelected: true44body: |45 ; CHECK-LABEL: name: tbnzw_slt46 ; CHECK: bb.0:47 ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)48 ; CHECK-NEXT: liveins: $x049 ; CHECK-NEXT: {{ $}}50 ; CHECK-NEXT: %copy:gpr32 = COPY $w051 ; CHECK-NEXT: TBNZW %copy, 31, %bb.152 ; CHECK-NEXT: B %bb.053 ; CHECK-NEXT: {{ $}}54 ; CHECK-NEXT: bb.1:55 ; CHECK-NEXT: RET_ReallyLR56 bb.0:57 successors: %bb.0, %bb.158 liveins: $x059 %copy:gpr(s32) = COPY $w060 %zero:gpr(s32) = G_CONSTANT i32 061 %cmp:gpr(s32) = G_ICMP intpred(slt), %copy(s32), %zero62 G_BRCOND %cmp, %bb.163 G_BR %bb.064 bb.1:65 RET_ReallyLR66 67...68---69name: tbnzx_sge70alignment: 471legalized: true72regBankSelected: true73body: |74 ; CHECK-LABEL: name: tbnzx_sge75 ; CHECK: bb.0:76 ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)77 ; CHECK-NEXT: liveins: $x078 ; CHECK-NEXT: {{ $}}79 ; CHECK-NEXT: %copy:gpr64 = COPY $x080 ; CHECK-NEXT: TBZX %copy, 63, %bb.181 ; CHECK-NEXT: B %bb.082 ; CHECK-NEXT: {{ $}}83 ; CHECK-NEXT: bb.1:84 ; CHECK-NEXT: RET_ReallyLR85 bb.0:86 successors: %bb.0, %bb.187 liveins: $x088 %copy:gpr(s64) = COPY $x089 %zero:gpr(s64) = G_CONSTANT i64 090 %cmp:gpr(s32) = G_ICMP intpred(sge), %copy(s64), %zero91 G_BRCOND %cmp, %bb.192 G_BR %bb.093 bb.1:94 RET_ReallyLR95 96...97---98name: tbnzw_sge99alignment: 4100legalized: true101regBankSelected: true102body: |103 ; CHECK-LABEL: name: tbnzw_sge104 ; CHECK: bb.0:105 ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)106 ; CHECK-NEXT: liveins: $x0107 ; CHECK-NEXT: {{ $}}108 ; CHECK-NEXT: %copy:gpr32 = COPY $w0109 ; CHECK-NEXT: TBZW %copy, 31, %bb.1110 ; CHECK-NEXT: B %bb.0111 ; CHECK-NEXT: {{ $}}112 ; CHECK-NEXT: bb.1:113 ; CHECK-NEXT: RET_ReallyLR114 bb.0:115 successors: %bb.0, %bb.1116 liveins: $x0117 %copy:gpr(s32) = COPY $w0118 %zero:gpr(s32) = G_CONSTANT i32 0119 %cmp:gpr(s32) = G_ICMP intpred(sge), %copy(s32), %zero120 G_BRCOND %cmp, %bb.1121 G_BR %bb.0122 bb.1:123 RET_ReallyLR124 125...126---127name: no_tbnz_not_zero128alignment: 4129legalized: true130regBankSelected: true131body: |132 ; CHECK-LABEL: name: no_tbnz_not_zero133 ; CHECK: bb.0:134 ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)135 ; CHECK-NEXT: liveins: $x0136 ; CHECK-NEXT: {{ $}}137 ; CHECK-NEXT: %copy:gpr32sp = COPY $w0138 ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %copy, 1, 0, implicit-def $nzcv139 ; CHECK-NEXT: Bcc 11, %bb.1, implicit $nzcv140 ; CHECK-NEXT: B %bb.0141 ; CHECK-NEXT: {{ $}}142 ; CHECK-NEXT: bb.1:143 ; CHECK-NEXT: RET_ReallyLR144 bb.0:145 successors: %bb.0, %bb.1146 liveins: $x0147 %copy:gpr(s32) = COPY $w0148 %one:gpr(s32) = G_CONSTANT i32 1149 %cmp:gpr(s32) = G_ICMP intpred(slt), %copy(s32), %one150 G_BRCOND %cmp, %bb.1151 G_BR %bb.0152 bb.1:153 RET_ReallyLR154 155...156---157name: dont_fold_and158alignment: 4159legalized: true160regBankSelected: true161body: |162 ; CHECK-LABEL: name: dont_fold_and163 ; CHECK: bb.0:164 ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)165 ; CHECK-NEXT: liveins: $x0166 ; CHECK-NEXT: {{ $}}167 ; CHECK-NEXT: %copy:gpr64 = COPY $x0168 ; CHECK-NEXT: [[ANDSXri:%[0-9]+]]:gpr64 = ANDSXri %copy, 8000, implicit-def $nzcv169 ; CHECK-NEXT: Bcc 4, %bb.1, implicit $nzcv170 ; CHECK-NEXT: B %bb.0171 ; CHECK-NEXT: {{ $}}172 ; CHECK-NEXT: bb.1:173 ; CHECK-NEXT: RET_ReallyLR174 bb.0:175 successors: %bb.0, %bb.1176 liveins: $x0177 %copy:gpr(s64) = COPY $x0178 %bit:gpr(s64) = G_CONSTANT i64 8179 %zero:gpr(s64) = G_CONSTANT i64 0180 %c:gpr(s64) = G_CONSTANT i64 8181 %and:gpr(s64) = G_AND %copy, %bit182 %cmp:gpr(s32) = G_ICMP intpred(slt), %and(s64), %zero183 G_BRCOND %cmp, %bb.1184 G_BR %bb.0185 bb.1:186 RET_ReallyLR187 188...189---190name: dont_commute191alignment: 4192legalized: true193regBankSelected: true194body: |195 ; CHECK-LABEL: name: dont_commute196 ; CHECK: bb.0:197 ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)198 ; CHECK-NEXT: liveins: $x0199 ; CHECK-NEXT: {{ $}}200 ; CHECK-NEXT: %copy:gpr64 = COPY $x0201 ; CHECK-NEXT: %zero:gpr64 = COPY $xzr202 ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %zero, %copy, implicit-def $nzcv203 ; CHECK-NEXT: Bcc 11, %bb.1, implicit $nzcv204 ; CHECK-NEXT: B %bb.0205 ; CHECK-NEXT: {{ $}}206 ; CHECK-NEXT: bb.1:207 ; CHECK-NEXT: RET_ReallyLR208 bb.0:209 successors: %bb.0, %bb.1210 liveins: $x0211 %copy:gpr(s64) = COPY $x0212 %zero:gpr(s64) = G_CONSTANT i64 0213 %cmp:gpr(s32) = G_ICMP intpred(slt), %zero, %copy(s64)214 G_BRCOND %cmp, %bb.1215 G_BR %bb.0216 bb.1:217 RET_ReallyLR218