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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3#4# Test that we can select G_TRN1 and G_TRN2.5#6# Each testcase is named based off of the instruction which should be selected.7 8...9---10name: TRN1v2i3211alignment: 412legalized: true13regBankSelected: true14tracksRegLiveness: true15body: |16 bb.0:17 liveins: $d0, $d118 ; CHECK-LABEL: name: TRN1v2i3219 ; CHECK: liveins: $d0, $d120 ; CHECK-NEXT: {{ $}}21 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d022 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d123 ; CHECK-NEXT: [[TRN1v2i32_:%[0-9]+]]:fpr64 = TRN1v2i32 [[COPY]], [[COPY1]]24 ; CHECK-NEXT: $d0 = COPY [[TRN1v2i32_]]25 ; CHECK-NEXT: RET_ReallyLR implicit $d026 %0:fpr(<2 x s32>) = COPY $d027 %1:fpr(<2 x s32>) = COPY $d128 %2:fpr(<2 x s32>) = G_TRN1 %0, %129 $d0 = COPY %2(<2 x s32>)30 RET_ReallyLR implicit $d031 32...33---34name: TRN1v2i6435alignment: 436legalized: true37regBankSelected: true38tracksRegLiveness: true39body: |40 bb.0:41 liveins: $q0, $q142 ; CHECK-LABEL: name: TRN1v2i6443 ; CHECK: liveins: $q0, $q144 ; CHECK-NEXT: {{ $}}45 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q046 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q147 ; CHECK-NEXT: [[TRN1v2i64_:%[0-9]+]]:fpr128 = TRN1v2i64 [[COPY]], [[COPY1]]48 ; CHECK-NEXT: $q0 = COPY [[TRN1v2i64_]]49 ; CHECK-NEXT: RET_ReallyLR implicit $q050 %0:fpr(<2 x s64>) = COPY $q051 %1:fpr(<2 x s64>) = COPY $q152 %2:fpr(<2 x s64>) = G_TRN1 %0, %153 $q0 = COPY %2(<2 x s64>)54 RET_ReallyLR implicit $q055 56...57---58name: TRN1v4i1659alignment: 460legalized: true61regBankSelected: true62tracksRegLiveness: true63body: |64 bb.0:65 liveins: $d0, $d166 ; CHECK-LABEL: name: TRN1v4i1667 ; CHECK: liveins: $d0, $d168 ; CHECK-NEXT: {{ $}}69 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d070 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d171 ; CHECK-NEXT: [[TRN1v4i16_:%[0-9]+]]:fpr64 = TRN1v4i16 [[COPY]], [[COPY1]]72 ; CHECK-NEXT: $d0 = COPY [[TRN1v4i16_]]73 ; CHECK-NEXT: RET_ReallyLR implicit $d074 %0:fpr(<4 x s16>) = COPY $d075 %1:fpr(<4 x s16>) = COPY $d176 %2:fpr(<4 x s16>) = G_TRN1 %0, %177 $d0 = COPY %2(<4 x s16>)78 RET_ReallyLR implicit $d079 80...81---82name: TRN1v4i3283alignment: 484legalized: true85regBankSelected: true86tracksRegLiveness: true87body: |88 bb.0:89 liveins: $q0, $q190 ; CHECK-LABEL: name: TRN1v4i3291 ; CHECK: liveins: $q0, $q192 ; CHECK-NEXT: {{ $}}93 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q094 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q195 ; CHECK-NEXT: [[TRN1v4i32_:%[0-9]+]]:fpr128 = TRN1v4i32 [[COPY]], [[COPY1]]96 ; CHECK-NEXT: $q0 = COPY [[TRN1v4i32_]]97 ; CHECK-NEXT: RET_ReallyLR implicit $q098 %0:fpr(<4 x s32>) = COPY $q099 %1:fpr(<4 x s32>) = COPY $q1100 %2:fpr(<4 x s32>) = G_TRN1 %0, %1101 $q0 = COPY %2(<4 x s32>)102 RET_ReallyLR implicit $q0103 104...105---106name: TRN1v8i8107alignment: 4108legalized: true109regBankSelected: true110tracksRegLiveness: true111body: |112 bb.0:113 liveins: $d0, $d1114 ; CHECK-LABEL: name: TRN1v8i8115 ; CHECK: liveins: $d0, $d1116 ; CHECK-NEXT: {{ $}}117 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0118 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1119 ; CHECK-NEXT: [[TRN1v8i8_:%[0-9]+]]:fpr64 = TRN1v8i8 [[COPY]], [[COPY1]]120 ; CHECK-NEXT: $d0 = COPY [[TRN1v8i8_]]121 ; CHECK-NEXT: RET_ReallyLR implicit $d0122 %0:fpr(<8 x s8>) = COPY $d0123 %1:fpr(<8 x s8>) = COPY $d1124 %2:fpr(<8 x s8>) = G_TRN1 %0, %1125 $d0 = COPY %2(<8 x s8>)126 RET_ReallyLR implicit $d0127 128...129---130name: TRN1v8i16131alignment: 4132legalized: true133regBankSelected: true134tracksRegLiveness: true135body: |136 bb.0:137 liveins: $q0, $q1138 ; CHECK-LABEL: name: TRN1v8i16139 ; CHECK: liveins: $q0, $q1140 ; CHECK-NEXT: {{ $}}141 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0142 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1143 ; CHECK-NEXT: [[TRN1v8i16_:%[0-9]+]]:fpr128 = TRN1v8i16 [[COPY]], [[COPY1]]144 ; CHECK-NEXT: $q0 = COPY [[TRN1v8i16_]]145 ; CHECK-NEXT: RET_ReallyLR implicit $q0146 %0:fpr(<8 x s16>) = COPY $q0147 %1:fpr(<8 x s16>) = COPY $q1148 %2:fpr(<8 x s16>) = G_TRN1 %0, %1149 $q0 = COPY %2(<8 x s16>)150 RET_ReallyLR implicit $q0151 152...153---154name: TRN1v16i8155alignment: 4156legalized: true157regBankSelected: true158tracksRegLiveness: true159body: |160 bb.0:161 liveins: $q0, $q1162 ; CHECK-LABEL: name: TRN1v16i8163 ; CHECK: liveins: $q0, $q1164 ; CHECK-NEXT: {{ $}}165 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0166 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1167 ; CHECK-NEXT: [[TRN1v16i8_:%[0-9]+]]:fpr128 = TRN1v16i8 [[COPY]], [[COPY1]]168 ; CHECK-NEXT: $q0 = COPY [[TRN1v16i8_]]169 ; CHECK-NEXT: RET_ReallyLR implicit $q0170 %0:fpr(<16 x s8>) = COPY $q0171 %1:fpr(<16 x s8>) = COPY $q1172 %2:fpr(<16 x s8>) = G_TRN1 %0, %1173 $q0 = COPY %2(<16 x s8>)174 RET_ReallyLR implicit $q0175 176...177---178name: TRN2v2i32179alignment: 4180legalized: true181regBankSelected: true182tracksRegLiveness: true183body: |184 bb.0:185 liveins: $d0, $d1186 ; CHECK-LABEL: name: TRN2v2i32187 ; CHECK: liveins: $d0, $d1188 ; CHECK-NEXT: {{ $}}189 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0190 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1191 ; CHECK-NEXT: [[TRN2v2i32_:%[0-9]+]]:fpr64 = TRN2v2i32 [[COPY]], [[COPY1]]192 ; CHECK-NEXT: $d0 = COPY [[TRN2v2i32_]]193 ; CHECK-NEXT: RET_ReallyLR implicit $d0194 %0:fpr(<2 x s32>) = COPY $d0195 %1:fpr(<2 x s32>) = COPY $d1196 %2:fpr(<2 x s32>) = G_TRN2 %0, %1197 $d0 = COPY %2(<2 x s32>)198 RET_ReallyLR implicit $d0199 200...201---202name: TRN2v2i64203alignment: 4204legalized: true205regBankSelected: true206tracksRegLiveness: true207body: |208 bb.0:209 liveins: $q0, $q1210 ; CHECK-LABEL: name: TRN2v2i64211 ; CHECK: liveins: $q0, $q1212 ; CHECK-NEXT: {{ $}}213 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0214 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1215 ; CHECK-NEXT: [[TRN2v2i64_:%[0-9]+]]:fpr128 = TRN2v2i64 [[COPY]], [[COPY1]]216 ; CHECK-NEXT: $q0 = COPY [[TRN2v2i64_]]217 ; CHECK-NEXT: RET_ReallyLR implicit $q0218 %0:fpr(<2 x s64>) = COPY $q0219 %1:fpr(<2 x s64>) = COPY $q1220 %2:fpr(<2 x s64>) = G_TRN2 %0, %1221 $q0 = COPY %2(<2 x s64>)222 RET_ReallyLR implicit $q0223 224...225---226name: TRN2v4i16227alignment: 4228legalized: true229regBankSelected: true230tracksRegLiveness: true231body: |232 bb.0:233 liveins: $d0, $d1234 ; CHECK-LABEL: name: TRN2v4i16235 ; CHECK: liveins: $d0, $d1236 ; CHECK-NEXT: {{ $}}237 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0238 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1239 ; CHECK-NEXT: [[TRN2v4i16_:%[0-9]+]]:fpr64 = TRN2v4i16 [[COPY]], [[COPY1]]240 ; CHECK-NEXT: $d0 = COPY [[TRN2v4i16_]]241 ; CHECK-NEXT: RET_ReallyLR implicit $d0242 %0:fpr(<4 x s16>) = COPY $d0243 %1:fpr(<4 x s16>) = COPY $d1244 %2:fpr(<4 x s16>) = G_TRN2 %0, %1245 $d0 = COPY %2(<4 x s16>)246 RET_ReallyLR implicit $d0247 248...249---250name: TRN2v4i32251alignment: 4252legalized: true253regBankSelected: true254tracksRegLiveness: true255body: |256 bb.0:257 liveins: $q0, $q1258 ; CHECK-LABEL: name: TRN2v4i32259 ; CHECK: liveins: $q0, $q1260 ; CHECK-NEXT: {{ $}}261 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0262 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1263 ; CHECK-NEXT: [[TRN2v4i32_:%[0-9]+]]:fpr128 = TRN2v4i32 [[COPY]], [[COPY1]]264 ; CHECK-NEXT: $q0 = COPY [[TRN2v4i32_]]265 ; CHECK-NEXT: RET_ReallyLR implicit $q0266 %0:fpr(<4 x s32>) = COPY $q0267 %1:fpr(<4 x s32>) = COPY $q1268 %2:fpr(<4 x s32>) = G_TRN2 %0, %1269 $q0 = COPY %2(<4 x s32>)270 RET_ReallyLR implicit $q0271 272...273---274name: TRN2v8i8275alignment: 4276legalized: true277regBankSelected: true278tracksRegLiveness: true279body: |280 bb.0:281 liveins: $d0, $d1282 ; CHECK-LABEL: name: TRN2v8i8283 ; CHECK: liveins: $d0, $d1284 ; CHECK-NEXT: {{ $}}285 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0286 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1287 ; CHECK-NEXT: [[TRN2v8i8_:%[0-9]+]]:fpr64 = TRN2v8i8 [[COPY]], [[COPY1]]288 ; CHECK-NEXT: $d0 = COPY [[TRN2v8i8_]]289 ; CHECK-NEXT: RET_ReallyLR implicit $d0290 %0:fpr(<8 x s8>) = COPY $d0291 %1:fpr(<8 x s8>) = COPY $d1292 %2:fpr(<8 x s8>) = G_TRN2 %0, %1293 $d0 = COPY %2(<8 x s8>)294 RET_ReallyLR implicit $d0295 296...297---298name: TRN2v8i16299alignment: 4300legalized: true301regBankSelected: true302tracksRegLiveness: true303body: |304 bb.0:305 liveins: $q0, $q1306 ; CHECK-LABEL: name: TRN2v8i16307 ; CHECK: liveins: $q0, $q1308 ; CHECK-NEXT: {{ $}}309 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0310 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1311 ; CHECK-NEXT: [[TRN2v8i16_:%[0-9]+]]:fpr128 = TRN2v8i16 [[COPY]], [[COPY1]]312 ; CHECK-NEXT: $q0 = COPY [[TRN2v8i16_]]313 ; CHECK-NEXT: RET_ReallyLR implicit $q0314 %0:fpr(<8 x s16>) = COPY $q0315 %1:fpr(<8 x s16>) = COPY $q1316 %2:fpr(<8 x s16>) = G_TRN2 %0, %1317 $q0 = COPY %2(<8 x s16>)318 RET_ReallyLR implicit $q0319 320...321---322name: TRN2v16i8323alignment: 4324legalized: true325regBankSelected: true326tracksRegLiveness: true327body: |328 bb.0:329 liveins: $q0, $q1330 ; CHECK-LABEL: name: TRN2v16i8331 ; CHECK: liveins: $q0, $q1332 ; CHECK-NEXT: {{ $}}333 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0334 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1335 ; CHECK-NEXT: [[TRN2v16i8_:%[0-9]+]]:fpr128 = TRN2v16i8 [[COPY]], [[COPY1]]336 ; CHECK-NEXT: $q0 = COPY [[TRN2v16i8_]]337 ; CHECK-NEXT: RET_ReallyLR implicit $q0338 %0:fpr(<16 x s8>) = COPY $q0339 %1:fpr(<16 x s8>) = COPY $q1340 %2:fpr(<16 x s8>) = G_TRN2 %0, %1341 $q0 = COPY %2(<16 x s8>)342 RET_ReallyLR implicit $q0343