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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=1 %s -o - | FileCheck %s3 4---5name: truncstore_atomic_326alignment: 47legalized: true8regBankSelected: true9tracksRegLiveness: true10liveins:11 - { reg: '$x0' }12 - { reg: '$w1' }13body: |14 ; CHECK-LABEL: name: truncstore_atomic_3215 ; CHECK: bb.0:16 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)17 ; CHECK-NEXT: liveins: $w1, $x018 ; CHECK-NEXT: {{ $}}19 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x020 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w121 ; CHECK-NEXT: TBNZW [[COPY1]], 0, %bb.222 ; CHECK-NEXT: B %bb.123 ; CHECK-NEXT: {{ $}}24 ; CHECK-NEXT: bb.1:25 ; CHECK-NEXT: successors: %bb.2(0x80000000)26 ; CHECK-NEXT: {{ $}}27 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 428 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_3229 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]].sub_3230 ; CHECK-NEXT: STLRW [[COPY2]], [[COPY]] :: (store release (s32))31 ; CHECK-NEXT: {{ $}}32 ; CHECK-NEXT: bb.2:33 ; CHECK-NEXT: RET_ReallyLR34 bb.1:35 liveins: $w1, $x036 37 %0:gpr(p0) = COPY $x038 %3:gpr(s32) = COPY $w139 G_BRCOND %3, %bb.340 G_BR %bb.241 42 bb.2:43 %8:gpr(s64) = G_CONSTANT i64 444 G_STORE %8(s64), %0(p0) :: (store release (s32))45 46 bb.3:47 RET_ReallyLR48 49...50---51name: truncstore_atomic_1652alignment: 453legalized: true54regBankSelected: true55tracksRegLiveness: true56liveins:57 - { reg: '$x0' }58 - { reg: '$w1' }59body: |60 ; CHECK-LABEL: name: truncstore_atomic_1661 ; CHECK: bb.0:62 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)63 ; CHECK-NEXT: liveins: $w1, $x064 ; CHECK-NEXT: {{ $}}65 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x066 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w167 ; CHECK-NEXT: TBNZW [[COPY1]], 0, %bb.268 ; CHECK-NEXT: B %bb.169 ; CHECK-NEXT: {{ $}}70 ; CHECK-NEXT: bb.1:71 ; CHECK-NEXT: successors: %bb.2(0x80000000)72 ; CHECK-NEXT: {{ $}}73 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 474 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_3275 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]].sub_3276 ; CHECK-NEXT: STLRH [[COPY2]], [[COPY]] :: (store release (s16))77 ; CHECK-NEXT: {{ $}}78 ; CHECK-NEXT: bb.2:79 ; CHECK-NEXT: RET_ReallyLR80 bb.1:81 liveins: $w1, $x082 83 %0:gpr(p0) = COPY $x084 %3:gpr(s32) = COPY $w185 G_BRCOND %3, %bb.386 G_BR %bb.287 88 bb.2:89 %8:gpr(s64) = G_CONSTANT i64 490 G_STORE %8(s64), %0(p0) :: (store release (s16))91 92 bb.3:93 RET_ReallyLR94 95...96---97name: truncstore_atomic_898alignment: 499legalized: true100regBankSelected: true101tracksRegLiveness: true102liveins:103 - { reg: '$x0' }104 - { reg: '$w1' }105body: |106 ; CHECK-LABEL: name: truncstore_atomic_8107 ; CHECK: bb.0:108 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)109 ; CHECK-NEXT: liveins: $w1, $x0110 ; CHECK-NEXT: {{ $}}111 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0112 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1113 ; CHECK-NEXT: TBNZW [[COPY1]], 0, %bb.2114 ; CHECK-NEXT: B %bb.1115 ; CHECK-NEXT: {{ $}}116 ; CHECK-NEXT: bb.1:117 ; CHECK-NEXT: successors: %bb.2(0x80000000)118 ; CHECK-NEXT: {{ $}}119 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 4120 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32121 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]].sub_32122 ; CHECK-NEXT: STLRB [[COPY2]], [[COPY]] :: (store release (s8))123 ; CHECK-NEXT: {{ $}}124 ; CHECK-NEXT: bb.2:125 ; CHECK-NEXT: RET_ReallyLR126 bb.1:127 liveins: $w1, $x0128 129 %0:gpr(p0) = COPY $x0130 %3:gpr(s32) = COPY $w1131 G_BRCOND %3, %bb.3132 G_BR %bb.2133 134 bb.2:135 %8:gpr(s64) = G_CONSTANT i64 4136 G_STORE %8(s64), %0(p0) :: (store release (s8))137 138 bb.3:139 RET_ReallyLR140 141...142