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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2#3# Check that we can select G_UZP1 and G_UZP2 via the tablegen importer.4#5# RUN: llc -mtriple aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s6 7...8---9name: uzp1_v4s3210legalized: true11regBankSelected: true12tracksRegLiveness: true13body: |14 bb.1.entry:15 liveins: $q0, $q116 17 ; CHECK-LABEL: name: uzp1_v4s3218 ; CHECK: liveins: $q0, $q119 ; CHECK-NEXT: {{ $}}20 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q021 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q122 ; CHECK-NEXT: [[UZP1v4i32_:%[0-9]+]]:fpr128 = UZP1v4i32 [[COPY]], [[COPY1]]23 ; CHECK-NEXT: $q0 = COPY [[UZP1v4i32_]]24 ; CHECK-NEXT: RET_ReallyLR implicit $q025 %0:fpr(<4 x s32>) = COPY $q026 %1:fpr(<4 x s32>) = COPY $q127 %2:fpr(<4 x s32>) = G_UZP1 %0, %128 $q0 = COPY %2(<4 x s32>)29 RET_ReallyLR implicit $q030 31...32---33name: uzp2_v4s3234legalized: true35regBankSelected: true36tracksRegLiveness: true37body: |38 bb.1.entry:39 liveins: $q0, $q140 41 ; CHECK-LABEL: name: uzp2_v4s3242 ; CHECK: liveins: $q0, $q143 ; CHECK-NEXT: {{ $}}44 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q045 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q146 ; CHECK-NEXT: [[UZP2v4i32_:%[0-9]+]]:fpr128 = UZP2v4i32 [[COPY]], [[COPY1]]47 ; CHECK-NEXT: $q0 = COPY [[UZP2v4i32_]]48 ; CHECK-NEXT: RET_ReallyLR implicit $q049 %0:fpr(<4 x s32>) = COPY $q050 %1:fpr(<4 x s32>) = COPY $q151 %2:fpr(<4 x s32>) = G_UZP2 %0, %152 $q0 = COPY %2(<4 x s32>)53 RET_ReallyLR implicit $q054 55...56