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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4--- |5  source_filename = "icmp-autogen-tests-with-ne.ll"6  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"7  target triple = "aarch64"8 9  define <2 x i1> @test_v2i64_eq(<2 x i64> %v1, <2 x i64> %v2) {10    %cmp = icmp eq <2 x i64> %v1, %v211    ret <2 x i1> %cmp12  }13 14  define <4 x i1> @test_v4i32_eq(<4 x i32> %v1, <4 x i32> %v2) {15    %cmp = icmp eq <4 x i32> %v1, %v216    ret <4 x i1> %cmp17  }18 19  define <2 x i1> @test_v2i32_eq(<2 x i32> %v1, <2 x i32> %v2) {20    %cmp = icmp eq <2 x i32> %v1, %v221    ret <2 x i1> %cmp22  }23 24  define <2 x i1> @test_v2i16_eq(<2 x i16> %v1, <2 x i16> %v2) {25    %cmp = icmp eq <2 x i16> %v1, %v226    ret <2 x i1> %cmp27  }28 29  define <8 x i1> @test_v8i16_eq(<8 x i16> %v1, <8 x i16> %v2) {30    %cmp = icmp eq <8 x i16> %v1, %v231    ret <8 x i1> %cmp32  }33 34  define <4 x i1> @test_v4i16_eq(<4 x i16> %v1, <4 x i16> %v2) {35    %cmp = icmp eq <4 x i16> %v1, %v236    ret <4 x i1> %cmp37  }38 39  define <16 x i1> @test_v16i8_eq(<16 x i8> %v1, <16 x i8> %v2) {40    %cmp = icmp eq <16 x i8> %v1, %v241    ret <16 x i1> %cmp42  }43 44  define <8 x i1> @test_v8i8_eq(<8 x i8> %v1, <8 x i8> %v2) {45    %cmp = icmp eq <8 x i8> %v1, %v246    ret <8 x i1> %cmp47  }48 49  define <2 x i1> @test_v2i64_ugt(<2 x i64> %v1, <2 x i64> %v2) {50    %cmp = icmp ugt <2 x i64> %v1, %v251    ret <2 x i1> %cmp52  }53 54  define <4 x i1> @test_v4i32_ugt(<4 x i32> %v1, <4 x i32> %v2) {55    %cmp = icmp ugt <4 x i32> %v1, %v256    ret <4 x i1> %cmp57  }58 59  define <2 x i1> @test_v2i32_ugt(<2 x i32> %v1, <2 x i32> %v2) {60    %cmp = icmp ugt <2 x i32> %v1, %v261    ret <2 x i1> %cmp62  }63 64  define <2 x i1> @test_v2i16_ugt(<2 x i16> %v1, <2 x i16> %v2) {65    %cmp = icmp ugt <2 x i16> %v1, %v266    ret <2 x i1> %cmp67  }68 69  define <8 x i1> @test_v8i16_ugt(<8 x i16> %v1, <8 x i16> %v2) {70    %cmp = icmp ugt <8 x i16> %v1, %v271    ret <8 x i1> %cmp72  }73 74  define <4 x i1> @test_v4i16_ugt(<4 x i16> %v1, <4 x i16> %v2) {75    %cmp = icmp ugt <4 x i16> %v1, %v276    ret <4 x i1> %cmp77  }78 79  define <16 x i1> @test_v16i8_ugt(<16 x i8> %v1, <16 x i8> %v2) {80    %cmp = icmp ugt <16 x i8> %v1, %v281    ret <16 x i1> %cmp82  }83 84  define <8 x i1> @test_v8i8_ugt(<8 x i8> %v1, <8 x i8> %v2) {85    %cmp = icmp ugt <8 x i8> %v1, %v286    ret <8 x i1> %cmp87  }88 89  define <2 x i1> @test_v2i64_uge(<2 x i64> %v1, <2 x i64> %v2) {90    %cmp = icmp uge <2 x i64> %v1, %v291    ret <2 x i1> %cmp92  }93 94  define <4 x i1> @test_v4i32_uge(<4 x i32> %v1, <4 x i32> %v2) {95    %cmp = icmp uge <4 x i32> %v1, %v296    ret <4 x i1> %cmp97  }98 99  define <2 x i1> @test_v2i32_uge(<2 x i32> %v1, <2 x i32> %v2) {100    %cmp = icmp uge <2 x i32> %v1, %v2101    ret <2 x i1> %cmp102  }103 104  define <2 x i1> @test_v2i16_uge(<2 x i16> %v1, <2 x i16> %v2) {105    %cmp = icmp uge <2 x i16> %v1, %v2106    ret <2 x i1> %cmp107  }108 109  define <8 x i1> @test_v8i16_uge(<8 x i16> %v1, <8 x i16> %v2) {110    %cmp = icmp uge <8 x i16> %v1, %v2111    ret <8 x i1> %cmp112  }113 114  define <4 x i1> @test_v4i16_uge(<4 x i16> %v1, <4 x i16> %v2) {115    %cmp = icmp uge <4 x i16> %v1, %v2116    ret <4 x i1> %cmp117  }118 119  define <16 x i1> @test_v16i8_uge(<16 x i8> %v1, <16 x i8> %v2) {120    %cmp = icmp uge <16 x i8> %v1, %v2121    ret <16 x i1> %cmp122  }123 124  define <8 x i1> @test_v8i8_uge(<8 x i8> %v1, <8 x i8> %v2) {125    %cmp = icmp uge <8 x i8> %v1, %v2126    ret <8 x i1> %cmp127  }128 129  define <2 x i1> @test_v2i64_ult(<2 x i64> %v1, <2 x i64> %v2) {130    %cmp = icmp ult <2 x i64> %v1, %v2131    ret <2 x i1> %cmp132  }133 134  define <4 x i1> @test_v4i32_ult(<4 x i32> %v1, <4 x i32> %v2) {135    %cmp = icmp ult <4 x i32> %v1, %v2136    ret <4 x i1> %cmp137  }138 139  define <2 x i1> @test_v2i32_ult(<2 x i32> %v1, <2 x i32> %v2) {140    %cmp = icmp ult <2 x i32> %v1, %v2141    ret <2 x i1> %cmp142  }143 144  define <2 x i1> @test_v2i16_ult(<2 x i16> %v1, <2 x i16> %v2) {145    %cmp = icmp ult <2 x i16> %v1, %v2146    ret <2 x i1> %cmp147  }148 149  define <8 x i1> @test_v8i16_ult(<8 x i16> %v1, <8 x i16> %v2) {150    %cmp = icmp ult <8 x i16> %v1, %v2151    ret <8 x i1> %cmp152  }153 154  define <4 x i1> @test_v4i16_ult(<4 x i16> %v1, <4 x i16> %v2) {155    %cmp = icmp ult <4 x i16> %v1, %v2156    ret <4 x i1> %cmp157  }158 159  define <16 x i1> @test_v16i8_ult(<16 x i8> %v1, <16 x i8> %v2) {160    %cmp = icmp ult <16 x i8> %v1, %v2161    ret <16 x i1> %cmp162  }163 164  define <8 x i1> @test_v8i8_ult(<8 x i8> %v1, <8 x i8> %v2) {165    %cmp = icmp ult <8 x i8> %v1, %v2166    ret <8 x i1> %cmp167  }168 169  define <2 x i1> @test_v2i64_ule(<2 x i64> %v1, <2 x i64> %v2) {170    %cmp = icmp ule <2 x i64> %v1, %v2171    ret <2 x i1> %cmp172  }173 174  define <4 x i1> @test_v4i32_ule(<4 x i32> %v1, <4 x i32> %v2) {175    %cmp = icmp ule <4 x i32> %v1, %v2176    ret <4 x i1> %cmp177  }178 179  define <2 x i1> @test_v2i32_ule(<2 x i32> %v1, <2 x i32> %v2) {180    %cmp = icmp ule <2 x i32> %v1, %v2181    ret <2 x i1> %cmp182  }183 184  define <2 x i1> @test_v2i16_ule(<2 x i16> %v1, <2 x i16> %v2) {185    %cmp = icmp ule <2 x i16> %v1, %v2186    ret <2 x i1> %cmp187  }188 189  define <8 x i1> @test_v8i16_ule(<8 x i16> %v1, <8 x i16> %v2) {190    %cmp = icmp ule <8 x i16> %v1, %v2191    ret <8 x i1> %cmp192  }193 194  define <4 x i1> @test_v4i16_ule(<4 x i16> %v1, <4 x i16> %v2) {195    %cmp = icmp ule <4 x i16> %v1, %v2196    ret <4 x i1> %cmp197  }198 199  define <16 x i1> @test_v16i8_ule(<16 x i8> %v1, <16 x i8> %v2) {200    %cmp = icmp ule <16 x i8> %v1, %v2201    ret <16 x i1> %cmp202  }203 204  define <8 x i1> @test_v8i8_ule(<8 x i8> %v1, <8 x i8> %v2) {205    %cmp = icmp ule <8 x i8> %v1, %v2206    ret <8 x i1> %cmp207  }208 209  define <2 x i1> @test_v2i64_sgt(<2 x i64> %v1, <2 x i64> %v2) {210    %cmp = icmp sgt <2 x i64> %v1, %v2211    ret <2 x i1> %cmp212  }213 214  define <4 x i1> @test_v4i32_sgt(<4 x i32> %v1, <4 x i32> %v2) {215    %cmp = icmp sgt <4 x i32> %v1, %v2216    ret <4 x i1> %cmp217  }218 219  define <2 x i1> @test_v2i32_sgt(<2 x i32> %v1, <2 x i32> %v2) {220    %cmp = icmp sgt <2 x i32> %v1, %v2221    ret <2 x i1> %cmp222  }223 224  define <2 x i1> @test_v2i16_sgt(<2 x i16> %v1, <2 x i16> %v2) {225    %cmp = icmp sgt <2 x i16> %v1, %v2226    ret <2 x i1> %cmp227  }228 229  define <8 x i1> @test_v8i16_sgt(<8 x i16> %v1, <8 x i16> %v2) {230    %cmp = icmp sgt <8 x i16> %v1, %v2231    ret <8 x i1> %cmp232  }233 234  define <4 x i1> @test_v4i16_sgt(<4 x i16> %v1, <4 x i16> %v2) {235    %cmp = icmp sgt <4 x i16> %v1, %v2236    ret <4 x i1> %cmp237  }238 239  define <16 x i1> @test_v16i8_sgt(<16 x i8> %v1, <16 x i8> %v2) {240    %cmp = icmp sgt <16 x i8> %v1, %v2241    ret <16 x i1> %cmp242  }243 244  define <8 x i1> @test_v8i8_sgt(<8 x i8> %v1, <8 x i8> %v2) {245    %cmp = icmp sgt <8 x i8> %v1, %v2246    ret <8 x i1> %cmp247  }248 249  define <2 x i1> @test_v2i64_sge(<2 x i64> %v1, <2 x i64> %v2) {250    %cmp = icmp sge <2 x i64> %v1, %v2251    ret <2 x i1> %cmp252  }253 254  define <4 x i1> @test_v4i32_sge(<4 x i32> %v1, <4 x i32> %v2) {255    %cmp = icmp sge <4 x i32> %v1, %v2256    ret <4 x i1> %cmp257  }258 259  define <2 x i1> @test_v2i32_sge(<2 x i32> %v1, <2 x i32> %v2) {260    %cmp = icmp sge <2 x i32> %v1, %v2261    ret <2 x i1> %cmp262  }263 264  define <2 x i1> @test_v2i16_sge(<2 x i16> %v1, <2 x i16> %v2) {265    %cmp = icmp sge <2 x i16> %v1, %v2266    ret <2 x i1> %cmp267  }268 269  define <8 x i1> @test_v8i16_sge(<8 x i16> %v1, <8 x i16> %v2) {270    %cmp = icmp sge <8 x i16> %v1, %v2271    ret <8 x i1> %cmp272  }273 274  define <4 x i1> @test_v4i16_sge(<4 x i16> %v1, <4 x i16> %v2) {275    %cmp = icmp sge <4 x i16> %v1, %v2276    ret <4 x i1> %cmp277  }278 279  define <16 x i1> @test_v16i8_sge(<16 x i8> %v1, <16 x i8> %v2) {280    %cmp = icmp sge <16 x i8> %v1, %v2281    ret <16 x i1> %cmp282  }283 284  define <8 x i1> @test_v8i8_sge(<8 x i8> %v1, <8 x i8> %v2) {285    %cmp = icmp sge <8 x i8> %v1, %v2286    ret <8 x i1> %cmp287  }288 289  define <2 x i1> @test_v2i64_slt(<2 x i64> %v1, <2 x i64> %v2) {290    %cmp = icmp slt <2 x i64> %v1, %v2291    ret <2 x i1> %cmp292  }293 294  define <4 x i1> @test_v4i32_slt(<4 x i32> %v1, <4 x i32> %v2) {295    %cmp = icmp slt <4 x i32> %v1, %v2296    ret <4 x i1> %cmp297  }298 299  define <2 x i1> @test_v2i32_slt(<2 x i32> %v1, <2 x i32> %v2) {300    %cmp = icmp slt <2 x i32> %v1, %v2301    ret <2 x i1> %cmp302  }303 304  define <2 x i1> @test_v2i16_slt(<2 x i16> %v1, <2 x i16> %v2) {305    %cmp = icmp slt <2 x i16> %v1, %v2306    ret <2 x i1> %cmp307  }308 309  define <8 x i1> @test_v8i16_slt(<8 x i16> %v1, <8 x i16> %v2) {310    %cmp = icmp slt <8 x i16> %v1, %v2311    ret <8 x i1> %cmp312  }313 314  define <4 x i1> @test_v4i16_slt(<4 x i16> %v1, <4 x i16> %v2) {315    %cmp = icmp slt <4 x i16> %v1, %v2316    ret <4 x i1> %cmp317  }318 319  define <16 x i1> @test_v16i8_slt(<16 x i8> %v1, <16 x i8> %v2) {320    %cmp = icmp slt <16 x i8> %v1, %v2321    ret <16 x i1> %cmp322  }323 324  define <8 x i1> @test_v8i8_slt(<8 x i8> %v1, <8 x i8> %v2) {325    %cmp = icmp slt <8 x i8> %v1, %v2326    ret <8 x i1> %cmp327  }328 329  define <2 x i1> @test_v2i64_sle(<2 x i64> %v1, <2 x i64> %v2) {330    %cmp = icmp sle <2 x i64> %v1, %v2331    ret <2 x i1> %cmp332  }333 334  define <4 x i1> @test_v4i32_sle(<4 x i32> %v1, <4 x i32> %v2) {335    %cmp = icmp sle <4 x i32> %v1, %v2336    ret <4 x i1> %cmp337  }338 339  define <2 x i1> @test_v2i32_sle(<2 x i32> %v1, <2 x i32> %v2) {340    %cmp = icmp sle <2 x i32> %v1, %v2341    ret <2 x i1> %cmp342  }343 344  define <2 x i1> @test_v2i16_sle(<2 x i16> %v1, <2 x i16> %v2) {345    %cmp = icmp sle <2 x i16> %v1, %v2346    ret <2 x i1> %cmp347  }348 349  define <8 x i1> @test_v8i16_sle(<8 x i16> %v1, <8 x i16> %v2) {350    %cmp = icmp sle <8 x i16> %v1, %v2351    ret <8 x i1> %cmp352  }353 354  define <4 x i1> @test_v4i16_sle(<4 x i16> %v1, <4 x i16> %v2) {355    %cmp = icmp sle <4 x i16> %v1, %v2356    ret <4 x i1> %cmp357  }358 359  define <16 x i1> @test_v16i8_sle(<16 x i8> %v1, <16 x i8> %v2) {360    %cmp = icmp sle <16 x i8> %v1, %v2361    ret <16 x i1> %cmp362  }363 364  define <8 x i1> @test_v8i8_sle(<8 x i8> %v1, <8 x i8> %v2) {365    %cmp = icmp sle <8 x i8> %v1, %v2366    ret <8 x i1> %cmp367  }368 369...370---371name:            test_v2i64_eq372alignment:       4373legalized:       true374regBankSelected: true375tracksRegLiveness: true376registers:377  - { id: 0, class: fpr }378  - { id: 1, class: fpr }379  - { id: 2, class: _ }380  - { id: 3, class: fpr }381  - { id: 4, class: fpr }382machineFunctionInfo: {}383body:             |384  bb.1 (%ir-block.0):385    liveins: $q0, $q1386 387    ; CHECK-LABEL: name: test_v2i64_eq388    ; CHECK: liveins: $q0, $q1389    ; CHECK-NEXT: {{  $}}390    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0391    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1392    ; CHECK-NEXT: [[CMEQv2i64_:%[0-9]+]]:fpr128 = CMEQv2i64 [[COPY]], [[COPY1]]393    ; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMEQv2i64_]]394    ; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]]395    ; CHECK-NEXT: RET_ReallyLR implicit $d0396    %0:fpr(<2 x s64>) = COPY $q0397    %1:fpr(<2 x s64>) = COPY $q1398    %4:fpr(<2 x s64>) = G_ICMP intpred(eq), %0(<2 x s64>), %1399    %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)400    $d0 = COPY %3(<2 x s32>)401    RET_ReallyLR implicit $d0402 403...404---405name:            test_v4i32_eq406alignment:       4407legalized:       true408regBankSelected: true409tracksRegLiveness: true410registers:411  - { id: 0, class: fpr }412  - { id: 1, class: fpr }413  - { id: 2, class: _ }414  - { id: 3, class: fpr }415  - { id: 4, class: fpr }416machineFunctionInfo: {}417body:             |418  bb.1 (%ir-block.0):419    liveins: $q0, $q1420 421    ; CHECK-LABEL: name: test_v4i32_eq422    ; CHECK: liveins: $q0, $q1423    ; CHECK-NEXT: {{  $}}424    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0425    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1426    ; CHECK-NEXT: [[CMEQv4i32_:%[0-9]+]]:fpr128 = CMEQv4i32 [[COPY]], [[COPY1]]427    ; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMEQv4i32_]]428    ; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]]429    ; CHECK-NEXT: RET_ReallyLR implicit $d0430    %0:fpr(<4 x s32>) = COPY $q0431    %1:fpr(<4 x s32>) = COPY $q1432    %4:fpr(<4 x s32>) = G_ICMP intpred(eq), %0(<4 x s32>), %1433    %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)434    $d0 = COPY %3(<4 x s16>)435    RET_ReallyLR implicit $d0436 437...438---439name:            test_v2i32_eq440alignment:       4441legalized:       true442regBankSelected: true443tracksRegLiveness: true444registers:445  - { id: 0, class: fpr }446  - { id: 1, class: fpr }447  - { id: 2, class: _ }448  - { id: 3, class: fpr }449  - { id: 4, class: fpr }450machineFunctionInfo: {}451body:             |452  bb.1 (%ir-block.0):453    liveins: $d0, $d1454 455    ; CHECK-LABEL: name: test_v2i32_eq456    ; CHECK: liveins: $d0, $d1457    ; CHECK-NEXT: {{  $}}458    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0459    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1460    ; CHECK-NEXT: [[CMEQv2i32_:%[0-9]+]]:fpr64 = CMEQv2i32 [[COPY]], [[COPY1]]461    ; CHECK-NEXT: $d0 = COPY [[CMEQv2i32_]]462    ; CHECK-NEXT: RET_ReallyLR implicit $d0463    %0:fpr(<2 x s32>) = COPY $d0464    %1:fpr(<2 x s32>) = COPY $d1465    %4:fpr(<2 x s32>) = G_ICMP intpred(eq), %0(<2 x s32>), %1466    %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)467    $d0 = COPY %3(<2 x s32>)468    RET_ReallyLR implicit $d0469 470...471---472name:            test_v2i16_eq473alignment:       4474legalized:       true475regBankSelected: true476tracksRegLiveness: true477registers:478  - { id: 0, class: _ }479  - { id: 1, class: _ }480  - { id: 2, class: fpr }481  - { id: 3, class: fpr }482  - { id: 4, class: _ }483  - { id: 5, class: fpr }484  - { id: 6, class: _ }485  - { id: 7, class: fpr }486  - { id: 8, class: fpr }487  - { id: 9, class: fpr }488  - { id: 10, class: gpr }489  - { id: 11, class: fpr }490  - { id: 12, class: fpr }491  - { id: 13, class: gpr }492  - { id: 14, class: fpr }493  - { id: 15, class: fpr }494machineFunctionInfo: {}495body:             |496  bb.1 (%ir-block.0):497    liveins: $d0, $d1498 499    ; CHECK-LABEL: name: test_v2i16_eq500    ; CHECK: liveins: $d0, $d1501    ; CHECK-NEXT: {{  $}}502    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0503    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1504    ; CHECK-NEXT: [[MOVID:%[0-9]+]]:fpr64 = MOVID 51505    ; CHECK-NEXT: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY]], [[MOVID]]506    ; CHECK-NEXT: [[MOVID1:%[0-9]+]]:fpr64 = MOVID 51507    ; CHECK-NEXT: [[ANDv8i8_1:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[MOVID1]]508    ; CHECK-NEXT: [[CMEQv2i32_:%[0-9]+]]:fpr64 = CMEQv2i32 [[ANDv8i8_]], [[ANDv8i8_1]]509    ; CHECK-NEXT: $d0 = COPY [[CMEQv2i32_]]510    ; CHECK-NEXT: RET_ReallyLR implicit $d0511    %2:fpr(<2 x s32>) = COPY $d0512    %3:fpr(<2 x s32>) = COPY $d1513    %13:gpr(s32) = G_CONSTANT i32 65535514    %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32)515    %15:fpr(<2 x s32>) = COPY %2(<2 x s32>)516    %7:fpr(<2 x s32>) = G_AND %15, %14517    %10:gpr(s32) = G_CONSTANT i32 65535518    %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)519    %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)520    %8:fpr(<2 x s32>) = G_AND %12, %11521    %9:fpr(<2 x s32>) = G_ICMP intpred(eq), %7(<2 x s32>), %8522    %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)523    $d0 = COPY %5(<2 x s32>)524    RET_ReallyLR implicit $d0525 526...527---528name:            test_v8i16_eq529alignment:       4530legalized:       true531regBankSelected: true532tracksRegLiveness: true533registers:534  - { id: 0, class: fpr }535  - { id: 1, class: fpr }536  - { id: 2, class: _ }537  - { id: 3, class: fpr }538  - { id: 4, class: fpr }539machineFunctionInfo: {}540body:             |541  bb.1 (%ir-block.0):542    liveins: $q0, $q1543 544    ; CHECK-LABEL: name: test_v8i16_eq545    ; CHECK: liveins: $q0, $q1546    ; CHECK-NEXT: {{  $}}547    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0548    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1549    ; CHECK-NEXT: [[CMEQv8i16_:%[0-9]+]]:fpr128 = CMEQv8i16 [[COPY]], [[COPY1]]550    ; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMEQv8i16_]]551    ; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]]552    ; CHECK-NEXT: RET_ReallyLR implicit $d0553    %0:fpr(<8 x s16>) = COPY $q0554    %1:fpr(<8 x s16>) = COPY $q1555    %4:fpr(<8 x s16>) = G_ICMP intpred(eq), %0(<8 x s16>), %1556    %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)557    $d0 = COPY %3(<8 x s8>)558    RET_ReallyLR implicit $d0559 560...561---562name:            test_v4i16_eq563alignment:       4564legalized:       true565regBankSelected: true566tracksRegLiveness: true567registers:568  - { id: 0, class: fpr }569  - { id: 1, class: fpr }570  - { id: 2, class: _ }571  - { id: 3, class: fpr }572  - { id: 4, class: fpr }573machineFunctionInfo: {}574body:             |575  bb.1 (%ir-block.0):576    liveins: $d0, $d1577 578    ; CHECK-LABEL: name: test_v4i16_eq579    ; CHECK: liveins: $d0, $d1580    ; CHECK-NEXT: {{  $}}581    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0582    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1583    ; CHECK-NEXT: [[CMEQv4i16_:%[0-9]+]]:fpr64 = CMEQv4i16 [[COPY]], [[COPY1]]584    ; CHECK-NEXT: $d0 = COPY [[CMEQv4i16_]]585    ; CHECK-NEXT: RET_ReallyLR implicit $d0586    %0:fpr(<4 x s16>) = COPY $d0587    %1:fpr(<4 x s16>) = COPY $d1588    %4:fpr(<4 x s16>) = G_ICMP intpred(eq), %0(<4 x s16>), %1589    %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)590    $d0 = COPY %3(<4 x s16>)591    RET_ReallyLR implicit $d0592 593...594---595name:            test_v16i8_eq596alignment:       4597legalized:       true598regBankSelected: true599tracksRegLiveness: true600registers:601  - { id: 0, class: fpr }602  - { id: 1, class: fpr }603  - { id: 2, class: _ }604  - { id: 3, class: fpr }605  - { id: 4, class: fpr }606machineFunctionInfo: {}607body:             |608  bb.1 (%ir-block.0):609    liveins: $q0, $q1610 611    ; CHECK-LABEL: name: test_v16i8_eq612    ; CHECK: liveins: $q0, $q1613    ; CHECK-NEXT: {{  $}}614    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0615    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1616    ; CHECK-NEXT: [[CMEQv16i8_:%[0-9]+]]:fpr128 = CMEQv16i8 [[COPY]], [[COPY1]]617    ; CHECK-NEXT: $q0 = COPY [[CMEQv16i8_]]618    ; CHECK-NEXT: RET_ReallyLR implicit $q0619    %0:fpr(<16 x s8>) = COPY $q0620    %1:fpr(<16 x s8>) = COPY $q1621    %4:fpr(<16 x s8>) = G_ICMP intpred(eq), %0(<16 x s8>), %1622    %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)623    $q0 = COPY %3(<16 x s8>)624    RET_ReallyLR implicit $q0625 626...627---628name:            test_v8i8_eq629alignment:       4630legalized:       true631regBankSelected: true632tracksRegLiveness: true633registers:634  - { id: 0, class: fpr }635  - { id: 1, class: fpr }636  - { id: 2, class: _ }637  - { id: 3, class: fpr }638  - { id: 4, class: fpr }639machineFunctionInfo: {}640body:             |641  bb.1 (%ir-block.0):642    liveins: $d0, $d1643 644    ; CHECK-LABEL: name: test_v8i8_eq645    ; CHECK: liveins: $d0, $d1646    ; CHECK-NEXT: {{  $}}647    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0648    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1649    ; CHECK-NEXT: [[CMEQv8i8_:%[0-9]+]]:fpr64 = CMEQv8i8 [[COPY]], [[COPY1]]650    ; CHECK-NEXT: $d0 = COPY [[CMEQv8i8_]]651    ; CHECK-NEXT: RET_ReallyLR implicit $d0652    %0:fpr(<8 x s8>) = COPY $d0653    %1:fpr(<8 x s8>) = COPY $d1654    %4:fpr(<8 x s8>) = G_ICMP intpred(eq), %0(<8 x s8>), %1655    %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)656    $d0 = COPY %3(<8 x s8>)657    RET_ReallyLR implicit $d0658 659...660---661name:            test_v2i64_ugt662alignment:       4663legalized:       true664regBankSelected: true665tracksRegLiveness: true666registers:667  - { id: 0, class: fpr }668  - { id: 1, class: fpr }669  - { id: 2, class: _ }670  - { id: 3, class: fpr }671  - { id: 4, class: fpr }672machineFunctionInfo: {}673body:             |674  bb.1 (%ir-block.0):675    liveins: $q0, $q1676 677    ; CHECK-LABEL: name: test_v2i64_ugt678    ; CHECK: liveins: $q0, $q1679    ; CHECK-NEXT: {{  $}}680    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0681    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1682    ; CHECK-NEXT: [[CMHIv2i64_:%[0-9]+]]:fpr128 = CMHIv2i64 [[COPY]], [[COPY1]]683    ; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMHIv2i64_]]684    ; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]]685    ; CHECK-NEXT: RET_ReallyLR implicit $d0686    %0:fpr(<2 x s64>) = COPY $q0687    %1:fpr(<2 x s64>) = COPY $q1688    %4:fpr(<2 x s64>) = G_ICMP intpred(ugt), %0(<2 x s64>), %1689    %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)690    $d0 = COPY %3(<2 x s32>)691    RET_ReallyLR implicit $d0692 693...694---695name:            test_v4i32_ugt696alignment:       4697legalized:       true698regBankSelected: true699tracksRegLiveness: true700registers:701  - { id: 0, class: fpr }702  - { id: 1, class: fpr }703  - { id: 2, class: _ }704  - { id: 3, class: fpr }705  - { id: 4, class: fpr }706machineFunctionInfo: {}707body:             |708  bb.1 (%ir-block.0):709    liveins: $q0, $q1710 711    ; CHECK-LABEL: name: test_v4i32_ugt712    ; CHECK: liveins: $q0, $q1713    ; CHECK-NEXT: {{  $}}714    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0715    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1716    ; CHECK-NEXT: [[CMHIv4i32_:%[0-9]+]]:fpr128 = CMHIv4i32 [[COPY]], [[COPY1]]717    ; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMHIv4i32_]]718    ; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]]719    ; CHECK-NEXT: RET_ReallyLR implicit $d0720    %0:fpr(<4 x s32>) = COPY $q0721    %1:fpr(<4 x s32>) = COPY $q1722    %4:fpr(<4 x s32>) = G_ICMP intpred(ugt), %0(<4 x s32>), %1723    %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)724    $d0 = COPY %3(<4 x s16>)725    RET_ReallyLR implicit $d0726 727...728---729name:            test_v2i32_ugt730alignment:       4731legalized:       true732regBankSelected: true733tracksRegLiveness: true734registers:735  - { id: 0, class: fpr }736  - { id: 1, class: fpr }737  - { id: 2, class: _ }738  - { id: 3, class: fpr }739  - { id: 4, class: fpr }740machineFunctionInfo: {}741body:             |742  bb.1 (%ir-block.0):743    liveins: $d0, $d1744 745    ; CHECK-LABEL: name: test_v2i32_ugt746    ; CHECK: liveins: $d0, $d1747    ; CHECK-NEXT: {{  $}}748    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0749    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1750    ; CHECK-NEXT: [[CMHIv2i32_:%[0-9]+]]:fpr64 = CMHIv2i32 [[COPY]], [[COPY1]]751    ; CHECK-NEXT: $d0 = COPY [[CMHIv2i32_]]752    ; CHECK-NEXT: RET_ReallyLR implicit $d0753    %0:fpr(<2 x s32>) = COPY $d0754    %1:fpr(<2 x s32>) = COPY $d1755    %4:fpr(<2 x s32>) = G_ICMP intpred(ugt), %0(<2 x s32>), %1756    %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)757    $d0 = COPY %3(<2 x s32>)758    RET_ReallyLR implicit $d0759 760...761---762name:            test_v2i16_ugt763alignment:       4764legalized:       true765regBankSelected: true766tracksRegLiveness: true767registers:768  - { id: 0, class: _ }769  - { id: 1, class: _ }770  - { id: 2, class: fpr }771  - { id: 3, class: fpr }772  - { id: 4, class: _ }773  - { id: 5, class: fpr }774  - { id: 6, class: _ }775  - { id: 7, class: fpr }776  - { id: 8, class: fpr }777  - { id: 9, class: fpr }778  - { id: 10, class: gpr }779  - { id: 11, class: fpr }780  - { id: 12, class: fpr }781  - { id: 13, class: gpr }782  - { id: 14, class: fpr }783  - { id: 15, class: fpr }784machineFunctionInfo: {}785body:             |786  bb.1 (%ir-block.0):787    liveins: $d0, $d1788 789    ; CHECK-LABEL: name: test_v2i16_ugt790    ; CHECK: liveins: $d0, $d1791    ; CHECK-NEXT: {{  $}}792    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0793    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1794    ; CHECK-NEXT: [[MOVID:%[0-9]+]]:fpr64 = MOVID 51795    ; CHECK-NEXT: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY]], [[MOVID]]796    ; CHECK-NEXT: [[MOVID1:%[0-9]+]]:fpr64 = MOVID 51797    ; CHECK-NEXT: [[ANDv8i8_1:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[MOVID1]]798    ; CHECK-NEXT: [[CMHIv2i32_:%[0-9]+]]:fpr64 = CMHIv2i32 [[ANDv8i8_]], [[ANDv8i8_1]]799    ; CHECK-NEXT: $d0 = COPY [[CMHIv2i32_]]800    ; CHECK-NEXT: RET_ReallyLR implicit $d0801    %2:fpr(<2 x s32>) = COPY $d0802    %3:fpr(<2 x s32>) = COPY $d1803    %13:gpr(s32) = G_CONSTANT i32 65535804    %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32)805    %15:fpr(<2 x s32>) = COPY %2(<2 x s32>)806    %7:fpr(<2 x s32>) = G_AND %15, %14807    %10:gpr(s32) = G_CONSTANT i32 65535808    %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)809    %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)810    %8:fpr(<2 x s32>) = G_AND %12, %11811    %9:fpr(<2 x s32>) = G_ICMP intpred(ugt), %7(<2 x s32>), %8812    %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)813    $d0 = COPY %5(<2 x s32>)814    RET_ReallyLR implicit $d0815 816...817---818name:            test_v8i16_ugt819alignment:       4820legalized:       true821regBankSelected: true822tracksRegLiveness: true823registers:824  - { id: 0, class: fpr }825  - { id: 1, class: fpr }826  - { id: 2, class: _ }827  - { id: 3, class: fpr }828  - { id: 4, class: fpr }829machineFunctionInfo: {}830body:             |831  bb.1 (%ir-block.0):832    liveins: $q0, $q1833 834    ; CHECK-LABEL: name: test_v8i16_ugt835    ; CHECK: liveins: $q0, $q1836    ; CHECK-NEXT: {{  $}}837    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0838    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1839    ; CHECK-NEXT: [[CMHIv8i16_:%[0-9]+]]:fpr128 = CMHIv8i16 [[COPY]], [[COPY1]]840    ; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMHIv8i16_]]841    ; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]]842    ; CHECK-NEXT: RET_ReallyLR implicit $d0843    %0:fpr(<8 x s16>) = COPY $q0844    %1:fpr(<8 x s16>) = COPY $q1845    %4:fpr(<8 x s16>) = G_ICMP intpred(ugt), %0(<8 x s16>), %1846    %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)847    $d0 = COPY %3(<8 x s8>)848    RET_ReallyLR implicit $d0849 850...851---852name:            test_v4i16_ugt853alignment:       4854legalized:       true855regBankSelected: true856tracksRegLiveness: true857registers:858  - { id: 0, class: fpr }859  - { id: 1, class: fpr }860  - { id: 2, class: _ }861  - { id: 3, class: fpr }862  - { id: 4, class: fpr }863machineFunctionInfo: {}864body:             |865  bb.1 (%ir-block.0):866    liveins: $d0, $d1867 868    ; CHECK-LABEL: name: test_v4i16_ugt869    ; CHECK: liveins: $d0, $d1870    ; CHECK-NEXT: {{  $}}871    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0872    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1873    ; CHECK-NEXT: [[CMHIv4i16_:%[0-9]+]]:fpr64 = CMHIv4i16 [[COPY]], [[COPY1]]874    ; CHECK-NEXT: $d0 = COPY [[CMHIv4i16_]]875    ; CHECK-NEXT: RET_ReallyLR implicit $d0876    %0:fpr(<4 x s16>) = COPY $d0877    %1:fpr(<4 x s16>) = COPY $d1878    %4:fpr(<4 x s16>) = G_ICMP intpred(ugt), %0(<4 x s16>), %1879    %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)880    $d0 = COPY %3(<4 x s16>)881    RET_ReallyLR implicit $d0882 883...884---885name:            test_v16i8_ugt886alignment:       4887legalized:       true888regBankSelected: true889tracksRegLiveness: true890registers:891  - { id: 0, class: fpr }892  - { id: 1, class: fpr }893  - { id: 2, class: _ }894  - { id: 3, class: fpr }895  - { id: 4, class: fpr }896machineFunctionInfo: {}897body:             |898  bb.1 (%ir-block.0):899    liveins: $q0, $q1900 901    ; CHECK-LABEL: name: test_v16i8_ugt902    ; CHECK: liveins: $q0, $q1903    ; CHECK-NEXT: {{  $}}904    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0905    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1906    ; CHECK-NEXT: [[CMHIv16i8_:%[0-9]+]]:fpr128 = CMHIv16i8 [[COPY]], [[COPY1]]907    ; CHECK-NEXT: $q0 = COPY [[CMHIv16i8_]]908    ; CHECK-NEXT: RET_ReallyLR implicit $q0909    %0:fpr(<16 x s8>) = COPY $q0910    %1:fpr(<16 x s8>) = COPY $q1911    %4:fpr(<16 x s8>) = G_ICMP intpred(ugt), %0(<16 x s8>), %1912    %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)913    $q0 = COPY %3(<16 x s8>)914    RET_ReallyLR implicit $q0915 916...917---918name:            test_v8i8_ugt919alignment:       4920legalized:       true921regBankSelected: true922tracksRegLiveness: true923registers:924  - { id: 0, class: fpr }925  - { id: 1, class: fpr }926  - { id: 2, class: _ }927  - { id: 3, class: fpr }928  - { id: 4, class: fpr }929machineFunctionInfo: {}930body:             |931  bb.1 (%ir-block.0):932    liveins: $d0, $d1933 934    ; CHECK-LABEL: name: test_v8i8_ugt935    ; CHECK: liveins: $d0, $d1936    ; CHECK-NEXT: {{  $}}937    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0938    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1939    ; CHECK-NEXT: [[CMHIv8i8_:%[0-9]+]]:fpr64 = CMHIv8i8 [[COPY]], [[COPY1]]940    ; CHECK-NEXT: $d0 = COPY [[CMHIv8i8_]]941    ; CHECK-NEXT: RET_ReallyLR implicit $d0942    %0:fpr(<8 x s8>) = COPY $d0943    %1:fpr(<8 x s8>) = COPY $d1944    %4:fpr(<8 x s8>) = G_ICMP intpred(ugt), %0(<8 x s8>), %1945    %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)946    $d0 = COPY %3(<8 x s8>)947    RET_ReallyLR implicit $d0948 949...950---951name:            test_v2i64_uge952alignment:       4953legalized:       true954regBankSelected: true955tracksRegLiveness: true956registers:957  - { id: 0, class: fpr }958  - { id: 1, class: fpr }959  - { id: 2, class: _ }960  - { id: 3, class: fpr }961  - { id: 4, class: fpr }962machineFunctionInfo: {}963body:             |964  bb.1 (%ir-block.0):965    liveins: $q0, $q1966 967    ; CHECK-LABEL: name: test_v2i64_uge968    ; CHECK: liveins: $q0, $q1969    ; CHECK-NEXT: {{  $}}970    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0971    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1972    ; CHECK-NEXT: [[CMHSv2i64_:%[0-9]+]]:fpr128 = CMHSv2i64 [[COPY]], [[COPY1]]973    ; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMHSv2i64_]]974    ; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]]975    ; CHECK-NEXT: RET_ReallyLR implicit $d0976    %0:fpr(<2 x s64>) = COPY $q0977    %1:fpr(<2 x s64>) = COPY $q1978    %4:fpr(<2 x s64>) = G_ICMP intpred(uge), %0(<2 x s64>), %1979    %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)980    $d0 = COPY %3(<2 x s32>)981    RET_ReallyLR implicit $d0982 983...984---985name:            test_v4i32_uge986alignment:       4987legalized:       true988regBankSelected: true989tracksRegLiveness: true990registers:991  - { id: 0, class: fpr }992  - { id: 1, class: fpr }993  - { id: 2, class: _ }994  - { id: 3, class: fpr }995  - { id: 4, class: fpr }996machineFunctionInfo: {}997body:             |998  bb.1 (%ir-block.0):999    liveins: $q0, $q11000 1001    ; CHECK-LABEL: name: test_v4i32_uge1002    ; CHECK: liveins: $q0, $q11003    ; CHECK-NEXT: {{  $}}1004    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q01005    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q11006    ; CHECK-NEXT: [[CMHSv4i32_:%[0-9]+]]:fpr128 = CMHSv4i32 [[COPY]], [[COPY1]]1007    ; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMHSv4i32_]]1008    ; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]]1009    ; CHECK-NEXT: RET_ReallyLR implicit $d01010    %0:fpr(<4 x s32>) = COPY $q01011    %1:fpr(<4 x s32>) = COPY $q11012    %4:fpr(<4 x s32>) = G_ICMP intpred(uge), %0(<4 x s32>), %11013    %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)1014    $d0 = COPY %3(<4 x s16>)1015    RET_ReallyLR implicit $d01016 1017...1018---1019name:            test_v2i32_uge1020alignment:       41021legalized:       true1022regBankSelected: true1023tracksRegLiveness: true1024registers:1025  - { id: 0, class: fpr }1026  - { id: 1, class: fpr }1027  - { id: 2, class: _ }1028  - { id: 3, class: fpr }1029  - { id: 4, class: fpr }1030machineFunctionInfo: {}1031body:             |1032  bb.1 (%ir-block.0):1033    liveins: $d0, $d11034 1035    ; CHECK-LABEL: name: test_v2i32_uge1036    ; CHECK: liveins: $d0, $d11037    ; CHECK-NEXT: {{  $}}1038    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01039    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11040    ; CHECK-NEXT: [[CMHSv2i32_:%[0-9]+]]:fpr64 = CMHSv2i32 [[COPY]], [[COPY1]]1041    ; CHECK-NEXT: $d0 = COPY [[CMHSv2i32_]]1042    ; CHECK-NEXT: RET_ReallyLR implicit $d01043    %0:fpr(<2 x s32>) = COPY $d01044    %1:fpr(<2 x s32>) = COPY $d11045    %4:fpr(<2 x s32>) = G_ICMP intpred(uge), %0(<2 x s32>), %11046    %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)1047    $d0 = COPY %3(<2 x s32>)1048    RET_ReallyLR implicit $d01049 1050...1051---1052name:            test_v2i16_uge1053alignment:       41054legalized:       true1055regBankSelected: true1056tracksRegLiveness: true1057registers:1058  - { id: 0, class: _ }1059  - { id: 1, class: _ }1060  - { id: 2, class: fpr }1061  - { id: 3, class: fpr }1062  - { id: 4, class: _ }1063  - { id: 5, class: fpr }1064  - { id: 6, class: _ }1065  - { id: 7, class: fpr }1066  - { id: 8, class: fpr }1067  - { id: 9, class: fpr }1068  - { id: 10, class: gpr }1069  - { id: 11, class: fpr }1070  - { id: 12, class: fpr }1071  - { id: 13, class: gpr }1072  - { id: 14, class: fpr }1073  - { id: 15, class: fpr }1074machineFunctionInfo: {}1075body:             |1076  bb.1 (%ir-block.0):1077    liveins: $d0, $d11078 1079    ; CHECK-LABEL: name: test_v2i16_uge1080    ; CHECK: liveins: $d0, $d11081    ; CHECK-NEXT: {{  $}}1082    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01083    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11084    ; CHECK-NEXT: [[MOVID:%[0-9]+]]:fpr64 = MOVID 511085    ; CHECK-NEXT: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY]], [[MOVID]]1086    ; CHECK-NEXT: [[MOVID1:%[0-9]+]]:fpr64 = MOVID 511087    ; CHECK-NEXT: [[ANDv8i8_1:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[MOVID1]]1088    ; CHECK-NEXT: [[CMHSv2i32_:%[0-9]+]]:fpr64 = CMHSv2i32 [[ANDv8i8_]], [[ANDv8i8_1]]1089    ; CHECK-NEXT: $d0 = COPY [[CMHSv2i32_]]1090    ; CHECK-NEXT: RET_ReallyLR implicit $d01091    %2:fpr(<2 x s32>) = COPY $d01092    %3:fpr(<2 x s32>) = COPY $d11093    %13:gpr(s32) = G_CONSTANT i32 655351094    %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32)1095    %15:fpr(<2 x s32>) = COPY %2(<2 x s32>)1096    %7:fpr(<2 x s32>) = G_AND %15, %141097    %10:gpr(s32) = G_CONSTANT i32 655351098    %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)1099    %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)1100    %8:fpr(<2 x s32>) = G_AND %12, %111101    %9:fpr(<2 x s32>) = G_ICMP intpred(uge), %7(<2 x s32>), %81102    %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)1103    $d0 = COPY %5(<2 x s32>)1104    RET_ReallyLR implicit $d01105 1106...1107---1108name:            test_v8i16_uge1109alignment:       41110legalized:       true1111regBankSelected: true1112tracksRegLiveness: true1113registers:1114  - { id: 0, class: fpr }1115  - { id: 1, class: fpr }1116  - { id: 2, class: _ }1117  - { id: 3, class: fpr }1118  - { id: 4, class: fpr }1119machineFunctionInfo: {}1120body:             |1121  bb.1 (%ir-block.0):1122    liveins: $q0, $q11123 1124    ; CHECK-LABEL: name: test_v8i16_uge1125    ; CHECK: liveins: $q0, $q11126    ; CHECK-NEXT: {{  $}}1127    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q01128    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q11129    ; CHECK-NEXT: [[CMHSv8i16_:%[0-9]+]]:fpr128 = CMHSv8i16 [[COPY]], [[COPY1]]1130    ; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMHSv8i16_]]1131    ; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]]1132    ; CHECK-NEXT: RET_ReallyLR implicit $d01133    %0:fpr(<8 x s16>) = COPY $q01134    %1:fpr(<8 x s16>) = COPY $q11135    %4:fpr(<8 x s16>) = G_ICMP intpred(uge), %0(<8 x s16>), %11136    %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)1137    $d0 = COPY %3(<8 x s8>)1138    RET_ReallyLR implicit $d01139 1140...1141---1142name:            test_v4i16_uge1143alignment:       41144legalized:       true1145regBankSelected: true1146tracksRegLiveness: true1147registers:1148  - { id: 0, class: fpr }1149  - { id: 1, class: fpr }1150  - { id: 2, class: _ }1151  - { id: 3, class: fpr }1152  - { id: 4, class: fpr }1153machineFunctionInfo: {}1154body:             |1155  bb.1 (%ir-block.0):1156    liveins: $d0, $d11157 1158    ; CHECK-LABEL: name: test_v4i16_uge1159    ; CHECK: liveins: $d0, $d11160    ; CHECK-NEXT: {{  $}}1161    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01162    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11163    ; CHECK-NEXT: [[CMHSv4i16_:%[0-9]+]]:fpr64 = CMHSv4i16 [[COPY]], [[COPY1]]1164    ; CHECK-NEXT: $d0 = COPY [[CMHSv4i16_]]1165    ; CHECK-NEXT: RET_ReallyLR implicit $d01166    %0:fpr(<4 x s16>) = COPY $d01167    %1:fpr(<4 x s16>) = COPY $d11168    %4:fpr(<4 x s16>) = G_ICMP intpred(uge), %0(<4 x s16>), %11169    %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)1170    $d0 = COPY %3(<4 x s16>)1171    RET_ReallyLR implicit $d01172 1173...1174---1175name:            test_v16i8_uge1176alignment:       41177legalized:       true1178regBankSelected: true1179tracksRegLiveness: true1180registers:1181  - { id: 0, class: fpr }1182  - { id: 1, class: fpr }1183  - { id: 2, class: _ }1184  - { id: 3, class: fpr }1185  - { id: 4, class: fpr }1186machineFunctionInfo: {}1187body:             |1188  bb.1 (%ir-block.0):1189    liveins: $q0, $q11190 1191    ; CHECK-LABEL: name: test_v16i8_uge1192    ; CHECK: liveins: $q0, $q11193    ; CHECK-NEXT: {{  $}}1194    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q01195    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q11196    ; CHECK-NEXT: [[CMHSv16i8_:%[0-9]+]]:fpr128 = CMHSv16i8 [[COPY]], [[COPY1]]1197    ; CHECK-NEXT: $q0 = COPY [[CMHSv16i8_]]1198    ; CHECK-NEXT: RET_ReallyLR implicit $q01199    %0:fpr(<16 x s8>) = COPY $q01200    %1:fpr(<16 x s8>) = COPY $q11201    %4:fpr(<16 x s8>) = G_ICMP intpred(uge), %0(<16 x s8>), %11202    %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)1203    $q0 = COPY %3(<16 x s8>)1204    RET_ReallyLR implicit $q01205 1206...1207---1208name:            test_v8i8_uge1209alignment:       41210legalized:       true1211regBankSelected: true1212tracksRegLiveness: true1213registers:1214  - { id: 0, class: fpr }1215  - { id: 1, class: fpr }1216  - { id: 2, class: _ }1217  - { id: 3, class: fpr }1218  - { id: 4, class: fpr }1219machineFunctionInfo: {}1220body:             |1221  bb.1 (%ir-block.0):1222    liveins: $d0, $d11223 1224    ; CHECK-LABEL: name: test_v8i8_uge1225    ; CHECK: liveins: $d0, $d11226    ; CHECK-NEXT: {{  $}}1227    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01228    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11229    ; CHECK-NEXT: [[CMHSv8i8_:%[0-9]+]]:fpr64 = CMHSv8i8 [[COPY]], [[COPY1]]1230    ; CHECK-NEXT: $d0 = COPY [[CMHSv8i8_]]1231    ; CHECK-NEXT: RET_ReallyLR implicit $d01232    %0:fpr(<8 x s8>) = COPY $d01233    %1:fpr(<8 x s8>) = COPY $d11234    %4:fpr(<8 x s8>) = G_ICMP intpred(uge), %0(<8 x s8>), %11235    %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)1236    $d0 = COPY %3(<8 x s8>)1237    RET_ReallyLR implicit $d01238 1239...1240---1241name:            test_v2i64_ult1242alignment:       41243legalized:       true1244regBankSelected: true1245tracksRegLiveness: true1246registers:1247  - { id: 0, class: fpr }1248  - { id: 1, class: fpr }1249  - { id: 2, class: _ }1250  - { id: 3, class: fpr }1251  - { id: 4, class: fpr }1252machineFunctionInfo: {}1253body:             |1254  bb.1 (%ir-block.0):1255    liveins: $q0, $q11256 1257    ; CHECK-LABEL: name: test_v2i64_ult1258    ; CHECK: liveins: $q0, $q11259    ; CHECK-NEXT: {{  $}}1260    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q01261    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q11262    ; CHECK-NEXT: [[CMHIv2i64_:%[0-9]+]]:fpr128 = CMHIv2i64 [[COPY1]], [[COPY]]1263    ; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMHIv2i64_]]1264    ; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]]1265    ; CHECK-NEXT: RET_ReallyLR implicit $d01266    %0:fpr(<2 x s64>) = COPY $q01267    %1:fpr(<2 x s64>) = COPY $q11268    %4:fpr(<2 x s64>) = G_ICMP intpred(ult), %0(<2 x s64>), %11269    %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)1270    $d0 = COPY %3(<2 x s32>)1271    RET_ReallyLR implicit $d01272 1273...1274---1275name:            test_v4i32_ult1276alignment:       41277legalized:       true1278regBankSelected: true1279tracksRegLiveness: true1280registers:1281  - { id: 0, class: fpr }1282  - { id: 1, class: fpr }1283  - { id: 2, class: _ }1284  - { id: 3, class: fpr }1285  - { id: 4, class: fpr }1286machineFunctionInfo: {}1287body:             |1288  bb.1 (%ir-block.0):1289    liveins: $q0, $q11290 1291    ; CHECK-LABEL: name: test_v4i32_ult1292    ; CHECK: liveins: $q0, $q11293    ; CHECK-NEXT: {{  $}}1294    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q01295    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q11296    ; CHECK-NEXT: [[CMHIv4i32_:%[0-9]+]]:fpr128 = CMHIv4i32 [[COPY1]], [[COPY]]1297    ; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMHIv4i32_]]1298    ; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]]1299    ; CHECK-NEXT: RET_ReallyLR implicit $d01300    %0:fpr(<4 x s32>) = COPY $q01301    %1:fpr(<4 x s32>) = COPY $q11302    %4:fpr(<4 x s32>) = G_ICMP intpred(ult), %0(<4 x s32>), %11303    %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)1304    $d0 = COPY %3(<4 x s16>)1305    RET_ReallyLR implicit $d01306 1307...1308---1309name:            test_v2i32_ult1310alignment:       41311legalized:       true1312regBankSelected: true1313tracksRegLiveness: true1314registers:1315  - { id: 0, class: fpr }1316  - { id: 1, class: fpr }1317  - { id: 2, class: _ }1318  - { id: 3, class: fpr }1319  - { id: 4, class: fpr }1320machineFunctionInfo: {}1321body:             |1322  bb.1 (%ir-block.0):1323    liveins: $d0, $d11324 1325    ; CHECK-LABEL: name: test_v2i32_ult1326    ; CHECK: liveins: $d0, $d11327    ; CHECK-NEXT: {{  $}}1328    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01329    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11330    ; CHECK-NEXT: [[CMHIv2i32_:%[0-9]+]]:fpr64 = CMHIv2i32 [[COPY1]], [[COPY]]1331    ; CHECK-NEXT: $d0 = COPY [[CMHIv2i32_]]1332    ; CHECK-NEXT: RET_ReallyLR implicit $d01333    %0:fpr(<2 x s32>) = COPY $d01334    %1:fpr(<2 x s32>) = COPY $d11335    %4:fpr(<2 x s32>) = G_ICMP intpred(ult), %0(<2 x s32>), %11336    %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)1337    $d0 = COPY %3(<2 x s32>)1338    RET_ReallyLR implicit $d01339 1340...1341---1342name:            test_v2i16_ult1343alignment:       41344legalized:       true1345regBankSelected: true1346tracksRegLiveness: true1347registers:1348  - { id: 0, class: _ }1349  - { id: 1, class: _ }1350  - { id: 2, class: fpr }1351  - { id: 3, class: fpr }1352  - { id: 4, class: _ }1353  - { id: 5, class: fpr }1354  - { id: 6, class: _ }1355  - { id: 7, class: fpr }1356  - { id: 8, class: fpr }1357  - { id: 9, class: fpr }1358  - { id: 10, class: gpr }1359  - { id: 11, class: fpr }1360  - { id: 12, class: fpr }1361  - { id: 13, class: gpr }1362  - { id: 14, class: fpr }1363  - { id: 15, class: fpr }1364machineFunctionInfo: {}1365body:             |1366  bb.1 (%ir-block.0):1367    liveins: $d0, $d11368 1369    ; CHECK-LABEL: name: test_v2i16_ult1370    ; CHECK: liveins: $d0, $d11371    ; CHECK-NEXT: {{  $}}1372    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01373    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11374    ; CHECK-NEXT: [[MOVID:%[0-9]+]]:fpr64 = MOVID 511375    ; CHECK-NEXT: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY]], [[MOVID]]1376    ; CHECK-NEXT: [[MOVID1:%[0-9]+]]:fpr64 = MOVID 511377    ; CHECK-NEXT: [[ANDv8i8_1:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[MOVID1]]1378    ; CHECK-NEXT: [[CMHIv2i32_:%[0-9]+]]:fpr64 = CMHIv2i32 [[ANDv8i8_1]], [[ANDv8i8_]]1379    ; CHECK-NEXT: $d0 = COPY [[CMHIv2i32_]]1380    ; CHECK-NEXT: RET_ReallyLR implicit $d01381    %2:fpr(<2 x s32>) = COPY $d01382    %3:fpr(<2 x s32>) = COPY $d11383    %13:gpr(s32) = G_CONSTANT i32 655351384    %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32)1385    %15:fpr(<2 x s32>) = COPY %2(<2 x s32>)1386    %7:fpr(<2 x s32>) = G_AND %15, %141387    %10:gpr(s32) = G_CONSTANT i32 655351388    %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)1389    %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)1390    %8:fpr(<2 x s32>) = G_AND %12, %111391    %9:fpr(<2 x s32>) = G_ICMP intpred(ult), %7(<2 x s32>), %81392    %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)1393    $d0 = COPY %5(<2 x s32>)1394    RET_ReallyLR implicit $d01395 1396...1397---1398name:            test_v8i16_ult1399alignment:       41400legalized:       true1401regBankSelected: true1402tracksRegLiveness: true1403registers:1404  - { id: 0, class: fpr }1405  - { id: 1, class: fpr }1406  - { id: 2, class: _ }1407  - { id: 3, class: fpr }1408  - { id: 4, class: fpr }1409machineFunctionInfo: {}1410body:             |1411  bb.1 (%ir-block.0):1412    liveins: $q0, $q11413 1414    ; CHECK-LABEL: name: test_v8i16_ult1415    ; CHECK: liveins: $q0, $q11416    ; CHECK-NEXT: {{  $}}1417    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q01418    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q11419    ; CHECK-NEXT: [[CMHIv8i16_:%[0-9]+]]:fpr128 = CMHIv8i16 [[COPY1]], [[COPY]]1420    ; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMHIv8i16_]]1421    ; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]]1422    ; CHECK-NEXT: RET_ReallyLR implicit $d01423    %0:fpr(<8 x s16>) = COPY $q01424    %1:fpr(<8 x s16>) = COPY $q11425    %4:fpr(<8 x s16>) = G_ICMP intpred(ult), %0(<8 x s16>), %11426    %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)1427    $d0 = COPY %3(<8 x s8>)1428    RET_ReallyLR implicit $d01429 1430...1431---1432name:            test_v4i16_ult1433alignment:       41434legalized:       true1435regBankSelected: true1436tracksRegLiveness: true1437registers:1438  - { id: 0, class: fpr }1439  - { id: 1, class: fpr }1440  - { id: 2, class: _ }1441  - { id: 3, class: fpr }1442  - { id: 4, class: fpr }1443machineFunctionInfo: {}1444body:             |1445  bb.1 (%ir-block.0):1446    liveins: $d0, $d11447 1448    ; CHECK-LABEL: name: test_v4i16_ult1449    ; CHECK: liveins: $d0, $d11450    ; CHECK-NEXT: {{  $}}1451    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01452    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11453    ; CHECK-NEXT: [[CMHIv4i16_:%[0-9]+]]:fpr64 = CMHIv4i16 [[COPY1]], [[COPY]]1454    ; CHECK-NEXT: $d0 = COPY [[CMHIv4i16_]]1455    ; CHECK-NEXT: RET_ReallyLR implicit $d01456    %0:fpr(<4 x s16>) = COPY $d01457    %1:fpr(<4 x s16>) = COPY $d11458    %4:fpr(<4 x s16>) = G_ICMP intpred(ult), %0(<4 x s16>), %11459    %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)1460    $d0 = COPY %3(<4 x s16>)1461    RET_ReallyLR implicit $d01462 1463...1464---1465name:            test_v16i8_ult1466alignment:       41467legalized:       true1468regBankSelected: true1469tracksRegLiveness: true1470registers:1471  - { id: 0, class: fpr }1472  - { id: 1, class: fpr }1473  - { id: 2, class: _ }1474  - { id: 3, class: fpr }1475  - { id: 4, class: fpr }1476machineFunctionInfo: {}1477body:             |1478  bb.1 (%ir-block.0):1479    liveins: $q0, $q11480 1481    ; CHECK-LABEL: name: test_v16i8_ult1482    ; CHECK: liveins: $q0, $q11483    ; CHECK-NEXT: {{  $}}1484    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q01485    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q11486    ; CHECK-NEXT: [[CMHIv16i8_:%[0-9]+]]:fpr128 = CMHIv16i8 [[COPY1]], [[COPY]]1487    ; CHECK-NEXT: $q0 = COPY [[CMHIv16i8_]]1488    ; CHECK-NEXT: RET_ReallyLR implicit $q01489    %0:fpr(<16 x s8>) = COPY $q01490    %1:fpr(<16 x s8>) = COPY $q11491    %4:fpr(<16 x s8>) = G_ICMP intpred(ult), %0(<16 x s8>), %11492    %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)1493    $q0 = COPY %3(<16 x s8>)1494    RET_ReallyLR implicit $q01495 1496...1497---1498name:            test_v8i8_ult1499alignment:       41500legalized:       true1501regBankSelected: true1502tracksRegLiveness: true1503registers:1504  - { id: 0, class: fpr }1505  - { id: 1, class: fpr }1506  - { id: 2, class: _ }1507  - { id: 3, class: fpr }1508  - { id: 4, class: fpr }1509machineFunctionInfo: {}1510body:             |1511  bb.1 (%ir-block.0):1512    liveins: $d0, $d11513 1514    ; CHECK-LABEL: name: test_v8i8_ult1515    ; CHECK: liveins: $d0, $d11516    ; CHECK-NEXT: {{  $}}1517    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01518    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11519    ; CHECK-NEXT: [[CMHIv8i8_:%[0-9]+]]:fpr64 = CMHIv8i8 [[COPY1]], [[COPY]]1520    ; CHECK-NEXT: $d0 = COPY [[CMHIv8i8_]]1521    ; CHECK-NEXT: RET_ReallyLR implicit $d01522    %0:fpr(<8 x s8>) = COPY $d01523    %1:fpr(<8 x s8>) = COPY $d11524    %4:fpr(<8 x s8>) = G_ICMP intpred(ult), %0(<8 x s8>), %11525    %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)1526    $d0 = COPY %3(<8 x s8>)1527    RET_ReallyLR implicit $d01528 1529...1530---1531name:            test_v2i64_ule1532alignment:       41533legalized:       true1534regBankSelected: true1535tracksRegLiveness: true1536registers:1537  - { id: 0, class: fpr }1538  - { id: 1, class: fpr }1539  - { id: 2, class: _ }1540  - { id: 3, class: fpr }1541  - { id: 4, class: fpr }1542machineFunctionInfo: {}1543body:             |1544  bb.1 (%ir-block.0):1545    liveins: $q0, $q11546 1547    ; CHECK-LABEL: name: test_v2i64_ule1548    ; CHECK: liveins: $q0, $q11549    ; CHECK-NEXT: {{  $}}1550    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q01551    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q11552    ; CHECK-NEXT: [[CMHSv2i64_:%[0-9]+]]:fpr128 = CMHSv2i64 [[COPY1]], [[COPY]]1553    ; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMHSv2i64_]]1554    ; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]]1555    ; CHECK-NEXT: RET_ReallyLR implicit $d01556    %0:fpr(<2 x s64>) = COPY $q01557    %1:fpr(<2 x s64>) = COPY $q11558    %4:fpr(<2 x s64>) = G_ICMP intpred(ule), %0(<2 x s64>), %11559    %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)1560    $d0 = COPY %3(<2 x s32>)1561    RET_ReallyLR implicit $d01562 1563...1564---1565name:            test_v4i32_ule1566alignment:       41567legalized:       true1568regBankSelected: true1569tracksRegLiveness: true1570registers:1571  - { id: 0, class: fpr }1572  - { id: 1, class: fpr }1573  - { id: 2, class: _ }1574  - { id: 3, class: fpr }1575  - { id: 4, class: fpr }1576machineFunctionInfo: {}1577body:             |1578  bb.1 (%ir-block.0):1579    liveins: $q0, $q11580 1581    ; CHECK-LABEL: name: test_v4i32_ule1582    ; CHECK: liveins: $q0, $q11583    ; CHECK-NEXT: {{  $}}1584    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q01585    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q11586    ; CHECK-NEXT: [[CMHSv4i32_:%[0-9]+]]:fpr128 = CMHSv4i32 [[COPY1]], [[COPY]]1587    ; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMHSv4i32_]]1588    ; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]]1589    ; CHECK-NEXT: RET_ReallyLR implicit $d01590    %0:fpr(<4 x s32>) = COPY $q01591    %1:fpr(<4 x s32>) = COPY $q11592    %4:fpr(<4 x s32>) = G_ICMP intpred(ule), %0(<4 x s32>), %11593    %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)1594    $d0 = COPY %3(<4 x s16>)1595    RET_ReallyLR implicit $d01596 1597...1598---1599name:            test_v2i32_ule1600alignment:       41601legalized:       true1602regBankSelected: true1603tracksRegLiveness: true1604registers:1605  - { id: 0, class: fpr }1606  - { id: 1, class: fpr }1607  - { id: 2, class: _ }1608  - { id: 3, class: fpr }1609  - { id: 4, class: fpr }1610machineFunctionInfo: {}1611body:             |1612  bb.1 (%ir-block.0):1613    liveins: $d0, $d11614 1615    ; CHECK-LABEL: name: test_v2i32_ule1616    ; CHECK: liveins: $d0, $d11617    ; CHECK-NEXT: {{  $}}1618    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01619    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11620    ; CHECK-NEXT: [[CMHSv2i32_:%[0-9]+]]:fpr64 = CMHSv2i32 [[COPY1]], [[COPY]]1621    ; CHECK-NEXT: $d0 = COPY [[CMHSv2i32_]]1622    ; CHECK-NEXT: RET_ReallyLR implicit $d01623    %0:fpr(<2 x s32>) = COPY $d01624    %1:fpr(<2 x s32>) = COPY $d11625    %4:fpr(<2 x s32>) = G_ICMP intpred(ule), %0(<2 x s32>), %11626    %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)1627    $d0 = COPY %3(<2 x s32>)1628    RET_ReallyLR implicit $d01629 1630...1631---1632name:            test_v2i16_ule1633alignment:       41634legalized:       true1635regBankSelected: true1636tracksRegLiveness: true1637registers:1638  - { id: 0, class: _ }1639  - { id: 1, class: _ }1640  - { id: 2, class: fpr }1641  - { id: 3, class: fpr }1642  - { id: 4, class: _ }1643  - { id: 5, class: fpr }1644  - { id: 6, class: _ }1645  - { id: 7, class: fpr }1646  - { id: 8, class: fpr }1647  - { id: 9, class: fpr }1648  - { id: 10, class: gpr }1649  - { id: 11, class: fpr }1650  - { id: 12, class: fpr }1651  - { id: 13, class: gpr }1652  - { id: 14, class: fpr }1653  - { id: 15, class: fpr }1654machineFunctionInfo: {}1655body:             |1656  bb.1 (%ir-block.0):1657    liveins: $d0, $d11658 1659    ; CHECK-LABEL: name: test_v2i16_ule1660    ; CHECK: liveins: $d0, $d11661    ; CHECK-NEXT: {{  $}}1662    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01663    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11664    ; CHECK-NEXT: [[MOVID:%[0-9]+]]:fpr64 = MOVID 511665    ; CHECK-NEXT: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY]], [[MOVID]]1666    ; CHECK-NEXT: [[MOVID1:%[0-9]+]]:fpr64 = MOVID 511667    ; CHECK-NEXT: [[ANDv8i8_1:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[MOVID1]]1668    ; CHECK-NEXT: [[CMHSv2i32_:%[0-9]+]]:fpr64 = CMHSv2i32 [[ANDv8i8_1]], [[ANDv8i8_]]1669    ; CHECK-NEXT: $d0 = COPY [[CMHSv2i32_]]1670    ; CHECK-NEXT: RET_ReallyLR implicit $d01671    %2:fpr(<2 x s32>) = COPY $d01672    %3:fpr(<2 x s32>) = COPY $d11673    %13:gpr(s32) = G_CONSTANT i32 655351674    %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32)1675    %15:fpr(<2 x s32>) = COPY %2(<2 x s32>)1676    %7:fpr(<2 x s32>) = G_AND %15, %141677    %10:gpr(s32) = G_CONSTANT i32 655351678    %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)1679    %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)1680    %8:fpr(<2 x s32>) = G_AND %12, %111681    %9:fpr(<2 x s32>) = G_ICMP intpred(ule), %7(<2 x s32>), %81682    %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)1683    $d0 = COPY %5(<2 x s32>)1684    RET_ReallyLR implicit $d01685 1686...1687---1688name:            test_v8i16_ule1689alignment:       41690legalized:       true1691regBankSelected: true1692tracksRegLiveness: true1693registers:1694  - { id: 0, class: fpr }1695  - { id: 1, class: fpr }1696  - { id: 2, class: _ }1697  - { id: 3, class: fpr }1698  - { id: 4, class: fpr }1699machineFunctionInfo: {}1700body:             |1701  bb.1 (%ir-block.0):1702    liveins: $q0, $q11703 1704    ; CHECK-LABEL: name: test_v8i16_ule1705    ; CHECK: liveins: $q0, $q11706    ; CHECK-NEXT: {{  $}}1707    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q01708    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q11709    ; CHECK-NEXT: [[CMHSv8i16_:%[0-9]+]]:fpr128 = CMHSv8i16 [[COPY1]], [[COPY]]1710    ; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMHSv8i16_]]1711    ; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]]1712    ; CHECK-NEXT: RET_ReallyLR implicit $d01713    %0:fpr(<8 x s16>) = COPY $q01714    %1:fpr(<8 x s16>) = COPY $q11715    %4:fpr(<8 x s16>) = G_ICMP intpred(ule), %0(<8 x s16>), %11716    %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)1717    $d0 = COPY %3(<8 x s8>)1718    RET_ReallyLR implicit $d01719 1720...1721---1722name:            test_v4i16_ule1723alignment:       41724legalized:       true1725regBankSelected: true1726tracksRegLiveness: true1727registers:1728  - { id: 0, class: fpr }1729  - { id: 1, class: fpr }1730  - { id: 2, class: _ }1731  - { id: 3, class: fpr }1732  - { id: 4, class: fpr }1733machineFunctionInfo: {}1734body:             |1735  bb.1 (%ir-block.0):1736    liveins: $d0, $d11737 1738    ; CHECK-LABEL: name: test_v4i16_ule1739    ; CHECK: liveins: $d0, $d11740    ; CHECK-NEXT: {{  $}}1741    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01742    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11743    ; CHECK-NEXT: [[CMHSv4i16_:%[0-9]+]]:fpr64 = CMHSv4i16 [[COPY1]], [[COPY]]1744    ; CHECK-NEXT: $d0 = COPY [[CMHSv4i16_]]1745    ; CHECK-NEXT: RET_ReallyLR implicit $d01746    %0:fpr(<4 x s16>) = COPY $d01747    %1:fpr(<4 x s16>) = COPY $d11748    %4:fpr(<4 x s16>) = G_ICMP intpred(ule), %0(<4 x s16>), %11749    %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)1750    $d0 = COPY %3(<4 x s16>)1751    RET_ReallyLR implicit $d01752 1753...1754---1755name:            test_v16i8_ule1756alignment:       41757legalized:       true1758regBankSelected: true1759tracksRegLiveness: true1760registers:1761  - { id: 0, class: fpr }1762  - { id: 1, class: fpr }1763  - { id: 2, class: _ }1764  - { id: 3, class: fpr }1765  - { id: 4, class: fpr }1766machineFunctionInfo: {}1767body:             |1768  bb.1 (%ir-block.0):1769    liveins: $q0, $q11770 1771    ; CHECK-LABEL: name: test_v16i8_ule1772    ; CHECK: liveins: $q0, $q11773    ; CHECK-NEXT: {{  $}}1774    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q01775    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q11776    ; CHECK-NEXT: [[CMHSv16i8_:%[0-9]+]]:fpr128 = CMHSv16i8 [[COPY1]], [[COPY]]1777    ; CHECK-NEXT: $q0 = COPY [[CMHSv16i8_]]1778    ; CHECK-NEXT: RET_ReallyLR implicit $q01779    %0:fpr(<16 x s8>) = COPY $q01780    %1:fpr(<16 x s8>) = COPY $q11781    %4:fpr(<16 x s8>) = G_ICMP intpred(ule), %0(<16 x s8>), %11782    %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)1783    $q0 = COPY %3(<16 x s8>)1784    RET_ReallyLR implicit $q01785 1786...1787---1788name:            test_v8i8_ule1789alignment:       41790legalized:       true1791regBankSelected: true1792tracksRegLiveness: true1793registers:1794  - { id: 0, class: fpr }1795  - { id: 1, class: fpr }1796  - { id: 2, class: _ }1797  - { id: 3, class: fpr }1798  - { id: 4, class: fpr }1799machineFunctionInfo: {}1800body:             |1801  bb.1 (%ir-block.0):1802    liveins: $d0, $d11803 1804    ; CHECK-LABEL: name: test_v8i8_ule1805    ; CHECK: liveins: $d0, $d11806    ; CHECK-NEXT: {{  $}}1807    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01808    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11809    ; CHECK-NEXT: [[CMHSv8i8_:%[0-9]+]]:fpr64 = CMHSv8i8 [[COPY1]], [[COPY]]1810    ; CHECK-NEXT: $d0 = COPY [[CMHSv8i8_]]1811    ; CHECK-NEXT: RET_ReallyLR implicit $d01812    %0:fpr(<8 x s8>) = COPY $d01813    %1:fpr(<8 x s8>) = COPY $d11814    %4:fpr(<8 x s8>) = G_ICMP intpred(ule), %0(<8 x s8>), %11815    %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)1816    $d0 = COPY %3(<8 x s8>)1817    RET_ReallyLR implicit $d01818 1819...1820---1821name:            test_v2i64_sgt1822alignment:       41823legalized:       true1824regBankSelected: true1825tracksRegLiveness: true1826registers:1827  - { id: 0, class: fpr }1828  - { id: 1, class: fpr }1829  - { id: 2, class: _ }1830  - { id: 3, class: fpr }1831  - { id: 4, class: fpr }1832machineFunctionInfo: {}1833body:             |1834  bb.1 (%ir-block.0):1835    liveins: $q0, $q11836 1837    ; CHECK-LABEL: name: test_v2i64_sgt1838    ; CHECK: liveins: $q0, $q11839    ; CHECK-NEXT: {{  $}}1840    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q01841    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q11842    ; CHECK-NEXT: [[CMGTv2i64_:%[0-9]+]]:fpr128 = CMGTv2i64 [[COPY]], [[COPY1]]1843    ; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMGTv2i64_]]1844    ; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]]1845    ; CHECK-NEXT: RET_ReallyLR implicit $d01846    %0:fpr(<2 x s64>) = COPY $q01847    %1:fpr(<2 x s64>) = COPY $q11848    %4:fpr(<2 x s64>) = G_ICMP intpred(sgt), %0(<2 x s64>), %11849    %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)1850    $d0 = COPY %3(<2 x s32>)1851    RET_ReallyLR implicit $d01852 1853...1854---1855name:            test_v4i32_sgt1856alignment:       41857legalized:       true1858regBankSelected: true1859tracksRegLiveness: true1860registers:1861  - { id: 0, class: fpr }1862  - { id: 1, class: fpr }1863  - { id: 2, class: _ }1864  - { id: 3, class: fpr }1865  - { id: 4, class: fpr }1866machineFunctionInfo: {}1867body:             |1868  bb.1 (%ir-block.0):1869    liveins: $q0, $q11870 1871    ; CHECK-LABEL: name: test_v4i32_sgt1872    ; CHECK: liveins: $q0, $q11873    ; CHECK-NEXT: {{  $}}1874    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q01875    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q11876    ; CHECK-NEXT: [[CMGTv4i32_:%[0-9]+]]:fpr128 = CMGTv4i32 [[COPY]], [[COPY1]]1877    ; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMGTv4i32_]]1878    ; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]]1879    ; CHECK-NEXT: RET_ReallyLR implicit $d01880    %0:fpr(<4 x s32>) = COPY $q01881    %1:fpr(<4 x s32>) = COPY $q11882    %4:fpr(<4 x s32>) = G_ICMP intpred(sgt), %0(<4 x s32>), %11883    %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)1884    $d0 = COPY %3(<4 x s16>)1885    RET_ReallyLR implicit $d01886 1887...1888---1889name:            test_v2i32_sgt1890alignment:       41891legalized:       true1892regBankSelected: true1893tracksRegLiveness: true1894registers:1895  - { id: 0, class: fpr }1896  - { id: 1, class: fpr }1897  - { id: 2, class: _ }1898  - { id: 3, class: fpr }1899  - { id: 4, class: fpr }1900machineFunctionInfo: {}1901body:             |1902  bb.1 (%ir-block.0):1903    liveins: $d0, $d11904 1905    ; CHECK-LABEL: name: test_v2i32_sgt1906    ; CHECK: liveins: $d0, $d11907    ; CHECK-NEXT: {{  $}}1908    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01909    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11910    ; CHECK-NEXT: [[CMGTv2i32_:%[0-9]+]]:fpr64 = CMGTv2i32 [[COPY]], [[COPY1]]1911    ; CHECK-NEXT: $d0 = COPY [[CMGTv2i32_]]1912    ; CHECK-NEXT: RET_ReallyLR implicit $d01913    %0:fpr(<2 x s32>) = COPY $d01914    %1:fpr(<2 x s32>) = COPY $d11915    %4:fpr(<2 x s32>) = G_ICMP intpred(sgt), %0(<2 x s32>), %11916    %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)1917    $d0 = COPY %3(<2 x s32>)1918    RET_ReallyLR implicit $d01919 1920...1921---1922name:            test_v2i16_sgt1923alignment:       41924legalized:       true1925regBankSelected: true1926tracksRegLiveness: true1927registers:1928  - { id: 0, class: _ }1929  - { id: 1, class: _ }1930  - { id: 2, class: fpr }1931  - { id: 3, class: fpr }1932  - { id: 4, class: _ }1933  - { id: 5, class: fpr }1934  - { id: 6, class: _ }1935  - { id: 7, class: fpr }1936  - { id: 8, class: fpr }1937  - { id: 9, class: fpr }1938  - { id: 10, class: gpr }1939  - { id: 11, class: fpr }1940  - { id: 12, class: fpr }1941  - { id: 13, class: fpr }1942  - { id: 14, class: gpr }1943  - { id: 15, class: fpr }1944  - { id: 16, class: fpr }1945  - { id: 17, class: fpr }1946machineFunctionInfo: {}1947body:             |1948  bb.1 (%ir-block.0):1949    liveins: $d0, $d11950 1951    ; CHECK-LABEL: name: test_v2i16_sgt1952    ; CHECK: liveins: $d0, $d11953    ; CHECK-NEXT: {{  $}}1954    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01955    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11956    ; CHECK-NEXT: [[MOVIv2i32_:%[0-9]+]]:fpr64 = MOVIv2i32 16, 01957    ; CHECK-NEXT: [[SHLv2i32_shift:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY]], 161958    ; CHECK-NEXT: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[MOVIv2i32_]]1959    ; CHECK-NEXT: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift]], [[NEGv2i32_]]1960    ; CHECK-NEXT: [[MOVIv2i32_1:%[0-9]+]]:fpr64 = MOVIv2i32 16, 01961    ; CHECK-NEXT: [[SHLv2i32_shift1:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY1]], 161962    ; CHECK-NEXT: [[NEGv2i32_1:%[0-9]+]]:fpr64 = NEGv2i32 [[MOVIv2i32_1]]1963    ; CHECK-NEXT: [[SSHLv2i32_1:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift1]], [[NEGv2i32_1]]1964    ; CHECK-NEXT: [[CMGTv2i32_:%[0-9]+]]:fpr64 = CMGTv2i32 [[SSHLv2i32_]], [[SSHLv2i32_1]]1965    ; CHECK-NEXT: $d0 = COPY [[CMGTv2i32_]]1966    ; CHECK-NEXT: RET_ReallyLR implicit $d01967    %2:fpr(<2 x s32>) = COPY $d01968    %3:fpr(<2 x s32>) = COPY $d11969    %14:gpr(s32) = G_CONSTANT i32 161970    %15:fpr(<2 x s32>) = G_BUILD_VECTOR %14(s32), %14(s32)1971    %16:fpr(<2 x s32>) = COPY %2(<2 x s32>)1972    %17:fpr(<2 x s32>) = G_SHL %16, %15(<2 x s32>)1973    %7:fpr(<2 x s32>) = G_ASHR %17, %15(<2 x s32>)1974    %10:gpr(s32) = G_CONSTANT i32 161975    %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)1976    %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)1977    %13:fpr(<2 x s32>) = G_SHL %12, %11(<2 x s32>)1978    %8:fpr(<2 x s32>) = G_ASHR %13, %11(<2 x s32>)1979    %9:fpr(<2 x s32>) = G_ICMP intpred(sgt), %7(<2 x s32>), %81980    %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)1981    $d0 = COPY %5(<2 x s32>)1982    RET_ReallyLR implicit $d01983 1984...1985---1986name:            test_v8i16_sgt1987alignment:       41988legalized:       true1989regBankSelected: true1990tracksRegLiveness: true1991registers:1992  - { id: 0, class: fpr }1993  - { id: 1, class: fpr }1994  - { id: 2, class: _ }1995  - { id: 3, class: fpr }1996  - { id: 4, class: fpr }1997machineFunctionInfo: {}1998body:             |1999  bb.1 (%ir-block.0):2000    liveins: $q0, $q12001 2002    ; CHECK-LABEL: name: test_v8i16_sgt2003    ; CHECK: liveins: $q0, $q12004    ; CHECK-NEXT: {{  $}}2005    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q02006    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q12007    ; CHECK-NEXT: [[CMGTv8i16_:%[0-9]+]]:fpr128 = CMGTv8i16 [[COPY]], [[COPY1]]2008    ; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMGTv8i16_]]2009    ; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]]2010    ; CHECK-NEXT: RET_ReallyLR implicit $d02011    %0:fpr(<8 x s16>) = COPY $q02012    %1:fpr(<8 x s16>) = COPY $q12013    %4:fpr(<8 x s16>) = G_ICMP intpred(sgt), %0(<8 x s16>), %12014    %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)2015    $d0 = COPY %3(<8 x s8>)2016    RET_ReallyLR implicit $d02017 2018...2019---2020name:            test_v4i16_sgt2021alignment:       42022legalized:       true2023regBankSelected: true2024tracksRegLiveness: true2025registers:2026  - { id: 0, class: fpr }2027  - { id: 1, class: fpr }2028  - { id: 2, class: _ }2029  - { id: 3, class: fpr }2030  - { id: 4, class: fpr }2031machineFunctionInfo: {}2032body:             |2033  bb.1 (%ir-block.0):2034    liveins: $d0, $d12035 2036    ; CHECK-LABEL: name: test_v4i16_sgt2037    ; CHECK: liveins: $d0, $d12038    ; CHECK-NEXT: {{  $}}2039    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d02040    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d12041    ; CHECK-NEXT: [[CMGTv4i16_:%[0-9]+]]:fpr64 = CMGTv4i16 [[COPY]], [[COPY1]]2042    ; CHECK-NEXT: $d0 = COPY [[CMGTv4i16_]]2043    ; CHECK-NEXT: RET_ReallyLR implicit $d02044    %0:fpr(<4 x s16>) = COPY $d02045    %1:fpr(<4 x s16>) = COPY $d12046    %4:fpr(<4 x s16>) = G_ICMP intpred(sgt), %0(<4 x s16>), %12047    %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)2048    $d0 = COPY %3(<4 x s16>)2049    RET_ReallyLR implicit $d02050 2051...2052---2053name:            test_v16i8_sgt2054alignment:       42055legalized:       true2056regBankSelected: true2057tracksRegLiveness: true2058registers:2059  - { id: 0, class: fpr }2060  - { id: 1, class: fpr }2061  - { id: 2, class: _ }2062  - { id: 3, class: fpr }2063  - { id: 4, class: fpr }2064machineFunctionInfo: {}2065body:             |2066  bb.1 (%ir-block.0):2067    liveins: $q0, $q12068 2069    ; CHECK-LABEL: name: test_v16i8_sgt2070    ; CHECK: liveins: $q0, $q12071    ; CHECK-NEXT: {{  $}}2072    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q02073    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q12074    ; CHECK-NEXT: [[CMGTv16i8_:%[0-9]+]]:fpr128 = CMGTv16i8 [[COPY]], [[COPY1]]2075    ; CHECK-NEXT: $q0 = COPY [[CMGTv16i8_]]2076    ; CHECK-NEXT: RET_ReallyLR implicit $q02077    %0:fpr(<16 x s8>) = COPY $q02078    %1:fpr(<16 x s8>) = COPY $q12079    %4:fpr(<16 x s8>) = G_ICMP intpred(sgt), %0(<16 x s8>), %12080    %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)2081    $q0 = COPY %3(<16 x s8>)2082    RET_ReallyLR implicit $q02083 2084...2085---2086name:            test_v8i8_sgt2087alignment:       42088legalized:       true2089regBankSelected: true2090tracksRegLiveness: true2091registers:2092  - { id: 0, class: fpr }2093  - { id: 1, class: fpr }2094  - { id: 2, class: _ }2095  - { id: 3, class: fpr }2096  - { id: 4, class: fpr }2097machineFunctionInfo: {}2098body:             |2099  bb.1 (%ir-block.0):2100    liveins: $d0, $d12101 2102    ; CHECK-LABEL: name: test_v8i8_sgt2103    ; CHECK: liveins: $d0, $d12104    ; CHECK-NEXT: {{  $}}2105    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d02106    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d12107    ; CHECK-NEXT: [[CMGTv8i8_:%[0-9]+]]:fpr64 = CMGTv8i8 [[COPY]], [[COPY1]]2108    ; CHECK-NEXT: $d0 = COPY [[CMGTv8i8_]]2109    ; CHECK-NEXT: RET_ReallyLR implicit $d02110    %0:fpr(<8 x s8>) = COPY $d02111    %1:fpr(<8 x s8>) = COPY $d12112    %4:fpr(<8 x s8>) = G_ICMP intpred(sgt), %0(<8 x s8>), %12113    %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)2114    $d0 = COPY %3(<8 x s8>)2115    RET_ReallyLR implicit $d02116 2117...2118---2119name:            test_v2i64_sge2120alignment:       42121legalized:       true2122regBankSelected: true2123tracksRegLiveness: true2124registers:2125  - { id: 0, class: fpr }2126  - { id: 1, class: fpr }2127  - { id: 2, class: _ }2128  - { id: 3, class: fpr }2129  - { id: 4, class: fpr }2130machineFunctionInfo: {}2131body:             |2132  bb.1 (%ir-block.0):2133    liveins: $q0, $q12134 2135    ; CHECK-LABEL: name: test_v2i64_sge2136    ; CHECK: liveins: $q0, $q12137    ; CHECK-NEXT: {{  $}}2138    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q02139    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q12140    ; CHECK-NEXT: [[CMGEv2i64_:%[0-9]+]]:fpr128 = CMGEv2i64 [[COPY]], [[COPY1]]2141    ; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMGEv2i64_]]2142    ; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]]2143    ; CHECK-NEXT: RET_ReallyLR implicit $d02144    %0:fpr(<2 x s64>) = COPY $q02145    %1:fpr(<2 x s64>) = COPY $q12146    %4:fpr(<2 x s64>) = G_ICMP intpred(sge), %0(<2 x s64>), %12147    %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)2148    $d0 = COPY %3(<2 x s32>)2149    RET_ReallyLR implicit $d02150 2151...2152---2153name:            test_v4i32_sge2154alignment:       42155legalized:       true2156regBankSelected: true2157tracksRegLiveness: true2158registers:2159  - { id: 0, class: fpr }2160  - { id: 1, class: fpr }2161  - { id: 2, class: _ }2162  - { id: 3, class: fpr }2163  - { id: 4, class: fpr }2164machineFunctionInfo: {}2165body:             |2166  bb.1 (%ir-block.0):2167    liveins: $q0, $q12168 2169    ; CHECK-LABEL: name: test_v4i32_sge2170    ; CHECK: liveins: $q0, $q12171    ; CHECK-NEXT: {{  $}}2172    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q02173    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q12174    ; CHECK-NEXT: [[CMGEv4i32_:%[0-9]+]]:fpr128 = CMGEv4i32 [[COPY]], [[COPY1]]2175    ; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMGEv4i32_]]2176    ; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]]2177    ; CHECK-NEXT: RET_ReallyLR implicit $d02178    %0:fpr(<4 x s32>) = COPY $q02179    %1:fpr(<4 x s32>) = COPY $q12180    %4:fpr(<4 x s32>) = G_ICMP intpred(sge), %0(<4 x s32>), %12181    %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)2182    $d0 = COPY %3(<4 x s16>)2183    RET_ReallyLR implicit $d02184 2185...2186---2187name:            test_v2i32_sge2188alignment:       42189legalized:       true2190regBankSelected: true2191tracksRegLiveness: true2192registers:2193  - { id: 0, class: fpr }2194  - { id: 1, class: fpr }2195  - { id: 2, class: _ }2196  - { id: 3, class: fpr }2197  - { id: 4, class: fpr }2198machineFunctionInfo: {}2199body:             |2200  bb.1 (%ir-block.0):2201    liveins: $d0, $d12202 2203    ; CHECK-LABEL: name: test_v2i32_sge2204    ; CHECK: liveins: $d0, $d12205    ; CHECK-NEXT: {{  $}}2206    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d02207    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d12208    ; CHECK-NEXT: [[CMGEv2i32_:%[0-9]+]]:fpr64 = CMGEv2i32 [[COPY]], [[COPY1]]2209    ; CHECK-NEXT: $d0 = COPY [[CMGEv2i32_]]2210    ; CHECK-NEXT: RET_ReallyLR implicit $d02211    %0:fpr(<2 x s32>) = COPY $d02212    %1:fpr(<2 x s32>) = COPY $d12213    %4:fpr(<2 x s32>) = G_ICMP intpred(sge), %0(<2 x s32>), %12214    %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)2215    $d0 = COPY %3(<2 x s32>)2216    RET_ReallyLR implicit $d02217 2218...2219---2220name:            test_v2i16_sge2221alignment:       42222legalized:       true2223regBankSelected: true2224tracksRegLiveness: true2225registers:2226  - { id: 0, class: _ }2227  - { id: 1, class: _ }2228  - { id: 2, class: fpr }2229  - { id: 3, class: fpr }2230  - { id: 4, class: _ }2231  - { id: 5, class: fpr }2232  - { id: 6, class: _ }2233  - { id: 7, class: fpr }2234  - { id: 8, class: fpr }2235  - { id: 9, class: fpr }2236  - { id: 10, class: gpr }2237  - { id: 11, class: fpr }2238  - { id: 12, class: fpr }2239  - { id: 13, class: fpr }2240  - { id: 14, class: gpr }2241  - { id: 15, class: fpr }2242  - { id: 16, class: fpr }2243  - { id: 17, class: fpr }2244machineFunctionInfo: {}2245body:             |2246  bb.1 (%ir-block.0):2247    liveins: $d0, $d12248 2249    ; CHECK-LABEL: name: test_v2i16_sge2250    ; CHECK: liveins: $d0, $d12251    ; CHECK-NEXT: {{  $}}2252    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d02253    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d12254    ; CHECK-NEXT: [[MOVIv2i32_:%[0-9]+]]:fpr64 = MOVIv2i32 16, 02255    ; CHECK-NEXT: [[SHLv2i32_shift:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY]], 162256    ; CHECK-NEXT: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[MOVIv2i32_]]2257    ; CHECK-NEXT: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift]], [[NEGv2i32_]]2258    ; CHECK-NEXT: [[MOVIv2i32_1:%[0-9]+]]:fpr64 = MOVIv2i32 16, 02259    ; CHECK-NEXT: [[SHLv2i32_shift1:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY1]], 162260    ; CHECK-NEXT: [[NEGv2i32_1:%[0-9]+]]:fpr64 = NEGv2i32 [[MOVIv2i32_1]]2261    ; CHECK-NEXT: [[SSHLv2i32_1:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift1]], [[NEGv2i32_1]]2262    ; CHECK-NEXT: [[CMGEv2i32_:%[0-9]+]]:fpr64 = CMGEv2i32 [[SSHLv2i32_]], [[SSHLv2i32_1]]2263    ; CHECK-NEXT: $d0 = COPY [[CMGEv2i32_]]2264    ; CHECK-NEXT: RET_ReallyLR implicit $d02265    %2:fpr(<2 x s32>) = COPY $d02266    %3:fpr(<2 x s32>) = COPY $d12267    %14:gpr(s32) = G_CONSTANT i32 162268    %15:fpr(<2 x s32>) = G_BUILD_VECTOR %14(s32), %14(s32)2269    %16:fpr(<2 x s32>) = COPY %2(<2 x s32>)2270    %17:fpr(<2 x s32>) = G_SHL %16, %15(<2 x s32>)2271    %7:fpr(<2 x s32>) = G_ASHR %17, %15(<2 x s32>)2272    %10:gpr(s32) = G_CONSTANT i32 162273    %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)2274    %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)2275    %13:fpr(<2 x s32>) = G_SHL %12, %11(<2 x s32>)2276    %8:fpr(<2 x s32>) = G_ASHR %13, %11(<2 x s32>)2277    %9:fpr(<2 x s32>) = G_ICMP intpred(sge), %7(<2 x s32>), %82278    %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)2279    $d0 = COPY %5(<2 x s32>)2280    RET_ReallyLR implicit $d02281 2282...2283---2284name:            test_v8i16_sge2285alignment:       42286legalized:       true2287regBankSelected: true2288tracksRegLiveness: true2289registers:2290  - { id: 0, class: fpr }2291  - { id: 1, class: fpr }2292  - { id: 2, class: _ }2293  - { id: 3, class: fpr }2294  - { id: 4, class: fpr }2295machineFunctionInfo: {}2296body:             |2297  bb.1 (%ir-block.0):2298    liveins: $q0, $q12299 2300    ; CHECK-LABEL: name: test_v8i16_sge2301    ; CHECK: liveins: $q0, $q12302    ; CHECK-NEXT: {{  $}}2303    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q02304    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q12305    ; CHECK-NEXT: [[CMGEv8i16_:%[0-9]+]]:fpr128 = CMGEv8i16 [[COPY]], [[COPY1]]2306    ; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMGEv8i16_]]2307    ; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]]2308    ; CHECK-NEXT: RET_ReallyLR implicit $d02309    %0:fpr(<8 x s16>) = COPY $q02310    %1:fpr(<8 x s16>) = COPY $q12311    %4:fpr(<8 x s16>) = G_ICMP intpred(sge), %0(<8 x s16>), %12312    %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)2313    $d0 = COPY %3(<8 x s8>)2314    RET_ReallyLR implicit $d02315 2316...2317---2318name:            test_v4i16_sge2319alignment:       42320legalized:       true2321regBankSelected: true2322tracksRegLiveness: true2323registers:2324  - { id: 0, class: fpr }2325  - { id: 1, class: fpr }2326  - { id: 2, class: _ }2327  - { id: 3, class: fpr }2328  - { id: 4, class: fpr }2329machineFunctionInfo: {}2330body:             |2331  bb.1 (%ir-block.0):2332    liveins: $d0, $d12333 2334    ; CHECK-LABEL: name: test_v4i16_sge2335    ; CHECK: liveins: $d0, $d12336    ; CHECK-NEXT: {{  $}}2337    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d02338    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d12339    ; CHECK-NEXT: [[CMGEv4i16_:%[0-9]+]]:fpr64 = CMGEv4i16 [[COPY]], [[COPY1]]2340    ; CHECK-NEXT: $d0 = COPY [[CMGEv4i16_]]2341    ; CHECK-NEXT: RET_ReallyLR implicit $d02342    %0:fpr(<4 x s16>) = COPY $d02343    %1:fpr(<4 x s16>) = COPY $d12344    %4:fpr(<4 x s16>) = G_ICMP intpred(sge), %0(<4 x s16>), %12345    %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)2346    $d0 = COPY %3(<4 x s16>)2347    RET_ReallyLR implicit $d02348 2349...2350---2351name:            test_v16i8_sge2352alignment:       42353legalized:       true2354regBankSelected: true2355tracksRegLiveness: true2356registers:2357  - { id: 0, class: fpr }2358  - { id: 1, class: fpr }2359  - { id: 2, class: _ }2360  - { id: 3, class: fpr }2361  - { id: 4, class: fpr }2362machineFunctionInfo: {}2363body:             |2364  bb.1 (%ir-block.0):2365    liveins: $q0, $q12366 2367    ; CHECK-LABEL: name: test_v16i8_sge2368    ; CHECK: liveins: $q0, $q12369    ; CHECK-NEXT: {{  $}}2370    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q02371    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q12372    ; CHECK-NEXT: [[CMGEv16i8_:%[0-9]+]]:fpr128 = CMGEv16i8 [[COPY]], [[COPY1]]2373    ; CHECK-NEXT: $q0 = COPY [[CMGEv16i8_]]2374    ; CHECK-NEXT: RET_ReallyLR implicit $q02375    %0:fpr(<16 x s8>) = COPY $q02376    %1:fpr(<16 x s8>) = COPY $q12377    %4:fpr(<16 x s8>) = G_ICMP intpred(sge), %0(<16 x s8>), %12378    %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)2379    $q0 = COPY %3(<16 x s8>)2380    RET_ReallyLR implicit $q02381 2382...2383---2384name:            test_v8i8_sge2385alignment:       42386legalized:       true2387regBankSelected: true2388tracksRegLiveness: true2389registers:2390  - { id: 0, class: fpr }2391  - { id: 1, class: fpr }2392  - { id: 2, class: _ }2393  - { id: 3, class: fpr }2394  - { id: 4, class: fpr }2395machineFunctionInfo: {}2396body:             |2397  bb.1 (%ir-block.0):2398    liveins: $d0, $d12399 2400    ; CHECK-LABEL: name: test_v8i8_sge2401    ; CHECK: liveins: $d0, $d12402    ; CHECK-NEXT: {{  $}}2403    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d02404    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d12405    ; CHECK-NEXT: [[CMGEv8i8_:%[0-9]+]]:fpr64 = CMGEv8i8 [[COPY]], [[COPY1]]2406    ; CHECK-NEXT: $d0 = COPY [[CMGEv8i8_]]2407    ; CHECK-NEXT: RET_ReallyLR implicit $d02408    %0:fpr(<8 x s8>) = COPY $d02409    %1:fpr(<8 x s8>) = COPY $d12410    %4:fpr(<8 x s8>) = G_ICMP intpred(sge), %0(<8 x s8>), %12411    %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)2412    $d0 = COPY %3(<8 x s8>)2413    RET_ReallyLR implicit $d02414 2415...2416---2417name:            test_v2i64_slt2418alignment:       42419legalized:       true2420regBankSelected: true2421tracksRegLiveness: true2422registers:2423  - { id: 0, class: fpr }2424  - { id: 1, class: fpr }2425  - { id: 2, class: _ }2426  - { id: 3, class: fpr }2427  - { id: 4, class: fpr }2428machineFunctionInfo: {}2429body:             |2430  bb.1 (%ir-block.0):2431    liveins: $q0, $q12432 2433    ; CHECK-LABEL: name: test_v2i64_slt2434    ; CHECK: liveins: $q0, $q12435    ; CHECK-NEXT: {{  $}}2436    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q02437    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q12438    ; CHECK-NEXT: [[CMGTv2i64_:%[0-9]+]]:fpr128 = CMGTv2i64 [[COPY1]], [[COPY]]2439    ; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMGTv2i64_]]2440    ; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]]2441    ; CHECK-NEXT: RET_ReallyLR implicit $d02442    %0:fpr(<2 x s64>) = COPY $q02443    %1:fpr(<2 x s64>) = COPY $q12444    %4:fpr(<2 x s64>) = G_ICMP intpred(slt), %0(<2 x s64>), %12445    %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)2446    $d0 = COPY %3(<2 x s32>)2447    RET_ReallyLR implicit $d02448 2449...2450---2451name:            test_v4i32_slt2452alignment:       42453legalized:       true2454regBankSelected: true2455tracksRegLiveness: true2456registers:2457  - { id: 0, class: fpr }2458  - { id: 1, class: fpr }2459  - { id: 2, class: _ }2460  - { id: 3, class: fpr }2461  - { id: 4, class: fpr }2462machineFunctionInfo: {}2463body:             |2464  bb.1 (%ir-block.0):2465    liveins: $q0, $q12466 2467    ; CHECK-LABEL: name: test_v4i32_slt2468    ; CHECK: liveins: $q0, $q12469    ; CHECK-NEXT: {{  $}}2470    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q02471    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q12472    ; CHECK-NEXT: [[CMGTv4i32_:%[0-9]+]]:fpr128 = CMGTv4i32 [[COPY1]], [[COPY]]2473    ; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMGTv4i32_]]2474    ; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]]2475    ; CHECK-NEXT: RET_ReallyLR implicit $d02476    %0:fpr(<4 x s32>) = COPY $q02477    %1:fpr(<4 x s32>) = COPY $q12478    %4:fpr(<4 x s32>) = G_ICMP intpred(slt), %0(<4 x s32>), %12479    %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)2480    $d0 = COPY %3(<4 x s16>)2481    RET_ReallyLR implicit $d02482 2483...2484---2485name:            test_v2i32_slt2486alignment:       42487legalized:       true2488regBankSelected: true2489tracksRegLiveness: true2490registers:2491  - { id: 0, class: fpr }2492  - { id: 1, class: fpr }2493  - { id: 2, class: _ }2494  - { id: 3, class: fpr }2495  - { id: 4, class: fpr }2496machineFunctionInfo: {}2497body:             |2498  bb.1 (%ir-block.0):2499    liveins: $d0, $d12500 2501    ; CHECK-LABEL: name: test_v2i32_slt2502    ; CHECK: liveins: $d0, $d12503    ; CHECK-NEXT: {{  $}}2504    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d02505    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d12506    ; CHECK-NEXT: [[CMGTv2i32_:%[0-9]+]]:fpr64 = CMGTv2i32 [[COPY1]], [[COPY]]2507    ; CHECK-NEXT: $d0 = COPY [[CMGTv2i32_]]2508    ; CHECK-NEXT: RET_ReallyLR implicit $d02509    %0:fpr(<2 x s32>) = COPY $d02510    %1:fpr(<2 x s32>) = COPY $d12511    %4:fpr(<2 x s32>) = G_ICMP intpred(slt), %0(<2 x s32>), %12512    %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)2513    $d0 = COPY %3(<2 x s32>)2514    RET_ReallyLR implicit $d02515 2516...2517---2518name:            test_v2i16_slt2519alignment:       42520legalized:       true2521regBankSelected: true2522tracksRegLiveness: true2523registers:2524  - { id: 0, class: _ }2525  - { id: 1, class: _ }2526  - { id: 2, class: fpr }2527  - { id: 3, class: fpr }2528  - { id: 4, class: _ }2529  - { id: 5, class: fpr }2530  - { id: 6, class: _ }2531  - { id: 7, class: fpr }2532  - { id: 8, class: fpr }2533  - { id: 9, class: fpr }2534  - { id: 10, class: gpr }2535  - { id: 11, class: fpr }2536  - { id: 12, class: fpr }2537  - { id: 13, class: fpr }2538  - { id: 14, class: gpr }2539  - { id: 15, class: fpr }2540  - { id: 16, class: fpr }2541  - { id: 17, class: fpr }2542machineFunctionInfo: {}2543body:             |2544  bb.1 (%ir-block.0):2545    liveins: $d0, $d12546 2547    ; CHECK-LABEL: name: test_v2i16_slt2548    ; CHECK: liveins: $d0, $d12549    ; CHECK-NEXT: {{  $}}2550    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d02551    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d12552    ; CHECK-NEXT: [[MOVIv2i32_:%[0-9]+]]:fpr64 = MOVIv2i32 16, 02553    ; CHECK-NEXT: [[SHLv2i32_shift:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY]], 162554    ; CHECK-NEXT: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[MOVIv2i32_]]2555    ; CHECK-NEXT: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift]], [[NEGv2i32_]]2556    ; CHECK-NEXT: [[MOVIv2i32_1:%[0-9]+]]:fpr64 = MOVIv2i32 16, 02557    ; CHECK-NEXT: [[SHLv2i32_shift1:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY1]], 162558    ; CHECK-NEXT: [[NEGv2i32_1:%[0-9]+]]:fpr64 = NEGv2i32 [[MOVIv2i32_1]]2559    ; CHECK-NEXT: [[SSHLv2i32_1:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift1]], [[NEGv2i32_1]]2560    ; CHECK-NEXT: [[CMGTv2i32_:%[0-9]+]]:fpr64 = CMGTv2i32 [[SSHLv2i32_1]], [[SSHLv2i32_]]2561    ; CHECK-NEXT: $d0 = COPY [[CMGTv2i32_]]2562    ; CHECK-NEXT: RET_ReallyLR implicit $d02563    %2:fpr(<2 x s32>) = COPY $d02564    %3:fpr(<2 x s32>) = COPY $d12565    %14:gpr(s32) = G_CONSTANT i32 162566    %15:fpr(<2 x s32>) = G_BUILD_VECTOR %14(s32), %14(s32)2567    %16:fpr(<2 x s32>) = COPY %2(<2 x s32>)2568    %17:fpr(<2 x s32>) = G_SHL %16, %15(<2 x s32>)2569    %7:fpr(<2 x s32>) = G_ASHR %17, %15(<2 x s32>)2570    %10:gpr(s32) = G_CONSTANT i32 162571    %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)2572    %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)2573    %13:fpr(<2 x s32>) = G_SHL %12, %11(<2 x s32>)2574    %8:fpr(<2 x s32>) = G_ASHR %13, %11(<2 x s32>)2575    %9:fpr(<2 x s32>) = G_ICMP intpred(slt), %7(<2 x s32>), %82576    %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)2577    $d0 = COPY %5(<2 x s32>)2578    RET_ReallyLR implicit $d02579 2580...2581---2582name:            test_v8i16_slt2583alignment:       42584legalized:       true2585regBankSelected: true2586tracksRegLiveness: true2587registers:2588  - { id: 0, class: fpr }2589  - { id: 1, class: fpr }2590  - { id: 2, class: _ }2591  - { id: 3, class: fpr }2592  - { id: 4, class: fpr }2593machineFunctionInfo: {}2594body:             |2595  bb.1 (%ir-block.0):2596    liveins: $q0, $q12597 2598    ; CHECK-LABEL: name: test_v8i16_slt2599    ; CHECK: liveins: $q0, $q12600    ; CHECK-NEXT: {{  $}}2601    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q02602    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q12603    ; CHECK-NEXT: [[CMGTv8i16_:%[0-9]+]]:fpr128 = CMGTv8i16 [[COPY1]], [[COPY]]2604    ; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMGTv8i16_]]2605    ; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]]2606    ; CHECK-NEXT: RET_ReallyLR implicit $d02607    %0:fpr(<8 x s16>) = COPY $q02608    %1:fpr(<8 x s16>) = COPY $q12609    %4:fpr(<8 x s16>) = G_ICMP intpred(slt), %0(<8 x s16>), %12610    %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)2611    $d0 = COPY %3(<8 x s8>)2612    RET_ReallyLR implicit $d02613 2614...2615---2616name:            test_v4i16_slt2617alignment:       42618legalized:       true2619regBankSelected: true2620tracksRegLiveness: true2621registers:2622  - { id: 0, class: fpr }2623  - { id: 1, class: fpr }2624  - { id: 2, class: _ }2625  - { id: 3, class: fpr }2626  - { id: 4, class: fpr }2627machineFunctionInfo: {}2628body:             |2629  bb.1 (%ir-block.0):2630    liveins: $d0, $d12631 2632    ; CHECK-LABEL: name: test_v4i16_slt2633    ; CHECK: liveins: $d0, $d12634    ; CHECK-NEXT: {{  $}}2635    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d02636    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d12637    ; CHECK-NEXT: [[CMGTv4i16_:%[0-9]+]]:fpr64 = CMGTv4i16 [[COPY1]], [[COPY]]2638    ; CHECK-NEXT: $d0 = COPY [[CMGTv4i16_]]2639    ; CHECK-NEXT: RET_ReallyLR implicit $d02640    %0:fpr(<4 x s16>) = COPY $d02641    %1:fpr(<4 x s16>) = COPY $d12642    %4:fpr(<4 x s16>) = G_ICMP intpred(slt), %0(<4 x s16>), %12643    %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)2644    $d0 = COPY %3(<4 x s16>)2645    RET_ReallyLR implicit $d02646 2647...2648---2649name:            test_v16i8_slt2650alignment:       42651legalized:       true2652regBankSelected: true2653tracksRegLiveness: true2654registers:2655  - { id: 0, class: fpr }2656  - { id: 1, class: fpr }2657  - { id: 2, class: _ }2658  - { id: 3, class: fpr }2659  - { id: 4, class: fpr }2660machineFunctionInfo: {}2661body:             |2662  bb.1 (%ir-block.0):2663    liveins: $q0, $q12664 2665    ; CHECK-LABEL: name: test_v16i8_slt2666    ; CHECK: liveins: $q0, $q12667    ; CHECK-NEXT: {{  $}}2668    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q02669    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q12670    ; CHECK-NEXT: [[CMGTv16i8_:%[0-9]+]]:fpr128 = CMGTv16i8 [[COPY1]], [[COPY]]2671    ; CHECK-NEXT: $q0 = COPY [[CMGTv16i8_]]2672    ; CHECK-NEXT: RET_ReallyLR implicit $q02673    %0:fpr(<16 x s8>) = COPY $q02674    %1:fpr(<16 x s8>) = COPY $q12675    %4:fpr(<16 x s8>) = G_ICMP intpred(slt), %0(<16 x s8>), %12676    %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)2677    $q0 = COPY %3(<16 x s8>)2678    RET_ReallyLR implicit $q02679 2680...2681---2682name:            test_v8i8_slt2683alignment:       42684legalized:       true2685regBankSelected: true2686tracksRegLiveness: true2687registers:2688  - { id: 0, class: fpr }2689  - { id: 1, class: fpr }2690  - { id: 2, class: _ }2691  - { id: 3, class: fpr }2692  - { id: 4, class: fpr }2693machineFunctionInfo: {}2694body:             |2695  bb.1 (%ir-block.0):2696    liveins: $d0, $d12697 2698    ; CHECK-LABEL: name: test_v8i8_slt2699    ; CHECK: liveins: $d0, $d12700    ; CHECK-NEXT: {{  $}}2701    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d02702    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d12703    ; CHECK-NEXT: [[CMGTv8i8_:%[0-9]+]]:fpr64 = CMGTv8i8 [[COPY1]], [[COPY]]2704    ; CHECK-NEXT: $d0 = COPY [[CMGTv8i8_]]2705    ; CHECK-NEXT: RET_ReallyLR implicit $d02706    %0:fpr(<8 x s8>) = COPY $d02707    %1:fpr(<8 x s8>) = COPY $d12708    %4:fpr(<8 x s8>) = G_ICMP intpred(slt), %0(<8 x s8>), %12709    %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)2710    $d0 = COPY %3(<8 x s8>)2711    RET_ReallyLR implicit $d02712 2713...2714---2715name:            test_v2i64_sle2716alignment:       42717legalized:       true2718regBankSelected: true2719tracksRegLiveness: true2720registers:2721  - { id: 0, class: fpr }2722  - { id: 1, class: fpr }2723  - { id: 2, class: _ }2724  - { id: 3, class: fpr }2725  - { id: 4, class: fpr }2726machineFunctionInfo: {}2727body:             |2728  bb.1 (%ir-block.0):2729    liveins: $q0, $q12730 2731    ; CHECK-LABEL: name: test_v2i64_sle2732    ; CHECK: liveins: $q0, $q12733    ; CHECK-NEXT: {{  $}}2734    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q02735    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q12736    ; CHECK-NEXT: [[CMGEv2i64_:%[0-9]+]]:fpr128 = CMGEv2i64 [[COPY1]], [[COPY]]2737    ; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMGEv2i64_]]2738    ; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]]2739    ; CHECK-NEXT: RET_ReallyLR implicit $d02740    %0:fpr(<2 x s64>) = COPY $q02741    %1:fpr(<2 x s64>) = COPY $q12742    %4:fpr(<2 x s64>) = G_ICMP intpred(sle), %0(<2 x s64>), %12743    %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)2744    $d0 = COPY %3(<2 x s32>)2745    RET_ReallyLR implicit $d02746 2747...2748---2749name:            test_v4i32_sle2750alignment:       42751legalized:       true2752regBankSelected: true2753tracksRegLiveness: true2754registers:2755  - { id: 0, class: fpr }2756  - { id: 1, class: fpr }2757  - { id: 2, class: _ }2758  - { id: 3, class: fpr }2759  - { id: 4, class: fpr }2760machineFunctionInfo: {}2761body:             |2762  bb.1 (%ir-block.0):2763    liveins: $q0, $q12764 2765    ; CHECK-LABEL: name: test_v4i32_sle2766    ; CHECK: liveins: $q0, $q12767    ; CHECK-NEXT: {{  $}}2768    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q02769    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q12770    ; CHECK-NEXT: [[CMGEv4i32_:%[0-9]+]]:fpr128 = CMGEv4i32 [[COPY1]], [[COPY]]2771    ; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMGEv4i32_]]2772    ; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]]2773    ; CHECK-NEXT: RET_ReallyLR implicit $d02774    %0:fpr(<4 x s32>) = COPY $q02775    %1:fpr(<4 x s32>) = COPY $q12776    %4:fpr(<4 x s32>) = G_ICMP intpred(sle), %0(<4 x s32>), %12777    %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)2778    $d0 = COPY %3(<4 x s16>)2779    RET_ReallyLR implicit $d02780 2781...2782---2783name:            test_v2i32_sle2784alignment:       42785legalized:       true2786regBankSelected: true2787tracksRegLiveness: true2788registers:2789  - { id: 0, class: fpr }2790  - { id: 1, class: fpr }2791  - { id: 2, class: _ }2792  - { id: 3, class: fpr }2793  - { id: 4, class: fpr }2794machineFunctionInfo: {}2795body:             |2796  bb.1 (%ir-block.0):2797    liveins: $d0, $d12798 2799    ; CHECK-LABEL: name: test_v2i32_sle2800    ; CHECK: liveins: $d0, $d12801    ; CHECK-NEXT: {{  $}}2802    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d02803    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d12804    ; CHECK-NEXT: [[CMGEv2i32_:%[0-9]+]]:fpr64 = CMGEv2i32 [[COPY1]], [[COPY]]2805    ; CHECK-NEXT: $d0 = COPY [[CMGEv2i32_]]2806    ; CHECK-NEXT: RET_ReallyLR implicit $d02807    %0:fpr(<2 x s32>) = COPY $d02808    %1:fpr(<2 x s32>) = COPY $d12809    %4:fpr(<2 x s32>) = G_ICMP intpred(sle), %0(<2 x s32>), %12810    %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)2811    $d0 = COPY %3(<2 x s32>)2812    RET_ReallyLR implicit $d02813 2814...2815---2816name:            test_v2i16_sle2817alignment:       42818legalized:       true2819regBankSelected: true2820tracksRegLiveness: true2821registers:2822  - { id: 0, class: _ }2823  - { id: 1, class: _ }2824  - { id: 2, class: fpr }2825  - { id: 3, class: fpr }2826  - { id: 4, class: _ }2827  - { id: 5, class: fpr }2828  - { id: 6, class: _ }2829  - { id: 7, class: fpr }2830  - { id: 8, class: fpr }2831  - { id: 9, class: fpr }2832  - { id: 10, class: gpr }2833  - { id: 11, class: fpr }2834  - { id: 12, class: fpr }2835  - { id: 13, class: fpr }2836  - { id: 14, class: gpr }2837  - { id: 15, class: fpr }2838  - { id: 16, class: fpr }2839  - { id: 17, class: fpr }2840machineFunctionInfo: {}2841body:             |2842  bb.1 (%ir-block.0):2843    liveins: $d0, $d12844 2845    ; CHECK-LABEL: name: test_v2i16_sle2846    ; CHECK: liveins: $d0, $d12847    ; CHECK-NEXT: {{  $}}2848    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d02849    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d12850    ; CHECK-NEXT: [[MOVIv2i32_:%[0-9]+]]:fpr64 = MOVIv2i32 16, 02851    ; CHECK-NEXT: [[SHLv2i32_shift:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY]], 162852    ; CHECK-NEXT: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[MOVIv2i32_]]2853    ; CHECK-NEXT: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift]], [[NEGv2i32_]]2854    ; CHECK-NEXT: [[MOVIv2i32_1:%[0-9]+]]:fpr64 = MOVIv2i32 16, 02855    ; CHECK-NEXT: [[SHLv2i32_shift1:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY1]], 162856    ; CHECK-NEXT: [[NEGv2i32_1:%[0-9]+]]:fpr64 = NEGv2i32 [[MOVIv2i32_1]]2857    ; CHECK-NEXT: [[SSHLv2i32_1:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift1]], [[NEGv2i32_1]]2858    ; CHECK-NEXT: [[CMGEv2i32_:%[0-9]+]]:fpr64 = CMGEv2i32 [[SSHLv2i32_1]], [[SSHLv2i32_]]2859    ; CHECK-NEXT: $d0 = COPY [[CMGEv2i32_]]2860    ; CHECK-NEXT: RET_ReallyLR implicit $d02861    %2:fpr(<2 x s32>) = COPY $d02862    %3:fpr(<2 x s32>) = COPY $d12863    %14:gpr(s32) = G_CONSTANT i32 162864    %15:fpr(<2 x s32>) = G_BUILD_VECTOR %14(s32), %14(s32)2865    %16:fpr(<2 x s32>) = COPY %2(<2 x s32>)2866    %17:fpr(<2 x s32>) = G_SHL %16, %15(<2 x s32>)2867    %7:fpr(<2 x s32>) = G_ASHR %17, %15(<2 x s32>)2868    %10:gpr(s32) = G_CONSTANT i32 162869    %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)2870    %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)2871    %13:fpr(<2 x s32>) = G_SHL %12, %11(<2 x s32>)2872    %8:fpr(<2 x s32>) = G_ASHR %13, %11(<2 x s32>)2873    %9:fpr(<2 x s32>) = G_ICMP intpred(sle), %7(<2 x s32>), %82874    %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)2875    $d0 = COPY %5(<2 x s32>)2876    RET_ReallyLR implicit $d02877 2878...2879---2880name:            test_v8i16_sle2881alignment:       42882legalized:       true2883regBankSelected: true2884tracksRegLiveness: true2885registers:2886  - { id: 0, class: fpr }2887  - { id: 1, class: fpr }2888  - { id: 2, class: _ }2889  - { id: 3, class: fpr }2890  - { id: 4, class: fpr }2891machineFunctionInfo: {}2892body:             |2893  bb.1 (%ir-block.0):2894    liveins: $q0, $q12895 2896    ; CHECK-LABEL: name: test_v8i16_sle2897    ; CHECK: liveins: $q0, $q12898    ; CHECK-NEXT: {{  $}}2899    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q02900    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q12901    ; CHECK-NEXT: [[CMGEv8i16_:%[0-9]+]]:fpr128 = CMGEv8i16 [[COPY1]], [[COPY]]2902    ; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMGEv8i16_]]2903    ; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]]2904    ; CHECK-NEXT: RET_ReallyLR implicit $d02905    %0:fpr(<8 x s16>) = COPY $q02906    %1:fpr(<8 x s16>) = COPY $q12907    %4:fpr(<8 x s16>) = G_ICMP intpred(sle), %0(<8 x s16>), %12908    %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)2909    $d0 = COPY %3(<8 x s8>)2910    RET_ReallyLR implicit $d02911 2912...2913---2914name:            test_v4i16_sle2915alignment:       42916legalized:       true2917regBankSelected: true2918tracksRegLiveness: true2919registers:2920  - { id: 0, class: fpr }2921  - { id: 1, class: fpr }2922  - { id: 2, class: _ }2923  - { id: 3, class: fpr }2924  - { id: 4, class: fpr }2925machineFunctionInfo: {}2926body:             |2927  bb.1 (%ir-block.0):2928    liveins: $d0, $d12929 2930    ; CHECK-LABEL: name: test_v4i16_sle2931    ; CHECK: liveins: $d0, $d12932    ; CHECK-NEXT: {{  $}}2933    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d02934    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d12935    ; CHECK-NEXT: [[CMGEv4i16_:%[0-9]+]]:fpr64 = CMGEv4i16 [[COPY1]], [[COPY]]2936    ; CHECK-NEXT: $d0 = COPY [[CMGEv4i16_]]2937    ; CHECK-NEXT: RET_ReallyLR implicit $d02938    %0:fpr(<4 x s16>) = COPY $d02939    %1:fpr(<4 x s16>) = COPY $d12940    %4:fpr(<4 x s16>) = G_ICMP intpred(sle), %0(<4 x s16>), %12941    %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)2942    $d0 = COPY %3(<4 x s16>)2943    RET_ReallyLR implicit $d02944 2945...2946---2947name:            test_v16i8_sle2948alignment:       42949legalized:       true2950regBankSelected: true2951tracksRegLiveness: true2952registers:2953  - { id: 0, class: fpr }2954  - { id: 1, class: fpr }2955  - { id: 2, class: _ }2956  - { id: 3, class: fpr }2957  - { id: 4, class: fpr }2958machineFunctionInfo: {}2959body:             |2960  bb.1 (%ir-block.0):2961    liveins: $q0, $q12962 2963    ; CHECK-LABEL: name: test_v16i8_sle2964    ; CHECK: liveins: $q0, $q12965    ; CHECK-NEXT: {{  $}}2966    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q02967    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q12968    ; CHECK-NEXT: [[CMGEv16i8_:%[0-9]+]]:fpr128 = CMGEv16i8 [[COPY1]], [[COPY]]2969    ; CHECK-NEXT: $q0 = COPY [[CMGEv16i8_]]2970    ; CHECK-NEXT: RET_ReallyLR implicit $q02971    %0:fpr(<16 x s8>) = COPY $q02972    %1:fpr(<16 x s8>) = COPY $q12973    %4:fpr(<16 x s8>) = G_ICMP intpred(sle), %0(<16 x s8>), %12974    %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)2975    $q0 = COPY %3(<16 x s8>)2976    RET_ReallyLR implicit $q02977 2978...2979---2980name:            test_v8i8_sle2981alignment:       42982legalized:       true2983regBankSelected: true2984tracksRegLiveness: true2985registers:2986  - { id: 0, class: fpr }2987  - { id: 1, class: fpr }2988  - { id: 2, class: _ }2989  - { id: 3, class: fpr }2990  - { id: 4, class: fpr }2991machineFunctionInfo: {}2992body:             |2993  bb.1 (%ir-block.0):2994    liveins: $d0, $d12995 2996    ; CHECK-LABEL: name: test_v8i8_sle2997    ; CHECK: liveins: $d0, $d12998    ; CHECK-NEXT: {{  $}}2999    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d03000    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d13001    ; CHECK-NEXT: [[CMGEv8i8_:%[0-9]+]]:fpr64 = CMGEv8i8 [[COPY1]], [[COPY]]3002    ; CHECK-NEXT: $d0 = COPY [[CMGEv8i8_]]3003    ; CHECK-NEXT: RET_ReallyLR implicit $d03004    %0:fpr(<8 x s8>) = COPY $d03005    %1:fpr(<8 x s8>) = COPY $d13006    %4:fpr(<8 x s8>) = G_ICMP intpred(sle), %0(<8 x s8>), %13007    %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)3008    $d0 = COPY %3(<8 x s8>)3009    RET_ReallyLR implicit $d03010 3011...3012