627 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3---4name: shl_v2i325alignment: 46legalized: true7regBankSelected: true8tracksRegLiveness: true9registers:10 - { id: 0, class: fpr }11 - { id: 1, class: fpr }12 - { id: 2, class: fpr }13machineFunctionInfo: {}14body: |15 bb.1:16 liveins: $d0, $d117 18 ; CHECK-LABEL: name: shl_v2i3219 ; CHECK: liveins: $d0, $d120 ; CHECK-NEXT: {{ $}}21 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d022 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d123 ; CHECK-NEXT: [[USHLv2i32_:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY]], [[COPY1]]24 ; CHECK-NEXT: $d0 = COPY [[USHLv2i32_]]25 ; CHECK-NEXT: RET_ReallyLR implicit $d026 %0:fpr(<2 x s32>) = COPY $d027 %1:fpr(<2 x s32>) = COPY $d128 %2:fpr(<2 x s32>) = G_SHL %0, %1(<2 x s32>)29 $d0 = COPY %2(<2 x s32>)30 RET_ReallyLR implicit $d031 32...33---34name: shl_v2i32_imm35alignment: 436legalized: true37regBankSelected: true38tracksRegLiveness: true39registers:40 - { id: 0, class: fpr }41 - { id: 1, class: fpr }42 - { id: 2, class: gpr }43 - { id: 3, class: fpr }44liveins:45 - { reg: '$d0' }46frameInfo:47 maxAlignment: 148machineFunctionInfo: {}49body: |50 bb.1:51 liveins: $d052 53 ; CHECK-LABEL: name: shl_v2i32_imm54 ; CHECK: liveins: $d055 ; CHECK-NEXT: {{ $}}56 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d057 ; CHECK-NEXT: [[SHLv2i32_shift:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY]], 2458 ; CHECK-NEXT: $d0 = COPY [[SHLv2i32_shift]]59 ; CHECK-NEXT: RET_ReallyLR implicit $d060 %0:fpr(<2 x s32>) = COPY $d061 %2:gpr(s32) = G_CONSTANT i32 2462 %1:fpr(<2 x s32>) = G_BUILD_VECTOR %2(s32), %2(s32)63 %3:fpr(<2 x s32>) = G_SHL %0, %1(<2 x s32>)64 $d0 = COPY %3(<2 x s32>)65 RET_ReallyLR implicit $d066 67...68---69name: shl_v2i32_imm_out_of_range70alignment: 471legalized: true72regBankSelected: true73tracksRegLiveness: true74registers:75 - { id: 0, class: fpr }76 - { id: 1, class: fpr }77 - { id: 2, class: gpr }78 - { id: 3, class: fpr }79liveins:80 - { reg: '$d0' }81frameInfo:82 maxAlignment: 183machineFunctionInfo: {}84body: |85 bb.1:86 liveins: $d087 88 ; CHECK-LABEL: name: shl_v2i32_imm_out_of_range89 ; CHECK: liveins: $d090 ; CHECK-NEXT: {{ $}}91 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d092 ; CHECK-NEXT: [[MOVIv2i32_:%[0-9]+]]:fpr64 = MOVIv2i32 40, 093 ; CHECK-NEXT: [[USHLv2i32_:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY]], [[MOVIv2i32_]]94 ; CHECK-NEXT: $d0 = COPY [[USHLv2i32_]]95 ; CHECK-NEXT: RET_ReallyLR implicit $d096 %0:fpr(<2 x s32>) = COPY $d097 %2:gpr(s32) = G_CONSTANT i32 4098 %1:fpr(<2 x s32>) = G_BUILD_VECTOR %2(s32), %2(s32)99 %3:fpr(<2 x s32>) = G_SHL %0, %1(<2 x s32>)100 $d0 = COPY %3(<2 x s32>)101 RET_ReallyLR implicit $d0102 103...104---105name: shl_v4i32106alignment: 4107legalized: true108regBankSelected: true109tracksRegLiveness: true110registers:111 - { id: 0, class: fpr }112 - { id: 1, class: fpr }113 - { id: 2, class: fpr }114machineFunctionInfo: {}115body: |116 bb.1:117 liveins: $q0, $q1118 119 ; CHECK-LABEL: name: shl_v4i32120 ; CHECK: liveins: $q0, $q1121 ; CHECK-NEXT: {{ $}}122 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0123 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1124 ; CHECK-NEXT: [[USHLv4i32_:%[0-9]+]]:fpr128 = USHLv4i32 [[COPY]], [[COPY1]]125 ; CHECK-NEXT: $q0 = COPY [[USHLv4i32_]]126 ; CHECK-NEXT: RET_ReallyLR implicit $q0127 %0:fpr(<4 x s32>) = COPY $q0128 %1:fpr(<4 x s32>) = COPY $q1129 %2:fpr(<4 x s32>) = G_SHL %0, %1(<4 x s32>)130 $q0 = COPY %2(<4 x s32>)131 RET_ReallyLR implicit $q0132 133...134---135name: shl_v4i32_imm136alignment: 4137legalized: true138regBankSelected: true139tracksRegLiveness: true140registers:141 - { id: 0, class: fpr }142 - { id: 1, class: fpr }143 - { id: 2, class: gpr }144 - { id: 3, class: fpr }145liveins:146 - { reg: '$q0' }147frameInfo:148 maxAlignment: 1149machineFunctionInfo: {}150body: |151 bb.1:152 liveins: $q0153 154 ; CHECK-LABEL: name: shl_v4i32_imm155 ; CHECK: liveins: $q0156 ; CHECK-NEXT: {{ $}}157 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0158 ; CHECK-NEXT: [[SHLv4i32_shift:%[0-9]+]]:fpr128 = SHLv4i32_shift [[COPY]], 24159 ; CHECK-NEXT: $q0 = COPY [[SHLv4i32_shift]]160 ; CHECK-NEXT: RET_ReallyLR implicit $q0161 %0:fpr(<4 x s32>) = COPY $q0162 %2:gpr(s32) = G_CONSTANT i32 24163 %1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %2(s32), %2(s32), %2(s32)164 %3:fpr(<4 x s32>) = G_SHL %0, %1(<4 x s32>)165 $q0 = COPY %3(<4 x s32>)166 RET_ReallyLR implicit $q0167 168...169---170name: shl_v2i64171alignment: 4172legalized: true173regBankSelected: true174tracksRegLiveness: true175registers:176 - { id: 0, class: fpr }177 - { id: 1, class: fpr }178 - { id: 2, class: fpr }179machineFunctionInfo: {}180body: |181 bb.1:182 liveins: $q0, $q1183 184 ; CHECK-LABEL: name: shl_v2i64185 ; CHECK: liveins: $q0, $q1186 ; CHECK-NEXT: {{ $}}187 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0188 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1189 ; CHECK-NEXT: [[USHLv2i64_:%[0-9]+]]:fpr128 = USHLv2i64 [[COPY]], [[COPY1]]190 ; CHECK-NEXT: $q0 = COPY [[USHLv2i64_]]191 ; CHECK-NEXT: RET_ReallyLR implicit $q0192 %0:fpr(<2 x s64>) = COPY $q0193 %1:fpr(<2 x s64>) = COPY $q1194 %2:fpr(<2 x s64>) = G_SHL %0, %1(<2 x s64>)195 $q0 = COPY %2(<2 x s64>)196 RET_ReallyLR implicit $q0197 198...199---200name: shl_v2i64_imm201alignment: 4202legalized: true203regBankSelected: true204tracksRegLiveness: true205registers:206 - { id: 0, class: fpr }207 - { id: 1, class: fpr }208 - { id: 2, class: gpr }209 - { id: 3, class: fpr }210liveins:211 - { reg: '$q0' }212frameInfo:213 maxAlignment: 1214machineFunctionInfo: {}215body: |216 bb.1:217 liveins: $q0218 219 ; CHECK-LABEL: name: shl_v2i64_imm220 ; CHECK: liveins: $q0221 ; CHECK-NEXT: {{ $}}222 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0223 ; CHECK-NEXT: [[SHLv2i64_shift:%[0-9]+]]:fpr128 = SHLv2i64_shift [[COPY]], 24224 ; CHECK-NEXT: $q0 = COPY [[SHLv2i64_shift]]225 ; CHECK-NEXT: RET_ReallyLR implicit $q0226 %0:fpr(<2 x s64>) = COPY $q0227 %2:gpr(s64) = G_CONSTANT i64 24228 %1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %2(s64)229 %3:fpr(<2 x s64>) = G_SHL %0, %1(<2 x s64>)230 $q0 = COPY %3(<2 x s64>)231 RET_ReallyLR implicit $q0232 233...234---235name: shl_v2i64_imm_out_of_range236alignment: 4237legalized: true238regBankSelected: true239tracksRegLiveness: true240registers:241 - { id: 0, class: fpr }242 - { id: 1, class: fpr }243 - { id: 2, class: gpr }244 - { id: 3, class: fpr }245liveins:246 - { reg: '$q0' }247frameInfo:248 maxAlignment: 1249machineFunctionInfo: {}250body: |251 bb.1:252 liveins: $q0253 254 ; CHECK-LABEL: name: shl_v2i64_imm_out_of_range255 ; CHECK: liveins: $q0256 ; CHECK-NEXT: {{ $}}257 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0258 ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0259 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)260 ; CHECK-NEXT: [[USHLv2i64_:%[0-9]+]]:fpr128 = USHLv2i64 [[COPY]], [[LDRQui]]261 ; CHECK-NEXT: $q0 = COPY [[USHLv2i64_]]262 ; CHECK-NEXT: RET_ReallyLR implicit $q0263 %0:fpr(<2 x s64>) = COPY $q0264 %2:gpr(s64) = G_CONSTANT i64 70265 %1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %2(s64)266 %3:fpr(<2 x s64>) = G_SHL %0, %1(<2 x s64>)267 $q0 = COPY %3(<2 x s64>)268 RET_ReallyLR implicit $q0269 270...271---272name: ashr_v2i32273alignment: 4274legalized: true275regBankSelected: true276tracksRegLiveness: true277registers:278 - { id: 0, class: fpr }279 - { id: 1, class: fpr }280 - { id: 2, class: fpr }281machineFunctionInfo: {}282body: |283 bb.1:284 liveins: $d0, $d1285 286 ; CHECK-LABEL: name: ashr_v2i32287 ; CHECK: liveins: $d0, $d1288 ; CHECK-NEXT: {{ $}}289 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0290 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1291 ; CHECK-NEXT: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[COPY1]]292 ; CHECK-NEXT: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[COPY]], [[NEGv2i32_]]293 ; CHECK-NEXT: $d0 = COPY [[SSHLv2i32_]]294 ; CHECK-NEXT: RET_ReallyLR implicit $d0295 %0:fpr(<2 x s32>) = COPY $d0296 %1:fpr(<2 x s32>) = COPY $d1297 %2:fpr(<2 x s32>) = G_ASHR %0, %1(<2 x s32>)298 $d0 = COPY %2(<2 x s32>)299 RET_ReallyLR implicit $d0300 301...302---303name: ashr_v4i32304alignment: 4305legalized: true306regBankSelected: true307tracksRegLiveness: true308registers:309 - { id: 0, class: fpr }310 - { id: 1, class: fpr }311 - { id: 2, class: fpr }312machineFunctionInfo: {}313body: |314 bb.1:315 liveins: $q0, $q1316 317 ; CHECK-LABEL: name: ashr_v4i32318 ; CHECK: liveins: $q0, $q1319 ; CHECK-NEXT: {{ $}}320 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0321 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1322 ; CHECK-NEXT: [[NEGv4i32_:%[0-9]+]]:fpr128 = NEGv4i32 [[COPY1]]323 ; CHECK-NEXT: [[SSHLv4i32_:%[0-9]+]]:fpr128 = SSHLv4i32 [[COPY]], [[NEGv4i32_]]324 ; CHECK-NEXT: $q0 = COPY [[SSHLv4i32_]]325 ; CHECK-NEXT: RET_ReallyLR implicit $q0326 %0:fpr(<4 x s32>) = COPY $q0327 %1:fpr(<4 x s32>) = COPY $q1328 %2:fpr(<4 x s32>) = G_ASHR %0, %1(<4 x s32>)329 $q0 = COPY %2(<4 x s32>)330 RET_ReallyLR implicit $q0331 332...333---334name: ashr_v2i64335alignment: 4336legalized: true337regBankSelected: true338tracksRegLiveness: true339registers:340 - { id: 0, class: fpr }341 - { id: 1, class: fpr }342 - { id: 2, class: fpr }343machineFunctionInfo: {}344body: |345 bb.1:346 liveins: $q0, $q1347 348 ; CHECK-LABEL: name: ashr_v2i64349 ; CHECK: liveins: $q0, $q1350 ; CHECK-NEXT: {{ $}}351 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0352 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1353 ; CHECK-NEXT: [[NEGv2i64_:%[0-9]+]]:fpr128 = NEGv2i64 [[COPY1]]354 ; CHECK-NEXT: [[SSHLv2i64_:%[0-9]+]]:fpr128 = SSHLv2i64 [[COPY]], [[NEGv2i64_]]355 ; CHECK-NEXT: $q0 = COPY [[SSHLv2i64_]]356 ; CHECK-NEXT: RET_ReallyLR implicit $q0357 %0:fpr(<2 x s64>) = COPY $q0358 %1:fpr(<2 x s64>) = COPY $q1359 %2:fpr(<2 x s64>) = G_ASHR %0, %1(<2 x s64>)360 $q0 = COPY %2(<2 x s64>)361 RET_ReallyLR implicit $q0362 363...364---365name: shl_v4i16366legalized: true367regBankSelected: true368tracksRegLiveness: true369body: |370 bb.1:371 liveins: $d0, $d1372 ; CHECK-LABEL: name: shl_v4i16373 ; CHECK: liveins: $d0, $d1374 ; CHECK-NEXT: {{ $}}375 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0376 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1377 ; CHECK-NEXT: [[USHLv4i16_:%[0-9]+]]:fpr64 = USHLv4i16 [[COPY]], [[COPY1]]378 ; CHECK-NEXT: $d0 = COPY [[USHLv4i16_]]379 ; CHECK-NEXT: RET_ReallyLR implicit $d0380 %0:fpr(<4 x s16>) = COPY $d0381 %1:fpr(<4 x s16>) = COPY $d1382 %2:fpr(<4 x s16>) = G_SHL %0, %1(<4 x s16>)383 $d0 = COPY %2(<4 x s16>)384 RET_ReallyLR implicit $d0385...386---387name: lshr_v4i16388legalized: true389regBankSelected: true390tracksRegLiveness: true391body: |392 bb.1:393 liveins: $d0, $d1394 ; CHECK-LABEL: name: lshr_v4i16395 ; CHECK: liveins: $d0, $d1396 ; CHECK-NEXT: {{ $}}397 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0398 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1399 ; CHECK-NEXT: [[NEGv4i16_:%[0-9]+]]:fpr64 = NEGv4i16 [[COPY1]]400 ; CHECK-NEXT: [[USHLv4i16_:%[0-9]+]]:fpr64 = USHLv4i16 [[COPY]], [[NEGv4i16_]]401 ; CHECK-NEXT: $d0 = COPY [[USHLv4i16_]]402 ; CHECK-NEXT: RET_ReallyLR implicit $d0403 %0:fpr(<4 x s16>) = COPY $d0404 %1:fpr(<4 x s16>) = COPY $d1405 %2:fpr(<4 x s16>) = G_LSHR %0, %1(<4 x s16>)406 $d0 = COPY %2(<4 x s16>)407 RET_ReallyLR implicit $d0408...409---410name: lshr_v4i32411alignment: 4412legalized: true413regBankSelected: true414tracksRegLiveness: true415registers:416 - { id: 0, class: fpr }417 - { id: 1, class: fpr }418 - { id: 2, class: fpr }419machineFunctionInfo: {}420body: |421 bb.1:422 liveins: $q0, $q1423 424 ; CHECK-LABEL: name: lshr_v4i32425 ; CHECK: liveins: $q0, $q1426 ; CHECK-NEXT: {{ $}}427 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0428 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1429 ; CHECK-NEXT: [[NEGv4i32_:%[0-9]+]]:fpr128 = NEGv4i32 [[COPY1]]430 ; CHECK-NEXT: [[USHLv4i32_:%[0-9]+]]:fpr128 = USHLv4i32 [[COPY]], [[NEGv4i32_]]431 ; CHECK-NEXT: $q0 = COPY [[USHLv4i32_]]432 ; CHECK-NEXT: RET_ReallyLR implicit $q0433 %0:fpr(<4 x s32>) = COPY $q0434 %1:fpr(<4 x s32>) = COPY $q1435 %2:fpr(<4 x s32>) = G_LSHR %0, %1(<4 x s32>)436 $q0 = COPY %2(<4 x s32>)437 RET_ReallyLR implicit $q0438 439...440---441name: lshr_v8i16442legalized: true443regBankSelected: true444tracksRegLiveness: true445body: |446 bb.1:447 liveins: $q0, $q1448 ; CHECK-LABEL: name: lshr_v8i16449 ; CHECK: liveins: $q0, $q1450 ; CHECK-NEXT: {{ $}}451 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0452 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1453 ; CHECK-NEXT: [[NEGv8i16_:%[0-9]+]]:fpr128 = NEGv8i16 [[COPY1]]454 ; CHECK-NEXT: [[USHLv8i16_:%[0-9]+]]:fpr128 = USHLv8i16 [[COPY]], [[NEGv8i16_]]455 ; CHECK-NEXT: $q0 = COPY [[USHLv8i16_]]456 ; CHECK-NEXT: RET_ReallyLR implicit $q0457 %0:fpr(<8 x s16>) = COPY $q0458 %1:fpr(<8 x s16>) = COPY $q1459 %2:fpr(<8 x s16>) = G_LSHR %0, %1(<8 x s16>)460 $q0 = COPY %2(<8 x s16>)461 RET_ReallyLR implicit $q0462...463---464name: ashr_v4i16465legalized: true466regBankSelected: true467tracksRegLiveness: true468body: |469 bb.1:470 liveins: $d0, $d1471 ; CHECK-LABEL: name: ashr_v4i16472 ; CHECK: liveins: $d0, $d1473 ; CHECK-NEXT: {{ $}}474 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0475 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1476 ; CHECK-NEXT: [[NEGv4i16_:%[0-9]+]]:fpr64 = NEGv4i16 [[COPY1]]477 ; CHECK-NEXT: [[SSHLv4i16_:%[0-9]+]]:fpr64 = SSHLv4i16 [[COPY]], [[NEGv4i16_]]478 ; CHECK-NEXT: $d0 = COPY [[SSHLv4i16_]]479 ; CHECK-NEXT: RET_ReallyLR implicit $d0480 %0:fpr(<4 x s16>) = COPY $d0481 %1:fpr(<4 x s16>) = COPY $d1482 %2:fpr(<4 x s16>) = G_ASHR %0, %1(<4 x s16>)483 $d0 = COPY %2(<4 x s16>)484 RET_ReallyLR implicit $d0485...486---487name: vashr_v4i16_imm488legalized: true489regBankSelected: true490tracksRegLiveness: true491body: |492 bb.1:493 liveins: $d0, $d1494 ; CHECK-LABEL: name: vashr_v4i16_imm495 ; CHECK: liveins: $d0, $d1496 ; CHECK-NEXT: {{ $}}497 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0498 ; CHECK-NEXT: [[SSHRv4i16_shift:%[0-9]+]]:fpr64 = SSHRv4i16_shift [[COPY]], 5499 ; CHECK-NEXT: $d0 = COPY [[SSHRv4i16_shift]]500 ; CHECK-NEXT: RET_ReallyLR implicit $d0501 %0:fpr(<4 x s16>) = COPY $d0502 %2:fpr(<4 x s16>) = G_VASHR %0, 5503 $d0 = COPY %2(<4 x s16>)504 RET_ReallyLR implicit $d0505...506---507name: vlshr_v4i16_imm508legalized: true509regBankSelected: true510tracksRegLiveness: true511body: |512 bb.1:513 liveins: $d0, $d1514 ; CHECK-LABEL: name: vlshr_v4i16_imm515 ; CHECK: liveins: $d0, $d1516 ; CHECK-NEXT: {{ $}}517 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0518 ; CHECK-NEXT: [[USHRv4i16_shift:%[0-9]+]]:fpr64 = USHRv4i16_shift [[COPY]], 5519 ; CHECK-NEXT: $d0 = COPY [[USHRv4i16_shift]]520 ; CHECK-NEXT: RET_ReallyLR implicit $d0521 %0:fpr(<4 x s16>) = COPY $d0522 %2:fpr(<4 x s16>) = G_VLSHR %0, 5523 $d0 = COPY %2(<4 x s16>)524 RET_ReallyLR implicit $d0525...526---527name: shl_v8i16528legalized: true529regBankSelected: true530tracksRegLiveness: true531body: |532 bb.1:533 liveins: $q0, $q1534 ; CHECK-LABEL: name: shl_v8i16535 ; CHECK: liveins: $q0, $q1536 ; CHECK-NEXT: {{ $}}537 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0538 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1539 ; CHECK-NEXT: [[USHLv8i16_:%[0-9]+]]:fpr128 = USHLv8i16 [[COPY]], [[COPY1]]540 ; CHECK-NEXT: $q0 = COPY [[USHLv8i16_]]541 ; CHECK-NEXT: RET_ReallyLR implicit $q0542 %0:fpr(<8 x s16>) = COPY $q0543 %1:fpr(<8 x s16>) = COPY $q1544 %2:fpr(<8 x s16>) = G_SHL %0, %1(<8 x s16>)545 $q0 = COPY %2(<8 x s16>)546 RET_ReallyLR implicit $q0547...548---549name: shl_v16i8550legalized: true551regBankSelected: true552tracksRegLiveness: true553body: |554 bb.1:555 liveins: $q0, $q1556 ; CHECK-LABEL: name: shl_v16i8557 ; CHECK: liveins: $q0, $q1558 ; CHECK-NEXT: {{ $}}559 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0560 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1561 ; CHECK-NEXT: [[USHLv16i8_:%[0-9]+]]:fpr128 = USHLv16i8 [[COPY]], [[COPY1]]562 ; CHECK-NEXT: $q0 = COPY [[USHLv16i8_]]563 ; CHECK-NEXT: RET_ReallyLR implicit $q0564 %0:fpr(<16 x s8>) = COPY $q0565 %1:fpr(<16 x s8>) = COPY $q1566 %2:fpr(<16 x s8>) = G_SHL %0, %1(<16 x s8>)567 $q0 = COPY %2(<16 x s8>)568 RET_ReallyLR implicit $q0569...570---571name: lshr_v16i8572legalized: true573regBankSelected: true574tracksRegLiveness: true575body: |576 bb.1:577 liveins: $q0, $q1578 ; CHECK-LABEL: name: lshr_v16i8579 ; CHECK: liveins: $q0, $q1580 ; CHECK-NEXT: {{ $}}581 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0582 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1583 ; CHECK-NEXT: [[NEGv16i8_:%[0-9]+]]:fpr128 = NEGv16i8 [[COPY1]]584 ; CHECK-NEXT: [[USHLv16i8_:%[0-9]+]]:fpr128 = USHLv16i8 [[COPY]], [[NEGv16i8_]]585 ; CHECK-NEXT: $q0 = COPY [[USHLv16i8_]]586 ; CHECK-NEXT: RET_ReallyLR implicit $q0587 %0:fpr(<16 x s8>) = COPY $q0588 %1:fpr(<16 x s8>) = COPY $q1589 %2:fpr(<16 x s8>) = G_LSHR %0, %1(<16 x s8>)590 $q0 = COPY %2(<16 x s8>)591 RET_ReallyLR implicit $q0592...593---594name: shl_v2i32_imm_dup595alignment: 4596legalized: true597regBankSelected: true598tracksRegLiveness: true599registers:600 - { id: 0, class: fpr }601 - { id: 1, class: fpr }602 - { id: 2, class: gpr }603 - { id: 3, class: fpr }604liveins:605 - { reg: '$d0' }606frameInfo:607 maxAlignment: 1608machineFunctionInfo: {}609body: |610 bb.1:611 liveins: $d0612 613 614 ; CHECK-LABEL: name: shl_v2i32_imm_dup615 ; CHECK: liveins: $d0616 ; CHECK-NEXT: {{ $}}617 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0618 ; CHECK-NEXT: [[SHLv2i32_shift:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY]], 24619 ; CHECK-NEXT: $d0 = COPY [[SHLv2i32_shift]]620 ; CHECK-NEXT: RET_ReallyLR implicit $d0621 %0:fpr(<2 x s32>) = COPY $d0622 %2:gpr(s32) = G_CONSTANT i32 24623 %1:fpr(<2 x s32>) = G_DUP %2(s32)624 %3:fpr(<2 x s32>) = G_SHL %0, %1(<2 x s32>)625 $d0 = COPY %3(<2 x s32>)626 RET_ReallyLR implicit $d0627