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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple aarch64-apple-ios -run-pass instruction-select %s \3# RUN: -disable-gisel-legality-check -verify-machineinstrs -simplify-mir \4# RUN: -o - | FileCheck %s5---6name: test_rule14_id188_at_idx10677alignment: 48legalized: true9regBankSelected: true10tracksRegLiveness: true11registers:12 - { id: 0, class: fpr }13 - { id: 1, class: fpr }14liveins:15 - { reg: '$d0', virtual-reg: '%1' }16body: |17 bb.0.entry:18 liveins: $d019 20 ; CHECK-LABEL: name: test_rule14_id188_at_idx106721 ; CHECK: liveins: $d022 ; CHECK-NEXT: {{ $}}23 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d024 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]25 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (s128))26 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[LDRQui]]27 %1:fpr(p0) = COPY $d028 %0:fpr(s128) = G_LOAD %1(p0) :: (load (s128))29 $noreg = PATCHABLE_RET %0(s128)30 31...32---33name: test_rule21_id2237_at_idx144934alignment: 435legalized: true36regBankSelected: true37tracksRegLiveness: true38registers:39 - { id: 0, class: fpr }40 - { id: 1, class: fpr }41liveins:42 - { reg: '$d0', virtual-reg: '%0' }43 - { reg: '$d1', virtual-reg: '%1' }44body: |45 bb.0.entry:46 liveins: $d0, $d147 48 ; CHECK-LABEL: name: test_rule21_id2237_at_idx144949 ; CHECK: liveins: $d0, $d150 ; CHECK-NEXT: {{ $}}51 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d152 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d053 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]54 ; CHECK-NEXT: STRDui [[COPY1]], [[COPY2]], 0 :: (store (<8 x s8>))55 ; CHECK-NEXT: $noreg = PATCHABLE_RET56 %1:fpr(p0) = COPY $d157 %0:fpr(<8 x s8>) = COPY $d058 G_STORE %0(<8 x s8>), %1(p0) :: (store (<8 x s8>))59 $noreg = PATCHABLE_RET60 61...62---63name: test_rule22_id2238_at_idx150564alignment: 465legalized: true66regBankSelected: true67tracksRegLiveness: true68registers:69 - { id: 0, class: fpr }70 - { id: 1, class: fpr }71liveins:72 - { reg: '$d0', virtual-reg: '%0' }73 - { reg: '$d1', virtual-reg: '%1' }74body: |75 bb.0.entry:76 liveins: $d0, $d177 78 ; CHECK-LABEL: name: test_rule22_id2238_at_idx150579 ; CHECK: liveins: $d0, $d180 ; CHECK-NEXT: {{ $}}81 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d182 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d083 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]84 ; CHECK-NEXT: STRDui [[COPY1]], [[COPY2]], 0 :: (store (<4 x s16>))85 ; CHECK-NEXT: $noreg = PATCHABLE_RET86 %1:fpr(p0) = COPY $d187 %0:fpr(<4 x s16>) = COPY $d088 G_STORE %0(<4 x s16>), %1(p0) :: (store (<4 x s16>))89 $noreg = PATCHABLE_RET90 91...92---93name: test_rule27_id2243_at_idx178194alignment: 495legalized: true96regBankSelected: true97tracksRegLiveness: true98registers:99 - { id: 0, class: fpr }100 - { id: 1, class: fpr }101liveins:102 - { reg: '$q0', virtual-reg: '%0' }103 - { reg: '$d0', virtual-reg: '%1' }104body: |105 bb.0.entry:106 liveins: $q0, $d0107 108 ; CHECK-LABEL: name: test_rule27_id2243_at_idx1781109 ; CHECK: liveins: $q0, $d0110 ; CHECK-NEXT: {{ $}}111 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0112 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0113 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]114 ; CHECK-NEXT: STRQui [[COPY1]], [[COPY2]], 0 :: (store (<4 x s32>))115 ; CHECK-NEXT: $noreg = PATCHABLE_RET116 %1:fpr(p0) = COPY $d0117 %0:fpr(<4 x s32>) = COPY $q0118 G_STORE %0(<4 x s32>), %1(p0) :: (store (<4 x s32>))119 $noreg = PATCHABLE_RET120 121...122---123name: test_rule28_id2244_at_idx1837124alignment: 4125legalized: true126regBankSelected: true127tracksRegLiveness: true128registers:129 - { id: 0, class: fpr }130 - { id: 1, class: fpr }131liveins:132 - { reg: '$q0', virtual-reg: '%0' }133 - { reg: '$d0', virtual-reg: '%1' }134body: |135 bb.0.entry:136 liveins: $q0, $d0137 138 ; CHECK-LABEL: name: test_rule28_id2244_at_idx1837139 ; CHECK: liveins: $q0, $d0140 ; CHECK-NEXT: {{ $}}141 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0142 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0143 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]144 ; CHECK-NEXT: STRQui [[COPY1]], [[COPY2]], 0 :: (store (<2 x s64>))145 ; CHECK-NEXT: $noreg = PATCHABLE_RET146 %1:fpr(p0) = COPY $d0147 %0:fpr(<2 x s64>) = COPY $q0148 G_STORE %0(<2 x s64>), %1(p0) :: (store (<2 x s64>))149 $noreg = PATCHABLE_RET150 151...152---153name: test_rule29_id2245_at_idx1893154alignment: 4155legalized: true156regBankSelected: true157tracksRegLiveness: true158registers:159 - { id: 0, class: fpr }160 - { id: 1, class: fpr }161liveins:162 - { reg: '$q0', virtual-reg: '%0' }163 - { reg: '$d0', virtual-reg: '%1' }164body: |165 bb.0.entry:166 liveins: $q0, $d0167 168 ; CHECK-LABEL: name: test_rule29_id2245_at_idx1893169 ; CHECK: liveins: $q0, $d0170 ; CHECK-NEXT: {{ $}}171 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0172 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0173 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]174 ; CHECK-NEXT: STRQui [[COPY1]], [[COPY2]], 0 :: (store (<16 x s8>))175 ; CHECK-NEXT: $noreg = PATCHABLE_RET176 %1:fpr(p0) = COPY $d0177 %0:fpr(<16 x s8>) = COPY $q0178 G_STORE %0(<16 x s8>), %1(p0) :: (store (<16 x s8>))179 $noreg = PATCHABLE_RET180 181...182---183name: test_rule30_id2246_at_idx1949184alignment: 4185legalized: true186regBankSelected: true187tracksRegLiveness: true188registers:189 - { id: 0, class: fpr }190 - { id: 1, class: fpr }191liveins:192 - { reg: '$q0', virtual-reg: '%0' }193 - { reg: '$d0', virtual-reg: '%1' }194body: |195 bb.0.entry:196 liveins: $q0, $d0197 198 ; CHECK-LABEL: name: test_rule30_id2246_at_idx1949199 ; CHECK: liveins: $q0, $d0200 ; CHECK-NEXT: {{ $}}201 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0202 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0203 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]204 ; CHECK-NEXT: STRQui [[COPY1]], [[COPY2]], 0 :: (store (<8 x s16>))205 ; CHECK-NEXT: $noreg = PATCHABLE_RET206 %1:fpr(p0) = COPY $d0207 %0:fpr(<8 x s16>) = COPY $q0208 G_STORE %0(<8 x s16>), %1(p0) :: (store (<8 x s16>))209 $noreg = PATCHABLE_RET210 211...212---213name: test_rule34_id2250_at_idx2173214alignment: 4215legalized: true216regBankSelected: true217tracksRegLiveness: true218registers:219 - { id: 0, class: fpr }220 - { id: 1, class: fpr }221liveins:222 - { reg: '$q0', virtual-reg: '%0' }223 - { reg: '$d0', virtual-reg: '%1' }224body: |225 bb.0.entry:226 liveins: $q0, $d0227 228 ; CHECK-LABEL: name: test_rule34_id2250_at_idx2173229 ; CHECK: liveins: $q0, $d0230 ; CHECK-NEXT: {{ $}}231 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0232 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0233 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]234 ; CHECK-NEXT: STRQui [[COPY1]], [[COPY2]], 0 :: (store (s128))235 ; CHECK-NEXT: $noreg = PATCHABLE_RET236 %1:fpr(p0) = COPY $d0237 %0:fpr(s128) = COPY $q0238 G_STORE %0(s128), %1(p0) :: (store (s128))239 $noreg = PATCHABLE_RET240 241...242# The rules that generated this test has changed. The generator should be rerun243---244name: test_rule92_id2150_at_idx7770245alignment: 4246legalized: true247regBankSelected: true248tracksRegLiveness: true249registers:250 - { id: 0, class: gpr }251 - { id: 1, class: gpr }252 - { id: 2, class: gpr }253liveins:254 - { reg: '$x0', virtual-reg: '%2' }255body: |256 bb.0.entry:257 liveins: $x0258 259 ; CHECK-LABEL: name: test_rule92_id2150_at_idx7770260 ; CHECK: liveins: $x0261 ; CHECK-NEXT: {{ $}}262 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0263 ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))264 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[LDRBBui]]265 %2:gpr(p0) = COPY $x0266 %0:gpr(s32) = G_LOAD %2(p0) :: (load (s8))267 $noreg = PATCHABLE_RET %0(s32)268 269...270# The rules that generated this test has changed. The generator should be rerun271---272name: test_rule96_id2146_at_idx8070273alignment: 4274legalized: true275regBankSelected: true276tracksRegLiveness: true277registers:278 - { id: 0, class: fpr }279 - { id: 1, class: gpr }280 - { id: 2, class: gpr }281liveins:282 - { reg: '$x0', virtual-reg: '%2' }283body: |284 bb.0.entry:285 liveins: $x0286 287 ; CHECK-LABEL: name: test_rule96_id2146_at_idx8070288 ; CHECK: liveins: $x0289 ; CHECK-NEXT: {{ $}}290 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0291 ; CHECK-NEXT: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load (s8))292 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[LDRBui]]293 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 0, 7294 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[UBFMWri]]295 %2:gpr(p0) = COPY $x0296 %0:fpr(s8) = G_LOAD %2(p0) :: (load (s8))297 %1:gpr(s32) = G_ZEXT %0(s8)298 $noreg = PATCHABLE_RET %1(s32)299 300...301---302name: test_rule129_id2130_at_idx10828303alignment: 4304legalized: true305regBankSelected: true306tracksRegLiveness: true307registers:308 - { id: 0, class: fpr }309 - { id: 1, class: fpr }310liveins:311 - { reg: '$d0', virtual-reg: '%1' }312body: |313 bb.0.entry:314 liveins: $d0315 316 ; CHECK-LABEL: name: test_rule129_id2130_at_idx10828317 ; CHECK: liveins: $d0318 ; CHECK-NEXT: {{ $}}319 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0320 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]321 ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load (<8 x s8>))322 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[LDRDui]]323 %1:fpr(p0) = COPY $d0324 %0:fpr(<8 x s8>) = G_LOAD %1(p0) :: (load (<8 x s8>))325 $noreg = PATCHABLE_RET %0(<8 x s8>)326 327...328---329name: test_rule130_id2131_at_idx10884330alignment: 4331legalized: true332regBankSelected: true333tracksRegLiveness: true334registers:335 - { id: 0, class: fpr }336 - { id: 1, class: fpr }337liveins:338 - { reg: '$d0', virtual-reg: '%1' }339body: |340 bb.0.entry:341 liveins: $d0342 343 ; CHECK-LABEL: name: test_rule130_id2131_at_idx10884344 ; CHECK: liveins: $d0345 ; CHECK-NEXT: {{ $}}346 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0347 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]348 ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load (<4 x s16>))349 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[LDRDui]]350 %1:fpr(p0) = COPY $d0351 %0:fpr(<4 x s16>) = G_LOAD %1(p0) :: (load (<4 x s16>))352 $noreg = PATCHABLE_RET %0(<4 x s16>)353 354...355---356name: test_rule135_id2136_at_idx11160357alignment: 4358legalized: true359regBankSelected: true360tracksRegLiveness: true361registers:362 - { id: 0, class: fpr }363 - { id: 1, class: fpr }364liveins:365 - { reg: '$d0', virtual-reg: '%1' }366body: |367 bb.0.entry:368 liveins: $d0369 370 ; CHECK-LABEL: name: test_rule135_id2136_at_idx11160371 ; CHECK: liveins: $d0372 ; CHECK-NEXT: {{ $}}373 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0374 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]375 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (<4 x s32>))376 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[LDRQui]]377 %1:fpr(p0) = COPY $d0378 %0:fpr(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>))379 $noreg = PATCHABLE_RET %0(<4 x s32>)380 381...382---383name: test_rule136_id2137_at_idx11216384alignment: 4385legalized: true386regBankSelected: true387tracksRegLiveness: true388registers:389 - { id: 0, class: fpr }390 - { id: 1, class: fpr }391liveins:392 - { reg: '$d0', virtual-reg: '%1' }393body: |394 bb.0.entry:395 liveins: $d0396 397 ; CHECK-LABEL: name: test_rule136_id2137_at_idx11216398 ; CHECK: liveins: $d0399 ; CHECK-NEXT: {{ $}}400 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0401 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]402 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (<2 x s64>))403 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[LDRQui]]404 %1:fpr(p0) = COPY $d0405 %0:fpr(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>))406 $noreg = PATCHABLE_RET %0(<2 x s64>)407 408...409---410name: test_rule137_id2138_at_idx11272411alignment: 4412legalized: true413regBankSelected: true414tracksRegLiveness: true415registers:416 - { id: 0, class: fpr }417 - { id: 1, class: fpr }418liveins:419 - { reg: '$d0', virtual-reg: '%1' }420body: |421 bb.0.entry:422 liveins: $d0423 424 ; CHECK-LABEL: name: test_rule137_id2138_at_idx11272425 ; CHECK: liveins: $d0426 ; CHECK-NEXT: {{ $}}427 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0428 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]429 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (<16 x s8>))430 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[LDRQui]]431 %1:fpr(p0) = COPY $d0432 %0:fpr(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>))433 $noreg = PATCHABLE_RET %0(<16 x s8>)434 435...436---437name: test_rule138_id2139_at_idx11328438alignment: 4439legalized: true440regBankSelected: true441tracksRegLiveness: true442registers:443 - { id: 0, class: fpr }444 - { id: 1, class: fpr }445liveins:446 - { reg: '$d0', virtual-reg: '%1' }447body: |448 bb.0.entry:449 liveins: $d0450 451 ; CHECK-LABEL: name: test_rule138_id2139_at_idx11328452 ; CHECK: liveins: $d0453 ; CHECK-NEXT: {{ $}}454 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0455 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]456 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (<8 x s16>))457 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[LDRQui]]458 %1:fpr(p0) = COPY $d0459 %0:fpr(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>))460 $noreg = PATCHABLE_RET %0(<8 x s16>)461 462...463---464name: test_rule339_id2369_at_idx26608465alignment: 4466legalized: true467regBankSelected: true468tracksRegLiveness: true469registers:470 - { id: 0, class: fpr }471 - { id: 1, class: fpr }472 - { id: 2, class: fpr }473 - { id: 3, class: fpr }474 - { id: 4, class: fpr }475 - { id: 5, class: fpr }476liveins:477 - { reg: '$s0', virtual-reg: '%3' }478 - { reg: '$s1', virtual-reg: '%4' }479 - { reg: '$s2', virtual-reg: '%5' }480body: |481 bb.0.entry:482 liveins: $s0, $s1, $s2483 484 ; CHECK-LABEL: name: test_rule339_id2369_at_idx26608485 ; CHECK: liveins: $s0, $s1, $s2486 ; CHECK-NEXT: {{ $}}487 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s2488 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1489 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0490 ; CHECK-NEXT: [[FNMADDSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMADDSrrr [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr491 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMADDSrrr]]492 %5:fpr(s32) = COPY $s2493 %4:fpr(s32) = COPY $s1494 %3:fpr(s32) = COPY $s0495 %1:fpr(s32) = G_FNEG %5496 %0:fpr(s32) = G_FNEG %4497 %2:fpr(s32) = G_FMA %0, %3, %1498 $noreg = PATCHABLE_RET %2(s32)499 500...501---502name: test_rule340_id2370_at_idx26714503alignment: 4504legalized: true505regBankSelected: true506tracksRegLiveness: true507registers:508 - { id: 0, class: fpr }509 - { id: 1, class: fpr }510 - { id: 2, class: fpr }511 - { id: 3, class: fpr }512 - { id: 4, class: fpr }513 - { id: 5, class: fpr }514liveins:515 - { reg: '$d0', virtual-reg: '%3' }516 - { reg: '$d1', virtual-reg: '%4' }517 - { reg: '$d2', virtual-reg: '%5' }518body: |519 bb.0.entry:520 liveins: $d0, $d1, $d2521 522 ; CHECK-LABEL: name: test_rule340_id2370_at_idx26714523 ; CHECK: liveins: $d0, $d1, $d2524 ; CHECK-NEXT: {{ $}}525 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d2526 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1527 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0528 ; CHECK-NEXT: [[FNMADDDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMADDDrrr [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr529 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMADDDrrr]]530 %5:fpr(s64) = COPY $d2531 %4:fpr(s64) = COPY $d1532 %3:fpr(s64) = COPY $d0533 %1:fpr(s64) = G_FNEG %5534 %0:fpr(s64) = G_FNEG %4535 %2:fpr(s64) = G_FMA %0, %3, %1536 $noreg = PATCHABLE_RET %2(s64)537 538...539---540name: test_rule341_id2371_at_idx26820541alignment: 4542legalized: true543regBankSelected: true544tracksRegLiveness: true545registers:546 - { id: 0, class: fpr }547 - { id: 1, class: fpr }548 - { id: 2, class: fpr }549 - { id: 3, class: fpr }550 - { id: 4, class: fpr }551 - { id: 5, class: fpr }552liveins:553 - { reg: '$s0', virtual-reg: '%3' }554 - { reg: '$s1', virtual-reg: '%4' }555 - { reg: '$s2', virtual-reg: '%5' }556body: |557 bb.0.entry:558 liveins: $s0, $s1, $s2559 560 ; CHECK-LABEL: name: test_rule341_id2371_at_idx26820561 ; CHECK: liveins: $s0, $s1, $s2562 ; CHECK-NEXT: {{ $}}563 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s2564 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1565 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0566 ; CHECK-NEXT: [[FNMADDSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMADDSrrr [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr567 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMADDSrrr]]568 %5:fpr(s32) = COPY $s2569 %4:fpr(s32) = COPY $s1570 %3:fpr(s32) = COPY $s0571 %1:fpr(s32) = G_FNEG %5572 %0:fpr(s32) = G_FNEG %4573 %2:fpr(s32) = G_FMA %3, %0, %1574 $noreg = PATCHABLE_RET %2(s32)575 576...577---578name: test_rule342_id2372_at_idx26926579alignment: 4580legalized: true581regBankSelected: true582tracksRegLiveness: true583registers:584 - { id: 0, class: fpr }585 - { id: 1, class: fpr }586 - { id: 2, class: fpr }587 - { id: 3, class: fpr }588 - { id: 4, class: fpr }589 - { id: 5, class: fpr }590liveins:591 - { reg: '$d0', virtual-reg: '%3' }592 - { reg: '$d1', virtual-reg: '%4' }593 - { reg: '$d2', virtual-reg: '%5' }594body: |595 bb.0.entry:596 liveins: $d0, $d1, $d2597 598 ; CHECK-LABEL: name: test_rule342_id2372_at_idx26926599 ; CHECK: liveins: $d0, $d1, $d2600 ; CHECK-NEXT: {{ $}}601 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d2602 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1603 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0604 ; CHECK-NEXT: [[FNMADDDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMADDDrrr [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr605 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMADDDrrr]]606 %5:fpr(s64) = COPY $d2607 %4:fpr(s64) = COPY $d1608 %3:fpr(s64) = COPY $d0609 %1:fpr(s64) = G_FNEG %5610 %0:fpr(s64) = G_FNEG %4611 %2:fpr(s64) = G_FMA %3, %0, %1612 $noreg = PATCHABLE_RET %2(s64)613 614...615---616name: test_rule343_id1266_at_idx27032617alignment: 4618legalized: true619regBankSelected: true620tracksRegLiveness: true621registers:622 - { id: 0, class: fpr }623 - { id: 1, class: fpr }624 - { id: 2, class: fpr }625 - { id: 3, class: fpr }626 - { id: 4, class: fpr }627liveins:628 - { reg: '$d0', virtual-reg: '%3' }629 - { reg: '$d1', virtual-reg: '%4' }630body: |631 bb.0.entry:632 liveins: $d0, $d1633 634 ; CHECK-LABEL: name: test_rule343_id1266_at_idx27032635 ; CHECK: liveins: $d0, $d1636 ; CHECK-NEXT: {{ $}}637 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d1638 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0639 ; CHECK-NEXT: [[SADDLv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDLv8i8_v8i16 [[COPY1]], [[COPY]]640 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SADDLv8i8_v8i16_]]641 %4:fpr(<8 x s8>) = COPY $d1642 %3:fpr(<8 x s8>) = COPY $d0643 %1:fpr(<8 x s16>) = G_SEXT %4(<8 x s8>)644 %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)645 %2:fpr(<8 x s16>) = G_ADD %0, %1646 $noreg = PATCHABLE_RET %2(<8 x s16>)647 648...649---650name: test_rule344_id1268_at_idx27128651alignment: 4652legalized: true653regBankSelected: true654tracksRegLiveness: true655registers:656 - { id: 0, class: fpr }657 - { id: 1, class: fpr }658 - { id: 2, class: fpr }659 - { id: 3, class: fpr }660 - { id: 4, class: fpr }661liveins:662 - { reg: '$d0', virtual-reg: '%3' }663 - { reg: '$d1', virtual-reg: '%4' }664body: |665 bb.0.entry:666 liveins: $d0, $d1667 668 ; CHECK-LABEL: name: test_rule344_id1268_at_idx27128669 ; CHECK: liveins: $d0, $d1670 ; CHECK-NEXT: {{ $}}671 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d1672 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0673 ; CHECK-NEXT: [[SADDLv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDLv4i16_v4i32 [[COPY1]], [[COPY]]674 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SADDLv4i16_v4i32_]]675 %4:fpr(<4 x s16>) = COPY $d1676 %3:fpr(<4 x s16>) = COPY $d0677 %1:fpr(<4 x s32>) = G_SEXT %4(<4 x s16>)678 %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)679 %2:fpr(<4 x s32>) = G_ADD %0, %1680 $noreg = PATCHABLE_RET %2(<4 x s32>)681 682...683---684name: test_rule345_id1270_at_idx27224685alignment: 4686legalized: true687regBankSelected: true688tracksRegLiveness: true689registers:690 - { id: 0, class: fpr }691 - { id: 1, class: fpr }692 - { id: 2, class: fpr }693 - { id: 3, class: fpr }694 - { id: 4, class: fpr }695liveins:696 - { reg: '$d0', virtual-reg: '%3' }697 - { reg: '$d1', virtual-reg: '%4' }698body: |699 bb.0.entry:700 liveins: $d0, $d1701 702 ; CHECK-LABEL: name: test_rule345_id1270_at_idx27224703 ; CHECK: liveins: $d0, $d1704 ; CHECK-NEXT: {{ $}}705 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d1706 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0707 ; CHECK-NEXT: [[SADDLv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDLv2i32_v2i64 [[COPY1]], [[COPY]]708 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SADDLv2i32_v2i64_]]709 %4:fpr(<2 x s32>) = COPY $d1710 %3:fpr(<2 x s32>) = COPY $d0711 %1:fpr(<2 x s64>) = G_SEXT %4(<2 x s32>)712 %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)713 %2:fpr(<2 x s64>) = G_ADD %0, %1714 $noreg = PATCHABLE_RET %2(<2 x s64>)715 716...717---718name: test_rule346_id1326_at_idx27320719alignment: 4720legalized: true721regBankSelected: true722tracksRegLiveness: true723registers:724 - { id: 0, class: fpr }725 - { id: 1, class: fpr }726 - { id: 2, class: fpr }727 - { id: 3, class: fpr }728 - { id: 4, class: fpr }729liveins:730 - { reg: '$d0', virtual-reg: '%3' }731 - { reg: '$d1', virtual-reg: '%4' }732body: |733 bb.0.entry:734 liveins: $d0, $d1735 736 ; CHECK-LABEL: name: test_rule346_id1326_at_idx27320737 ; CHECK: liveins: $d0, $d1738 ; CHECK-NEXT: {{ $}}739 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d1740 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0741 ; CHECK-NEXT: [[UADDLv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDLv8i8_v8i16 [[COPY1]], [[COPY]]742 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[UADDLv8i8_v8i16_]]743 %4:fpr(<8 x s8>) = COPY $d1744 %3:fpr(<8 x s8>) = COPY $d0745 %1:fpr(<8 x s16>) = G_ZEXT %4(<8 x s8>)746 %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)747 %2:fpr(<8 x s16>) = G_ADD %0, %1748 $noreg = PATCHABLE_RET %2(<8 x s16>)749 750...751---752name: test_rule347_id1328_at_idx27416753alignment: 4754legalized: true755regBankSelected: true756tracksRegLiveness: true757registers:758 - { id: 0, class: fpr }759 - { id: 1, class: fpr }760 - { id: 2, class: fpr }761 - { id: 3, class: fpr }762 - { id: 4, class: fpr }763liveins:764 - { reg: '$d0', virtual-reg: '%3' }765 - { reg: '$d1', virtual-reg: '%4' }766body: |767 bb.0.entry:768 liveins: $d0, $d1769 770 ; CHECK-LABEL: name: test_rule347_id1328_at_idx27416771 ; CHECK: liveins: $d0, $d1772 ; CHECK-NEXT: {{ $}}773 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d1774 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0775 ; CHECK-NEXT: [[UADDLv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDLv4i16_v4i32 [[COPY1]], [[COPY]]776 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[UADDLv4i16_v4i32_]]777 %4:fpr(<4 x s16>) = COPY $d1778 %3:fpr(<4 x s16>) = COPY $d0779 %1:fpr(<4 x s32>) = G_ZEXT %4(<4 x s16>)780 %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)781 %2:fpr(<4 x s32>) = G_ADD %0, %1782 $noreg = PATCHABLE_RET %2(<4 x s32>)783 784...785---786name: test_rule348_id1330_at_idx27512787alignment: 4788legalized: true789regBankSelected: true790tracksRegLiveness: true791registers:792 - { id: 0, class: fpr }793 - { id: 1, class: fpr }794 - { id: 2, class: fpr }795 - { id: 3, class: fpr }796 - { id: 4, class: fpr }797liveins:798 - { reg: '$d0', virtual-reg: '%3' }799 - { reg: '$d1', virtual-reg: '%4' }800body: |801 bb.0.entry:802 liveins: $d0, $d1803 804 ; CHECK-LABEL: name: test_rule348_id1330_at_idx27512805 ; CHECK: liveins: $d0, $d1806 ; CHECK-NEXT: {{ $}}807 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d1808 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0809 ; CHECK-NEXT: [[UADDLv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDLv2i32_v2i64 [[COPY1]], [[COPY]]810 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[UADDLv2i32_v2i64_]]811 %4:fpr(<2 x s32>) = COPY $d1812 %3:fpr(<2 x s32>) = COPY $d0813 %1:fpr(<2 x s64>) = G_ZEXT %4(<2 x s32>)814 %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)815 %2:fpr(<2 x s64>) = G_ADD %0, %1816 $noreg = PATCHABLE_RET %2(<2 x s64>)817 818...819---820name: test_rule349_id1308_at_idx27608821alignment: 4822legalized: true823regBankSelected: true824tracksRegLiveness: true825registers:826 - { id: 0, class: fpr }827 - { id: 1, class: fpr }828 - { id: 2, class: fpr }829 - { id: 3, class: fpr }830 - { id: 4, class: fpr }831liveins:832 - { reg: '$d0', virtual-reg: '%3' }833 - { reg: '$d1', virtual-reg: '%4' }834body: |835 bb.0.entry:836 liveins: $d0, $d1837 838 ; CHECK-LABEL: name: test_rule349_id1308_at_idx27608839 ; CHECK: liveins: $d0, $d1840 ; CHECK-NEXT: {{ $}}841 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d1842 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0843 ; CHECK-NEXT: [[SSUBLv8i8_v8i16_:%[0-9]+]]:fpr128 = SSUBLv8i8_v8i16 [[COPY1]], [[COPY]]844 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SSUBLv8i8_v8i16_]]845 %4:fpr(<8 x s8>) = COPY $d1846 %3:fpr(<8 x s8>) = COPY $d0847 %1:fpr(<8 x s16>) = G_SEXT %4(<8 x s8>)848 %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)849 %2:fpr(<8 x s16>) = G_SUB %0, %1850 $noreg = PATCHABLE_RET %2(<8 x s16>)851 852...853---854name: test_rule350_id1310_at_idx27704855alignment: 4856legalized: true857regBankSelected: true858tracksRegLiveness: true859registers:860 - { id: 0, class: fpr }861 - { id: 1, class: fpr }862 - { id: 2, class: fpr }863 - { id: 3, class: fpr }864 - { id: 4, class: fpr }865liveins:866 - { reg: '$d0', virtual-reg: '%3' }867 - { reg: '$d1', virtual-reg: '%4' }868body: |869 bb.0.entry:870 liveins: $d0, $d1871 872 ; CHECK-LABEL: name: test_rule350_id1310_at_idx27704873 ; CHECK: liveins: $d0, $d1874 ; CHECK-NEXT: {{ $}}875 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d1876 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0877 ; CHECK-NEXT: [[SSUBLv4i16_v4i32_:%[0-9]+]]:fpr128 = SSUBLv4i16_v4i32 [[COPY1]], [[COPY]]878 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SSUBLv4i16_v4i32_]]879 %4:fpr(<4 x s16>) = COPY $d1880 %3:fpr(<4 x s16>) = COPY $d0881 %1:fpr(<4 x s32>) = G_SEXT %4(<4 x s16>)882 %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)883 %2:fpr(<4 x s32>) = G_SUB %0, %1884 $noreg = PATCHABLE_RET %2(<4 x s32>)885 886...887---888name: test_rule351_id1312_at_idx27800889alignment: 4890legalized: true891regBankSelected: true892tracksRegLiveness: true893registers:894 - { id: 0, class: fpr }895 - { id: 1, class: fpr }896 - { id: 2, class: fpr }897 - { id: 3, class: fpr }898 - { id: 4, class: fpr }899liveins:900 - { reg: '$d0', virtual-reg: '%3' }901 - { reg: '$d1', virtual-reg: '%4' }902body: |903 bb.0.entry:904 liveins: $d0, $d1905 906 ; CHECK-LABEL: name: test_rule351_id1312_at_idx27800907 ; CHECK: liveins: $d0, $d1908 ; CHECK-NEXT: {{ $}}909 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d1910 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0911 ; CHECK-NEXT: [[SSUBLv2i32_v2i64_:%[0-9]+]]:fpr128 = SSUBLv2i32_v2i64 [[COPY1]], [[COPY]]912 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SSUBLv2i32_v2i64_]]913 %4:fpr(<2 x s32>) = COPY $d1914 %3:fpr(<2 x s32>) = COPY $d0915 %1:fpr(<2 x s64>) = G_SEXT %4(<2 x s32>)916 %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)917 %2:fpr(<2 x s64>) = G_SUB %0, %1918 $noreg = PATCHABLE_RET %2(<2 x s64>)919 920...921---922name: test_rule352_id1356_at_idx27896923alignment: 4924legalized: true925regBankSelected: true926tracksRegLiveness: true927registers:928 - { id: 0, class: fpr }929 - { id: 1, class: fpr }930 - { id: 2, class: fpr }931 - { id: 3, class: fpr }932 - { id: 4, class: fpr }933liveins:934 - { reg: '$d0', virtual-reg: '%3' }935 - { reg: '$d1', virtual-reg: '%4' }936body: |937 bb.0.entry:938 liveins: $d0, $d1939 940 ; CHECK-LABEL: name: test_rule352_id1356_at_idx27896941 ; CHECK: liveins: $d0, $d1942 ; CHECK-NEXT: {{ $}}943 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d1944 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0945 ; CHECK-NEXT: [[USUBLv8i8_v8i16_:%[0-9]+]]:fpr128 = USUBLv8i8_v8i16 [[COPY1]], [[COPY]]946 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[USUBLv8i8_v8i16_]]947 %4:fpr(<8 x s8>) = COPY $d1948 %3:fpr(<8 x s8>) = COPY $d0949 %1:fpr(<8 x s16>) = G_ZEXT %4(<8 x s8>)950 %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)951 %2:fpr(<8 x s16>) = G_SUB %0, %1952 $noreg = PATCHABLE_RET %2(<8 x s16>)953 954...955---956name: test_rule353_id1358_at_idx27992957alignment: 4958legalized: true959regBankSelected: true960tracksRegLiveness: true961registers:962 - { id: 0, class: fpr }963 - { id: 1, class: fpr }964 - { id: 2, class: fpr }965 - { id: 3, class: fpr }966 - { id: 4, class: fpr }967liveins:968 - { reg: '$d0', virtual-reg: '%3' }969 - { reg: '$d1', virtual-reg: '%4' }970body: |971 bb.0.entry:972 liveins: $d0, $d1973 974 ; CHECK-LABEL: name: test_rule353_id1358_at_idx27992975 ; CHECK: liveins: $d0, $d1976 ; CHECK-NEXT: {{ $}}977 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d1978 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0979 ; CHECK-NEXT: [[USUBLv4i16_v4i32_:%[0-9]+]]:fpr128 = USUBLv4i16_v4i32 [[COPY1]], [[COPY]]980 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[USUBLv4i16_v4i32_]]981 %4:fpr(<4 x s16>) = COPY $d1982 %3:fpr(<4 x s16>) = COPY $d0983 %1:fpr(<4 x s32>) = G_ZEXT %4(<4 x s16>)984 %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)985 %2:fpr(<4 x s32>) = G_SUB %0, %1986 $noreg = PATCHABLE_RET %2(<4 x s32>)987 988...989---990name: test_rule354_id1360_at_idx28088991alignment: 4992legalized: true993regBankSelected: true994tracksRegLiveness: true995registers:996 - { id: 0, class: fpr }997 - { id: 1, class: fpr }998 - { id: 2, class: fpr }999 - { id: 3, class: fpr }1000 - { id: 4, class: fpr }1001liveins:1002 - { reg: '$d0', virtual-reg: '%3' }1003 - { reg: '$d1', virtual-reg: '%4' }1004body: |1005 bb.0.entry:1006 liveins: $d0, $d11007 1008 ; CHECK-LABEL: name: test_rule354_id1360_at_idx280881009 ; CHECK: liveins: $d0, $d11010 ; CHECK-NEXT: {{ $}}1011 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d11012 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d01013 ; CHECK-NEXT: [[USUBLv2i32_v2i64_:%[0-9]+]]:fpr128 = USUBLv2i32_v2i64 [[COPY1]], [[COPY]]1014 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[USUBLv2i32_v2i64_]]1015 %4:fpr(<2 x s32>) = COPY $d11016 %3:fpr(<2 x s32>) = COPY $d01017 %1:fpr(<2 x s64>) = G_ZEXT %4(<2 x s32>)1018 %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)1019 %2:fpr(<2 x s64>) = G_SUB %0, %11020 $noreg = PATCHABLE_RET %2(<2 x s64>)1021 1022...1023---1024name: test_rule928_id2367_at_idx600191025alignment: 41026legalized: true1027regBankSelected: true1028tracksRegLiveness: true1029registers:1030 - { id: 0, class: fpr }1031 - { id: 1, class: fpr }1032 - { id: 2, class: fpr }1033 - { id: 3, class: fpr }1034 - { id: 4, class: fpr }1035liveins:1036 - { reg: '$s0', virtual-reg: '%2' }1037 - { reg: '$s1', virtual-reg: '%3' }1038 - { reg: '$s2', virtual-reg: '%4' }1039body: |1040 bb.0.entry:1041 liveins: $s0, $s1, $s21042 1043 ; CHECK-LABEL: name: test_rule928_id2367_at_idx600191044 ; CHECK: liveins: $s0, $s1, $s21045 ; CHECK-NEXT: {{ $}}1046 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s21047 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s11048 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s01049 ; CHECK-NEXT: [[FMSUBSrrr:%[0-9]+]]:fpr32 = nofpexcept FMSUBSrrr [[COPY]], [[COPY2]], [[COPY1]], implicit $fpcr1050 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMSUBSrrr]]1051 %4:fpr(s32) = COPY $s21052 %3:fpr(s32) = COPY $s11053 %2:fpr(s32) = COPY $s01054 %0:fpr(s32) = G_FNEG %41055 %1:fpr(s32) = G_FMA %0, %2, %31056 $noreg = PATCHABLE_RET %1(s32)1057 1058...1059---1060name: test_rule929_id2368_at_idx601051061alignment: 41062legalized: true1063regBankSelected: true1064tracksRegLiveness: true1065registers:1066 - { id: 0, class: fpr }1067 - { id: 1, class: fpr }1068 - { id: 2, class: fpr }1069 - { id: 3, class: fpr }1070 - { id: 4, class: fpr }1071liveins:1072 - { reg: '$d0', virtual-reg: '%2' }1073 - { reg: '$d1', virtual-reg: '%3' }1074 - { reg: '$d2', virtual-reg: '%4' }1075body: |1076 bb.0.entry:1077 liveins: $d0, $d1, $d21078 1079 ; CHECK-LABEL: name: test_rule929_id2368_at_idx601051080 ; CHECK: liveins: $d0, $d1, $d21081 ; CHECK-NEXT: {{ $}}1082 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d21083 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11084 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d01085 ; CHECK-NEXT: [[FMSUBDrrr:%[0-9]+]]:fpr64 = nofpexcept FMSUBDrrr [[COPY]], [[COPY2]], [[COPY1]], implicit $fpcr1086 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMSUBDrrr]]1087 %4:fpr(s64) = COPY $d21088 %3:fpr(s64) = COPY $d11089 %2:fpr(s64) = COPY $d01090 %0:fpr(s64) = G_FNEG %41091 %1:fpr(s64) = G_FMA %0, %2, %31092 $noreg = PATCHABLE_RET %1(s64)1093 1094...1095---1096name: test_rule930_id2446_at_idx601911097alignment: 41098legalized: true1099regBankSelected: true1100tracksRegLiveness: true1101registers:1102 - { id: 0, class: fpr }1103 - { id: 1, class: fpr }1104 - { id: 2, class: fpr }1105 - { id: 3, class: fpr }1106 - { id: 4, class: fpr }1107liveins:1108 - { reg: '$d0', virtual-reg: '%2' }1109 - { reg: '$d1', virtual-reg: '%3' }1110 - { reg: '$d2', virtual-reg: '%4' }1111body: |1112 bb.0.entry:1113 liveins: $d0, $d1, $d21114 1115 ; CHECK-LABEL: name: test_rule930_id2446_at_idx601911116 ; CHECK: liveins: $d0, $d1, $d21117 ; CHECK-NEXT: {{ $}}1118 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d21119 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11120 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d01121 ; CHECK-NEXT: [[FMLSv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMLSv2f32 [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr1122 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLSv2f32_]]1123 %4:fpr(<2 x s32>) = COPY $d21124 %3:fpr(<2 x s32>) = COPY $d11125 %2:fpr(<2 x s32>) = COPY $d01126 %0:fpr(<2 x s32>) = G_FNEG %41127 %1:fpr(<2 x s32>) = G_FMA %0, %2, %31128 $noreg = PATCHABLE_RET %1(<2 x s32>)1129 1130...1131---1132name: test_rule931_id2447_at_idx602771133alignment: 41134legalized: true1135regBankSelected: true1136tracksRegLiveness: true1137registers:1138 - { id: 0, class: fpr }1139 - { id: 1, class: fpr }1140 - { id: 2, class: fpr }1141 - { id: 3, class: fpr }1142 - { id: 4, class: fpr }1143liveins:1144 - { reg: '$q0', virtual-reg: '%2' }1145 - { reg: '$q1', virtual-reg: '%3' }1146 - { reg: '$q2', virtual-reg: '%4' }1147body: |1148 bb.0.entry:1149 liveins: $q0, $q1, $q21150 1151 ; CHECK-LABEL: name: test_rule931_id2447_at_idx602771152 ; CHECK: liveins: $q0, $q1, $q21153 ; CHECK-NEXT: {{ $}}1154 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q21155 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q11156 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q01157 ; CHECK-NEXT: [[FMLSv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMLSv4f32 [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr1158 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLSv4f32_]]1159 %4:fpr(<4 x s32>) = COPY $q21160 %3:fpr(<4 x s32>) = COPY $q11161 %2:fpr(<4 x s32>) = COPY $q01162 %0:fpr(<4 x s32>) = G_FNEG %41163 %1:fpr(<4 x s32>) = G_FMA %0, %2, %31164 $noreg = PATCHABLE_RET %1(<4 x s32>)1165 1166...1167---1168name: test_rule932_id2448_at_idx603631169alignment: 41170legalized: true1171regBankSelected: true1172tracksRegLiveness: true1173registers:1174 - { id: 0, class: fpr }1175 - { id: 1, class: fpr }1176 - { id: 2, class: fpr }1177 - { id: 3, class: fpr }1178 - { id: 4, class: fpr }1179liveins:1180 - { reg: '$q0', virtual-reg: '%2' }1181 - { reg: '$q1', virtual-reg: '%3' }1182 - { reg: '$q2', virtual-reg: '%4' }1183body: |1184 bb.0.entry:1185 liveins: $q0, $q1, $q21186 1187 ; CHECK-LABEL: name: test_rule932_id2448_at_idx603631188 ; CHECK: liveins: $q0, $q1, $q21189 ; CHECK-NEXT: {{ $}}1190 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q21191 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q11192 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q01193 ; CHECK-NEXT: [[FMLSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMLSv2f64 [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr1194 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLSv2f64_]]1195 %4:fpr(<2 x s64>) = COPY $q21196 %3:fpr(<2 x s64>) = COPY $q11197 %2:fpr(<2 x s64>) = COPY $q01198 %0:fpr(<2 x s64>) = G_FNEG %41199 %1:fpr(<2 x s64>) = G_FMA %0, %2, %31200 $noreg = PATCHABLE_RET %1(<2 x s64>)1201 1202...1203---1204name: test_rule934_id429_at_idx605371205alignment: 41206legalized: true1207regBankSelected: true1208tracksRegLiveness: true1209registers:1210 - { id: 0, class: fpr }1211 - { id: 1, class: fpr }1212 - { id: 2, class: fpr }1213 - { id: 3, class: fpr }1214 - { id: 4, class: fpr }1215liveins:1216 - { reg: '$s0', virtual-reg: '%2' }1217 - { reg: '$s1', virtual-reg: '%3' }1218 - { reg: '$s2', virtual-reg: '%4' }1219body: |1220 bb.0.entry:1221 liveins: $s0, $s1, $s21222 1223 ; CHECK-LABEL: name: test_rule934_id429_at_idx605371224 ; CHECK: liveins: $s0, $s1, $s21225 ; CHECK-NEXT: {{ $}}1226 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s21227 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s11228 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s01229 ; CHECK-NEXT: [[FMSUBSrrr:%[0-9]+]]:fpr32 = nofpexcept FMSUBSrrr [[COPY2]], [[COPY]], [[COPY1]], implicit $fpcr1230 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMSUBSrrr]]1231 %4:fpr(s32) = COPY $s21232 %3:fpr(s32) = COPY $s11233 %2:fpr(s32) = COPY $s01234 %0:fpr(s32) = G_FNEG %41235 %1:fpr(s32) = G_FMA %2, %0, %31236 $noreg = PATCHABLE_RET %1(s32)1237 1238...1239---1240name: test_rule935_id430_at_idx606251241alignment: 41242legalized: true1243regBankSelected: true1244tracksRegLiveness: true1245registers:1246 - { id: 0, class: fpr }1247 - { id: 1, class: fpr }1248 - { id: 2, class: fpr }1249 - { id: 3, class: fpr }1250 - { id: 4, class: fpr }1251liveins:1252 - { reg: '$d0', virtual-reg: '%2' }1253 - { reg: '$d1', virtual-reg: '%3' }1254 - { reg: '$d2', virtual-reg: '%4' }1255body: |1256 bb.0.entry:1257 liveins: $d0, $d1, $d21258 1259 ; CHECK-LABEL: name: test_rule935_id430_at_idx606251260 ; CHECK: liveins: $d0, $d1, $d21261 ; CHECK-NEXT: {{ $}}1262 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d21263 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11264 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d01265 ; CHECK-NEXT: [[FMSUBDrrr:%[0-9]+]]:fpr64 = nofpexcept FMSUBDrrr [[COPY2]], [[COPY]], [[COPY1]], implicit $fpcr1266 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMSUBDrrr]]1267 %4:fpr(s64) = COPY $d21268 %3:fpr(s64) = COPY $d11269 %2:fpr(s64) = COPY $d01270 %0:fpr(s64) = G_FNEG %41271 %1:fpr(s64) = G_FMA %2, %0, %31272 $noreg = PATCHABLE_RET %1(s64)1273 1274...1275---1276name: test_rule938_id899_at_idx608891277alignment: 41278legalized: true1279regBankSelected: true1280tracksRegLiveness: true1281registers:1282 - { id: 0, class: fpr }1283 - { id: 1, class: fpr }1284 - { id: 2, class: fpr }1285 - { id: 3, class: fpr }1286 - { id: 4, class: fpr }1287liveins:1288 - { reg: '$d0', virtual-reg: '%2' }1289 - { reg: '$d1', virtual-reg: '%3' }1290 - { reg: '$d2', virtual-reg: '%4' }1291body: |1292 bb.0.entry:1293 liveins: $d0, $d1, $d21294 1295 ; CHECK-LABEL: name: test_rule938_id899_at_idx608891296 ; CHECK: liveins: $d0, $d1, $d21297 ; CHECK-NEXT: {{ $}}1298 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d21299 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11300 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d01301 ; CHECK-NEXT: [[FMLSv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMLSv2f32 [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr1302 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLSv2f32_]]1303 %4:fpr(<2 x s32>) = COPY $d21304 %3:fpr(<2 x s32>) = COPY $d11305 %2:fpr(<2 x s32>) = COPY $d01306 %0:fpr(<2 x s32>) = G_FNEG %41307 %1:fpr(<2 x s32>) = G_FMA %2, %0, %31308 $noreg = PATCHABLE_RET %1(<2 x s32>)1309 1310...1311---1312name: test_rule939_id900_at_idx609771313alignment: 41314legalized: true1315regBankSelected: true1316tracksRegLiveness: true1317registers:1318 - { id: 0, class: fpr }1319 - { id: 1, class: fpr }1320 - { id: 2, class: fpr }1321 - { id: 3, class: fpr }1322 - { id: 4, class: fpr }1323liveins:1324 - { reg: '$q0', virtual-reg: '%2' }1325 - { reg: '$q1', virtual-reg: '%3' }1326 - { reg: '$q2', virtual-reg: '%4' }1327body: |1328 bb.0.entry:1329 liveins: $q0, $q1, $q21330 1331 ; CHECK-LABEL: name: test_rule939_id900_at_idx609771332 ; CHECK: liveins: $q0, $q1, $q21333 ; CHECK-NEXT: {{ $}}1334 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q21335 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q11336 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q01337 ; CHECK-NEXT: [[FMLSv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMLSv4f32 [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr1338 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLSv4f32_]]1339 %4:fpr(<4 x s32>) = COPY $q21340 %3:fpr(<4 x s32>) = COPY $q11341 %2:fpr(<4 x s32>) = COPY $q01342 %0:fpr(<4 x s32>) = G_FNEG %41343 %1:fpr(<4 x s32>) = G_FMA %2, %0, %31344 $noreg = PATCHABLE_RET %1(<4 x s32>)1345 1346...1347---1348name: test_rule940_id901_at_idx610651349alignment: 41350legalized: true1351regBankSelected: true1352tracksRegLiveness: true1353registers:1354 - { id: 0, class: fpr }1355 - { id: 1, class: fpr }1356 - { id: 2, class: fpr }1357 - { id: 3, class: fpr }1358 - { id: 4, class: fpr }1359liveins:1360 - { reg: '$q0', virtual-reg: '%2' }1361 - { reg: '$q1', virtual-reg: '%3' }1362 - { reg: '$q2', virtual-reg: '%4' }1363body: |1364 bb.0.entry:1365 liveins: $q0, $q1, $q21366 1367 ; CHECK-LABEL: name: test_rule940_id901_at_idx610651368 ; CHECK: liveins: $q0, $q1, $q21369 ; CHECK-NEXT: {{ $}}1370 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q21371 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q11372 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q01373 ; CHECK-NEXT: [[FMLSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMLSv2f64 [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr1374 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLSv2f64_]]1375 %4:fpr(<2 x s64>) = COPY $q21376 %3:fpr(<2 x s64>) = COPY $q11377 %2:fpr(<2 x s64>) = COPY $q01378 %0:fpr(<2 x s64>) = G_FNEG %41379 %1:fpr(<2 x s64>) = G_FMA %2, %0, %31380 $noreg = PATCHABLE_RET %1(<2 x s64>)1381 1382...1383---1384name: test_rule942_id435_at_idx612411385alignment: 41386legalized: true1387regBankSelected: true1388tracksRegLiveness: true1389registers:1390 - { id: 0, class: fpr }1391 - { id: 1, class: fpr }1392 - { id: 2, class: fpr }1393 - { id: 3, class: fpr }1394 - { id: 4, class: fpr }1395liveins:1396 - { reg: '$s0', virtual-reg: '%2' }1397 - { reg: '$s1', virtual-reg: '%3' }1398 - { reg: '$s2', virtual-reg: '%4' }1399body: |1400 bb.0.entry:1401 liveins: $s0, $s1, $s21402 1403 ; CHECK-LABEL: name: test_rule942_id435_at_idx612411404 ; CHECK: liveins: $s0, $s1, $s21405 ; CHECK-NEXT: {{ $}}1406 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s21407 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s11408 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s01409 ; CHECK-NEXT: [[FNMSUBSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMSUBSrrr [[COPY2]], [[COPY1]], [[COPY]], implicit $fpcr1410 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMSUBSrrr]]1411 %4:fpr(s32) = COPY $s21412 %3:fpr(s32) = COPY $s11413 %2:fpr(s32) = COPY $s01414 %0:fpr(s32) = G_FNEG %41415 %1:fpr(s32) = G_FMA %2, %3, %01416 $noreg = PATCHABLE_RET %1(s32)1417 1418...1419---1420name: test_rule943_id436_at_idx613291421alignment: 41422legalized: true1423regBankSelected: true1424tracksRegLiveness: true1425registers:1426 - { id: 0, class: fpr }1427 - { id: 1, class: fpr }1428 - { id: 2, class: fpr }1429 - { id: 3, class: fpr }1430 - { id: 4, class: fpr }1431liveins:1432 - { reg: '$d0', virtual-reg: '%2' }1433 - { reg: '$d1', virtual-reg: '%3' }1434 - { reg: '$d2', virtual-reg: '%4' }1435body: |1436 bb.0.entry:1437 liveins: $d0, $d1, $d21438 1439 ; CHECK-LABEL: name: test_rule943_id436_at_idx613291440 ; CHECK: liveins: $d0, $d1, $d21441 ; CHECK-NEXT: {{ $}}1442 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d21443 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11444 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d01445 ; CHECK-NEXT: [[FNMSUBDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMSUBDrrr [[COPY2]], [[COPY1]], [[COPY]], implicit $fpcr1446 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMSUBDrrr]]1447 %4:fpr(s64) = COPY $d21448 %3:fpr(s64) = COPY $d11449 %2:fpr(s64) = COPY $d01450 %0:fpr(s64) = G_FNEG %41451 %1:fpr(s64) = G_FMA %2, %3, %01452 $noreg = PATCHABLE_RET %1(s64)1453 1454...1455---1456name: test_rule944_id3803_at_idx614171457alignment: 41458legalized: true1459regBankSelected: true1460tracksRegLiveness: true1461registers:1462 - { id: 0, class: fpr }1463 - { id: 1, class: fpr }1464 - { id: 2, class: fpr }1465 - { id: 3, class: fpr }1466 - { id: 4, class: fpr }1467liveins:1468 - { reg: '$d0', virtual-reg: '%2' }1469 - { reg: '$d1', virtual-reg: '%3' }1470 - { reg: '$d2', virtual-reg: '%4' }1471body: |1472 bb.0.entry:1473 liveins: $d0, $d1, $d21474 1475 ; CHECK-LABEL: name: test_rule944_id3803_at_idx614171476 ; CHECK: liveins: $d0, $d1, $d21477 ; CHECK-NEXT: {{ $}}1478 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d21479 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11480 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d01481 ; CHECK-NEXT: [[MULv8i8_:%[0-9]+]]:fpr64 = MULv8i8 [[COPY1]], [[COPY]]1482 ; CHECK-NEXT: [[ADDv8i8_:%[0-9]+]]:fpr64 = ADDv8i8 [[MULv8i8_]], [[COPY2]]1483 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[ADDv8i8_]]1484 %4:fpr(<8 x s8>) = COPY $d21485 %3:fpr(<8 x s8>) = COPY $d11486 %2:fpr(<8 x s8>) = COPY $d01487 %0:fpr(<8 x s8>) = G_MUL %3, %41488 %1:fpr(<8 x s8>) = G_ADD %0, %21489 $noreg = PATCHABLE_RET %1(<8 x s8>)1490 1491...1492---1493name: test_rule945_id3804_at_idx615051494alignment: 41495legalized: true1496regBankSelected: true1497tracksRegLiveness: true1498registers:1499 - { id: 0, class: fpr }1500 - { id: 1, class: fpr }1501 - { id: 2, class: fpr }1502 - { id: 3, class: fpr }1503 - { id: 4, class: fpr }1504liveins:1505 - { reg: '$q0', virtual-reg: '%2' }1506 - { reg: '$q1', virtual-reg: '%3' }1507 - { reg: '$q2', virtual-reg: '%4' }1508body: |1509 bb.0.entry:1510 liveins: $q0, $q1, $q21511 1512 ; CHECK-LABEL: name: test_rule945_id3804_at_idx615051513 ; CHECK: liveins: $q0, $q1, $q21514 ; CHECK-NEXT: {{ $}}1515 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q21516 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q11517 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q01518 ; CHECK-NEXT: [[MULv16i8_:%[0-9]+]]:fpr128 = MULv16i8 [[COPY1]], [[COPY]]1519 ; CHECK-NEXT: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[MULv16i8_]], [[COPY2]]1520 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[ADDv16i8_]]1521 %4:fpr(<16 x s8>) = COPY $q21522 %3:fpr(<16 x s8>) = COPY $q11523 %2:fpr(<16 x s8>) = COPY $q01524 %0:fpr(<16 x s8>) = G_MUL %3, %41525 %1:fpr(<16 x s8>) = G_ADD %0, %21526 $noreg = PATCHABLE_RET %1(<16 x s8>)1527 1528...1529---1530name: test_rule946_id3805_at_idx615931531alignment: 41532legalized: true1533regBankSelected: true1534tracksRegLiveness: true1535registers:1536 - { id: 0, class: fpr }1537 - { id: 1, class: fpr }1538 - { id: 2, class: fpr }1539 - { id: 3, class: fpr }1540 - { id: 4, class: fpr }1541liveins:1542 - { reg: '$d0', virtual-reg: '%2' }1543 - { reg: '$d1', virtual-reg: '%3' }1544 - { reg: '$d2', virtual-reg: '%4' }1545body: |1546 bb.0.entry:1547 liveins: $d0, $d1, $d21548 1549 ; CHECK-LABEL: name: test_rule946_id3805_at_idx615931550 ; CHECK: liveins: $d0, $d1, $d21551 ; CHECK-NEXT: {{ $}}1552 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d21553 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11554 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d01555 ; CHECK-NEXT: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY1]], [[COPY]]1556 ; CHECK-NEXT: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[MULv4i16_]], [[COPY2]]1557 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[ADDv4i16_]]1558 %4:fpr(<4 x s16>) = COPY $d21559 %3:fpr(<4 x s16>) = COPY $d11560 %2:fpr(<4 x s16>) = COPY $d01561 %0:fpr(<4 x s16>) = G_MUL %3, %41562 %1:fpr(<4 x s16>) = G_ADD %0, %21563 $noreg = PATCHABLE_RET %1(<4 x s16>)1564 1565...1566---1567name: test_rule947_id3806_at_idx616811568alignment: 41569legalized: true1570regBankSelected: true1571tracksRegLiveness: true1572registers:1573 - { id: 0, class: fpr }1574 - { id: 1, class: fpr }1575 - { id: 2, class: fpr }1576 - { id: 3, class: fpr }1577 - { id: 4, class: fpr }1578liveins:1579 - { reg: '$q0', virtual-reg: '%2' }1580 - { reg: '$q1', virtual-reg: '%3' }1581 - { reg: '$q2', virtual-reg: '%4' }1582body: |1583 bb.0.entry:1584 liveins: $q0, $q1, $q21585 1586 ; CHECK-LABEL: name: test_rule947_id3806_at_idx616811587 ; CHECK: liveins: $q0, $q1, $q21588 ; CHECK-NEXT: {{ $}}1589 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q21590 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q11591 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q01592 ; CHECK-NEXT: [[MULv8i16_:%[0-9]+]]:fpr128 = MULv8i16 [[COPY1]], [[COPY]]1593 ; CHECK-NEXT: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[MULv8i16_]], [[COPY2]]1594 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[ADDv8i16_]]1595 %4:fpr(<8 x s16>) = COPY $q21596 %3:fpr(<8 x s16>) = COPY $q11597 %2:fpr(<8 x s16>) = COPY $q01598 %0:fpr(<8 x s16>) = G_MUL %3, %41599 %1:fpr(<8 x s16>) = G_ADD %0, %21600 $noreg = PATCHABLE_RET %1(<8 x s16>)1601 1602...1603---1604name: test_rule950_id3869_at_idx619451605alignment: 41606legalized: true1607regBankSelected: true1608tracksRegLiveness: true1609registers:1610 - { id: 0, class: fpr }1611 - { id: 1, class: fpr }1612 - { id: 2, class: fpr }1613 - { id: 3, class: fpr }1614liveins:1615 - { reg: '$q0', virtual-reg: '%2' }1616 - { reg: '$d0', virtual-reg: '%3' }1617body: |1618 bb.0.entry:1619 liveins: $q0, $d01620 1621 ; CHECK-LABEL: name: test_rule950_id3869_at_idx619451622 ; CHECK: liveins: $q0, $d01623 ; CHECK-NEXT: {{ $}}1624 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01625 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q01626 ; CHECK-NEXT: [[SADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDWv8i8_v8i16 [[COPY1]], [[COPY]]1627 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SADDWv8i8_v8i16_]]1628 %3:fpr(<8 x s8>) = COPY $d01629 %2:fpr(<8 x s16>) = COPY $q01630 %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)1631 %1:fpr(<8 x s16>) = G_ADD %0, %21632 $noreg = PATCHABLE_RET %1(<8 x s16>)1633 1634...1635---1636name: test_rule951_id3871_at_idx620211637alignment: 41638legalized: true1639regBankSelected: true1640tracksRegLiveness: true1641registers:1642 - { id: 0, class: fpr }1643 - { id: 1, class: fpr }1644 - { id: 2, class: fpr }1645 - { id: 3, class: fpr }1646liveins:1647 - { reg: '$q0', virtual-reg: '%2' }1648 - { reg: '$d0', virtual-reg: '%3' }1649body: |1650 bb.0.entry:1651 liveins: $q0, $d01652 1653 ; CHECK-LABEL: name: test_rule951_id3871_at_idx620211654 ; CHECK: liveins: $q0, $d01655 ; CHECK-NEXT: {{ $}}1656 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01657 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q01658 ; CHECK-NEXT: [[SADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDWv4i16_v4i32 [[COPY1]], [[COPY]]1659 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SADDWv4i16_v4i32_]]1660 %3:fpr(<4 x s16>) = COPY $d01661 %2:fpr(<4 x s32>) = COPY $q01662 %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)1663 %1:fpr(<4 x s32>) = G_ADD %0, %21664 $noreg = PATCHABLE_RET %1(<4 x s32>)1665 1666...1667---1668name: test_rule952_id3873_at_idx620971669alignment: 41670legalized: true1671regBankSelected: true1672tracksRegLiveness: true1673registers:1674 - { id: 0, class: fpr }1675 - { id: 1, class: fpr }1676 - { id: 2, class: fpr }1677 - { id: 3, class: fpr }1678liveins:1679 - { reg: '$q0', virtual-reg: '%2' }1680 - { reg: '$d0', virtual-reg: '%3' }1681body: |1682 bb.0.entry:1683 liveins: $q0, $d01684 1685 ; CHECK-LABEL: name: test_rule952_id3873_at_idx620971686 ; CHECK: liveins: $q0, $d01687 ; CHECK-NEXT: {{ $}}1688 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01689 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q01690 ; CHECK-NEXT: [[SADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDWv2i32_v2i64 [[COPY1]], [[COPY]]1691 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SADDWv2i32_v2i64_]]1692 %3:fpr(<2 x s32>) = COPY $d01693 %2:fpr(<2 x s64>) = COPY $q01694 %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)1695 %1:fpr(<2 x s64>) = G_ADD %0, %21696 $noreg = PATCHABLE_RET %1(<2 x s64>)1697 1698...1699---1700name: test_rule953_id3887_at_idx621731701alignment: 41702legalized: true1703regBankSelected: true1704tracksRegLiveness: true1705registers:1706 - { id: 0, class: fpr }1707 - { id: 1, class: fpr }1708 - { id: 2, class: fpr }1709 - { id: 3, class: fpr }1710liveins:1711 - { reg: '$q0', virtual-reg: '%2' }1712 - { reg: '$d0', virtual-reg: '%3' }1713body: |1714 bb.0.entry:1715 liveins: $q0, $d01716 1717 ; CHECK-LABEL: name: test_rule953_id3887_at_idx621731718 ; CHECK: liveins: $q0, $d01719 ; CHECK-NEXT: {{ $}}1720 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01721 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q01722 ; CHECK-NEXT: [[UADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDWv8i8_v8i16 [[COPY1]], [[COPY]]1723 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[UADDWv8i8_v8i16_]]1724 %3:fpr(<8 x s8>) = COPY $d01725 %2:fpr(<8 x s16>) = COPY $q01726 %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)1727 %1:fpr(<8 x s16>) = G_ADD %0, %21728 $noreg = PATCHABLE_RET %1(<8 x s16>)1729 1730...1731---1732name: test_rule954_id3889_at_idx622491733alignment: 41734legalized: true1735regBankSelected: true1736tracksRegLiveness: true1737registers:1738 - { id: 0, class: fpr }1739 - { id: 1, class: fpr }1740 - { id: 2, class: fpr }1741 - { id: 3, class: fpr }1742liveins:1743 - { reg: '$q0', virtual-reg: '%2' }1744 - { reg: '$d0', virtual-reg: '%3' }1745body: |1746 bb.0.entry:1747 liveins: $q0, $d01748 1749 ; CHECK-LABEL: name: test_rule954_id3889_at_idx622491750 ; CHECK: liveins: $q0, $d01751 ; CHECK-NEXT: {{ $}}1752 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01753 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q01754 ; CHECK-NEXT: [[UADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDWv4i16_v4i32 [[COPY1]], [[COPY]]1755 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[UADDWv4i16_v4i32_]]1756 %3:fpr(<4 x s16>) = COPY $d01757 %2:fpr(<4 x s32>) = COPY $q01758 %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)1759 %1:fpr(<4 x s32>) = G_ADD %0, %21760 $noreg = PATCHABLE_RET %1(<4 x s32>)1761 1762...1763---1764name: test_rule955_id3891_at_idx623251765alignment: 41766legalized: true1767regBankSelected: true1768tracksRegLiveness: true1769registers:1770 - { id: 0, class: fpr }1771 - { id: 1, class: fpr }1772 - { id: 2, class: fpr }1773 - { id: 3, class: fpr }1774liveins:1775 - { reg: '$q0', virtual-reg: '%2' }1776 - { reg: '$d0', virtual-reg: '%3' }1777body: |1778 bb.0.entry:1779 liveins: $q0, $d01780 1781 ; CHECK-LABEL: name: test_rule955_id3891_at_idx623251782 ; CHECK: liveins: $q0, $d01783 ; CHECK-NEXT: {{ $}}1784 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01785 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q01786 ; CHECK-NEXT: [[UADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDWv2i32_v2i64 [[COPY1]], [[COPY]]1787 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[UADDWv2i32_v2i64_]]1788 %3:fpr(<2 x s32>) = COPY $d01789 %2:fpr(<2 x s64>) = COPY $q01790 %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)1791 %1:fpr(<2 x s64>) = G_ADD %0, %21792 $noreg = PATCHABLE_RET %1(<2 x s64>)1793 1794...1795---1796name: test_rule956_id927_at_idx624011797alignment: 41798legalized: true1799regBankSelected: true1800tracksRegLiveness: true1801registers:1802 - { id: 0, class: fpr }1803 - { id: 1, class: fpr }1804 - { id: 2, class: fpr }1805 - { id: 3, class: fpr }1806 - { id: 4, class: fpr }1807liveins:1808 - { reg: '$d0', virtual-reg: '%2' }1809 - { reg: '$d1', virtual-reg: '%3' }1810 - { reg: '$d2', virtual-reg: '%4' }1811body: |1812 bb.0.entry:1813 liveins: $d0, $d1, $d21814 1815 ; CHECK-LABEL: name: test_rule956_id927_at_idx624011816 ; CHECK: liveins: $d0, $d1, $d21817 ; CHECK-NEXT: {{ $}}1818 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d21819 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11820 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d01821 ; CHECK-NEXT: [[MULv8i8_:%[0-9]+]]:fpr64 = MULv8i8 [[COPY1]], [[COPY]]1822 ; CHECK-NEXT: [[ADDv8i8_:%[0-9]+]]:fpr64 = ADDv8i8 [[COPY2]], [[MULv8i8_]]1823 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[ADDv8i8_]]1824 %4:fpr(<8 x s8>) = COPY $d21825 %3:fpr(<8 x s8>) = COPY $d11826 %2:fpr(<8 x s8>) = COPY $d01827 %0:fpr(<8 x s8>) = G_MUL %3, %41828 %1:fpr(<8 x s8>) = G_ADD %2, %01829 $noreg = PATCHABLE_RET %1(<8 x s8>)1830 1831...1832---1833name: test_rule957_id928_at_idx624891834alignment: 41835legalized: true1836regBankSelected: true1837tracksRegLiveness: true1838registers:1839 - { id: 0, class: fpr }1840 - { id: 1, class: fpr }1841 - { id: 2, class: fpr }1842 - { id: 3, class: fpr }1843 - { id: 4, class: fpr }1844liveins:1845 - { reg: '$q0', virtual-reg: '%2' }1846 - { reg: '$q1', virtual-reg: '%3' }1847 - { reg: '$q2', virtual-reg: '%4' }1848body: |1849 bb.0.entry:1850 liveins: $q0, $q1, $q21851 1852 ; CHECK-LABEL: name: test_rule957_id928_at_idx624891853 ; CHECK: liveins: $q0, $q1, $q21854 ; CHECK-NEXT: {{ $}}1855 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q21856 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q11857 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q01858 ; CHECK-NEXT: [[MULv16i8_:%[0-9]+]]:fpr128 = MULv16i8 [[COPY1]], [[COPY]]1859 ; CHECK-NEXT: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[COPY2]], [[MULv16i8_]]1860 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[ADDv16i8_]]1861 %4:fpr(<16 x s8>) = COPY $q21862 %3:fpr(<16 x s8>) = COPY $q11863 %2:fpr(<16 x s8>) = COPY $q01864 %0:fpr(<16 x s8>) = G_MUL %3, %41865 %1:fpr(<16 x s8>) = G_ADD %2, %01866 $noreg = PATCHABLE_RET %1(<16 x s8>)1867 1868...1869---1870name: test_rule958_id929_at_idx625771871alignment: 41872legalized: true1873regBankSelected: true1874tracksRegLiveness: true1875registers:1876 - { id: 0, class: fpr }1877 - { id: 1, class: fpr }1878 - { id: 2, class: fpr }1879 - { id: 3, class: fpr }1880 - { id: 4, class: fpr }1881liveins:1882 - { reg: '$d0', virtual-reg: '%2' }1883 - { reg: '$d1', virtual-reg: '%3' }1884 - { reg: '$d2', virtual-reg: '%4' }1885body: |1886 bb.0.entry:1887 liveins: $d0, $d1, $d21888 1889 ; CHECK-LABEL: name: test_rule958_id929_at_idx625771890 ; CHECK: liveins: $d0, $d1, $d21891 ; CHECK-NEXT: {{ $}}1892 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d21893 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11894 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d01895 ; CHECK-NEXT: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY1]], [[COPY]]1896 ; CHECK-NEXT: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[COPY2]], [[MULv4i16_]]1897 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[ADDv4i16_]]1898 %4:fpr(<4 x s16>) = COPY $d21899 %3:fpr(<4 x s16>) = COPY $d11900 %2:fpr(<4 x s16>) = COPY $d01901 %0:fpr(<4 x s16>) = G_MUL %3, %41902 %1:fpr(<4 x s16>) = G_ADD %2, %01903 $noreg = PATCHABLE_RET %1(<4 x s16>)1904 1905...1906---1907name: test_rule959_id930_at_idx626651908alignment: 41909legalized: true1910regBankSelected: true1911tracksRegLiveness: true1912registers:1913 - { id: 0, class: fpr }1914 - { id: 1, class: fpr }1915 - { id: 2, class: fpr }1916 - { id: 3, class: fpr }1917 - { id: 4, class: fpr }1918liveins:1919 - { reg: '$q0', virtual-reg: '%2' }1920 - { reg: '$q1', virtual-reg: '%3' }1921 - { reg: '$q2', virtual-reg: '%4' }1922body: |1923 bb.0.entry:1924 liveins: $q0, $q1, $q21925 1926 ; CHECK-LABEL: name: test_rule959_id930_at_idx626651927 ; CHECK: liveins: $q0, $q1, $q21928 ; CHECK-NEXT: {{ $}}1929 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q21930 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q11931 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q01932 ; CHECK-NEXT: [[MULv8i16_:%[0-9]+]]:fpr128 = MULv8i16 [[COPY1]], [[COPY]]1933 ; CHECK-NEXT: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[COPY2]], [[MULv8i16_]]1934 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[ADDv8i16_]]1935 %4:fpr(<8 x s16>) = COPY $q21936 %3:fpr(<8 x s16>) = COPY $q11937 %2:fpr(<8 x s16>) = COPY $q01938 %0:fpr(<8 x s16>) = G_MUL %3, %41939 %1:fpr(<8 x s16>) = G_ADD %2, %01940 $noreg = PATCHABLE_RET %1(<8 x s16>)1941 1942...1943---1944name: test_rule962_id1272_at_idx629291945alignment: 41946legalized: true1947regBankSelected: true1948tracksRegLiveness: true1949registers:1950 - { id: 0, class: fpr }1951 - { id: 1, class: fpr }1952 - { id: 2, class: fpr }1953 - { id: 3, class: fpr }1954liveins:1955 - { reg: '$q0', virtual-reg: '%2' }1956 - { reg: '$d0', virtual-reg: '%3' }1957body: |1958 bb.0.entry:1959 liveins: $q0, $d01960 1961 ; CHECK-LABEL: name: test_rule962_id1272_at_idx629291962 ; CHECK: liveins: $q0, $d01963 ; CHECK-NEXT: {{ $}}1964 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01965 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q01966 ; CHECK-NEXT: [[SADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDWv8i8_v8i16 [[COPY1]], [[COPY]]1967 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SADDWv8i8_v8i16_]]1968 %3:fpr(<8 x s8>) = COPY $d01969 %2:fpr(<8 x s16>) = COPY $q01970 %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)1971 %1:fpr(<8 x s16>) = G_ADD %2, %01972 $noreg = PATCHABLE_RET %1(<8 x s16>)1973 1974...1975---1976name: test_rule963_id1274_at_idx630051977alignment: 41978legalized: true1979regBankSelected: true1980tracksRegLiveness: true1981registers:1982 - { id: 0, class: fpr }1983 - { id: 1, class: fpr }1984 - { id: 2, class: fpr }1985 - { id: 3, class: fpr }1986liveins:1987 - { reg: '$q0', virtual-reg: '%2' }1988 - { reg: '$d0', virtual-reg: '%3' }1989body: |1990 bb.0.entry:1991 liveins: $q0, $d01992 1993 ; CHECK-LABEL: name: test_rule963_id1274_at_idx630051994 ; CHECK: liveins: $q0, $d01995 ; CHECK-NEXT: {{ $}}1996 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01997 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q01998 ; CHECK-NEXT: [[SADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDWv4i16_v4i32 [[COPY1]], [[COPY]]1999 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SADDWv4i16_v4i32_]]2000 %3:fpr(<4 x s16>) = COPY $d02001 %2:fpr(<4 x s32>) = COPY $q02002 %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)2003 %1:fpr(<4 x s32>) = G_ADD %2, %02004 $noreg = PATCHABLE_RET %1(<4 x s32>)2005 2006...2007---2008name: test_rule964_id1276_at_idx630812009alignment: 42010legalized: true2011regBankSelected: true2012tracksRegLiveness: true2013registers:2014 - { id: 0, class: fpr }2015 - { id: 1, class: fpr }2016 - { id: 2, class: fpr }2017 - { id: 3, class: fpr }2018liveins:2019 - { reg: '$q0', virtual-reg: '%2' }2020 - { reg: '$d0', virtual-reg: '%3' }2021body: |2022 bb.0.entry:2023 liveins: $q0, $d02024 2025 ; CHECK-LABEL: name: test_rule964_id1276_at_idx630812026 ; CHECK: liveins: $q0, $d02027 ; CHECK-NEXT: {{ $}}2028 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d02029 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q02030 ; CHECK-NEXT: [[SADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDWv2i32_v2i64 [[COPY1]], [[COPY]]2031 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SADDWv2i32_v2i64_]]2032 %3:fpr(<2 x s32>) = COPY $d02033 %2:fpr(<2 x s64>) = COPY $q02034 %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)2035 %1:fpr(<2 x s64>) = G_ADD %2, %02036 $noreg = PATCHABLE_RET %1(<2 x s64>)2037 2038...2039---2040name: test_rule965_id1332_at_idx631572041alignment: 42042legalized: true2043regBankSelected: true2044tracksRegLiveness: true2045registers:2046 - { id: 0, class: fpr }2047 - { id: 1, class: fpr }2048 - { id: 2, class: fpr }2049 - { id: 3, class: fpr }2050liveins:2051 - { reg: '$q0', virtual-reg: '%2' }2052 - { reg: '$d0', virtual-reg: '%3' }2053body: |2054 bb.0.entry:2055 liveins: $q0, $d02056 2057 ; CHECK-LABEL: name: test_rule965_id1332_at_idx631572058 ; CHECK: liveins: $q0, $d02059 ; CHECK-NEXT: {{ $}}2060 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d02061 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q02062 ; CHECK-NEXT: [[UADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDWv8i8_v8i16 [[COPY1]], [[COPY]]2063 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[UADDWv8i8_v8i16_]]2064 %3:fpr(<8 x s8>) = COPY $d02065 %2:fpr(<8 x s16>) = COPY $q02066 %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)2067 %1:fpr(<8 x s16>) = G_ADD %2, %02068 $noreg = PATCHABLE_RET %1(<8 x s16>)2069 2070...2071---2072name: test_rule966_id1334_at_idx632332073alignment: 42074legalized: true2075regBankSelected: true2076tracksRegLiveness: true2077registers:2078 - { id: 0, class: fpr }2079 - { id: 1, class: fpr }2080 - { id: 2, class: fpr }2081 - { id: 3, class: fpr }2082liveins:2083 - { reg: '$q0', virtual-reg: '%2' }2084 - { reg: '$d0', virtual-reg: '%3' }2085body: |2086 bb.0.entry:2087 liveins: $q0, $d02088 2089 ; CHECK-LABEL: name: test_rule966_id1334_at_idx632332090 ; CHECK: liveins: $q0, $d02091 ; CHECK-NEXT: {{ $}}2092 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d02093 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q02094 ; CHECK-NEXT: [[UADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDWv4i16_v4i32 [[COPY1]], [[COPY]]2095 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[UADDWv4i16_v4i32_]]2096 %3:fpr(<4 x s16>) = COPY $d02097 %2:fpr(<4 x s32>) = COPY $q02098 %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)2099 %1:fpr(<4 x s32>) = G_ADD %2, %02100 $noreg = PATCHABLE_RET %1(<4 x s32>)2101 2102...2103---2104name: test_rule967_id1336_at_idx633092105alignment: 42106legalized: true2107regBankSelected: true2108tracksRegLiveness: true2109registers:2110 - { id: 0, class: fpr }2111 - { id: 1, class: fpr }2112 - { id: 2, class: fpr }2113 - { id: 3, class: fpr }2114liveins:2115 - { reg: '$q0', virtual-reg: '%2' }2116 - { reg: '$d0', virtual-reg: '%3' }2117body: |2118 bb.0.entry:2119 liveins: $q0, $d02120 2121 ; CHECK-LABEL: name: test_rule967_id1336_at_idx633092122 ; CHECK: liveins: $q0, $d02123 ; CHECK-NEXT: {{ $}}2124 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d02125 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q02126 ; CHECK-NEXT: [[UADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDWv2i32_v2i64 [[COPY1]], [[COPY]]2127 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[UADDWv2i32_v2i64_]]2128 %3:fpr(<2 x s32>) = COPY $d02129 %2:fpr(<2 x s64>) = COPY $q02130 %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)2131 %1:fpr(<2 x s64>) = G_ADD %2, %02132 $noreg = PATCHABLE_RET %1(<2 x s64>)2133 2134...2135---2136name: test_rule977_id933_at_idx640512137alignment: 42138legalized: true2139regBankSelected: true2140tracksRegLiveness: true2141registers:2142 - { id: 0, class: fpr }2143 - { id: 1, class: fpr }2144 - { id: 2, class: fpr }2145 - { id: 3, class: fpr }2146 - { id: 4, class: fpr }2147liveins:2148 - { reg: '$d0', virtual-reg: '%2' }2149 - { reg: '$d1', virtual-reg: '%3' }2150 - { reg: '$d2', virtual-reg: '%4' }2151body: |2152 bb.0.entry:2153 liveins: $d0, $d1, $d22154 2155 ; CHECK-LABEL: name: test_rule977_id933_at_idx640512156 ; CHECK: liveins: $d0, $d1, $d22157 ; CHECK-NEXT: {{ $}}2158 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d22159 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d12160 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d02161 ; CHECK-NEXT: [[MULv8i8_:%[0-9]+]]:fpr64 = MULv8i8 [[COPY1]], [[COPY]]2162 ; CHECK-NEXT: [[SUBv8i8_:%[0-9]+]]:fpr64 = SUBv8i8 [[COPY2]], [[MULv8i8_]]2163 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SUBv8i8_]]2164 %4:fpr(<8 x s8>) = COPY $d22165 %3:fpr(<8 x s8>) = COPY $d12166 %2:fpr(<8 x s8>) = COPY $d02167 %0:fpr(<8 x s8>) = G_MUL %3, %42168 %1:fpr(<8 x s8>) = G_SUB %2, %02169 $noreg = PATCHABLE_RET %1(<8 x s8>)2170 2171...2172---2173name: test_rule978_id934_at_idx641392174alignment: 42175legalized: true2176regBankSelected: true2177tracksRegLiveness: true2178registers:2179 - { id: 0, class: fpr }2180 - { id: 1, class: fpr }2181 - { id: 2, class: fpr }2182 - { id: 3, class: fpr }2183 - { id: 4, class: fpr }2184liveins:2185 - { reg: '$q0', virtual-reg: '%2' }2186 - { reg: '$q1', virtual-reg: '%3' }2187 - { reg: '$q2', virtual-reg: '%4' }2188body: |2189 bb.0.entry:2190 liveins: $q0, $q1, $q22191 2192 ; CHECK-LABEL: name: test_rule978_id934_at_idx641392193 ; CHECK: liveins: $q0, $q1, $q22194 ; CHECK-NEXT: {{ $}}2195 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q22196 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q12197 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q02198 ; CHECK-NEXT: [[MULv16i8_:%[0-9]+]]:fpr128 = MULv16i8 [[COPY1]], [[COPY]]2199 ; CHECK-NEXT: [[SUBv16i8_:%[0-9]+]]:fpr128 = SUBv16i8 [[COPY2]], [[MULv16i8_]]2200 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SUBv16i8_]]2201 %4:fpr(<16 x s8>) = COPY $q22202 %3:fpr(<16 x s8>) = COPY $q12203 %2:fpr(<16 x s8>) = COPY $q02204 %0:fpr(<16 x s8>) = G_MUL %3, %42205 %1:fpr(<16 x s8>) = G_SUB %2, %02206 $noreg = PATCHABLE_RET %1(<16 x s8>)2207 2208...2209---2210name: test_rule979_id935_at_idx642272211alignment: 42212legalized: true2213regBankSelected: true2214tracksRegLiveness: true2215registers:2216 - { id: 0, class: fpr }2217 - { id: 1, class: fpr }2218 - { id: 2, class: fpr }2219 - { id: 3, class: fpr }2220 - { id: 4, class: fpr }2221liveins:2222 - { reg: '$d0', virtual-reg: '%2' }2223 - { reg: '$d1', virtual-reg: '%3' }2224 - { reg: '$d2', virtual-reg: '%4' }2225body: |2226 bb.0.entry:2227 liveins: $d0, $d1, $d22228 2229 ; CHECK-LABEL: name: test_rule979_id935_at_idx642272230 ; CHECK: liveins: $d0, $d1, $d22231 ; CHECK-NEXT: {{ $}}2232 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d22233 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d12234 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d02235 ; CHECK-NEXT: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY1]], [[COPY]]2236 ; CHECK-NEXT: [[SUBv4i16_:%[0-9]+]]:fpr64 = SUBv4i16 [[COPY2]], [[MULv4i16_]]2237 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SUBv4i16_]]2238 %4:fpr(<4 x s16>) = COPY $d22239 %3:fpr(<4 x s16>) = COPY $d12240 %2:fpr(<4 x s16>) = COPY $d02241 %0:fpr(<4 x s16>) = G_MUL %3, %42242 %1:fpr(<4 x s16>) = G_SUB %2, %02243 $noreg = PATCHABLE_RET %1(<4 x s16>)2244 2245...2246---2247name: test_rule980_id936_at_idx643152248alignment: 42249legalized: true2250regBankSelected: true2251tracksRegLiveness: true2252registers:2253 - { id: 0, class: fpr }2254 - { id: 1, class: fpr }2255 - { id: 2, class: fpr }2256 - { id: 3, class: fpr }2257 - { id: 4, class: fpr }2258liveins:2259 - { reg: '$q0', virtual-reg: '%2' }2260 - { reg: '$q1', virtual-reg: '%3' }2261 - { reg: '$q2', virtual-reg: '%4' }2262body: |2263 bb.0.entry:2264 liveins: $q0, $q1, $q22265 2266 ; CHECK-LABEL: name: test_rule980_id936_at_idx643152267 ; CHECK: liveins: $q0, $q1, $q22268 ; CHECK-NEXT: {{ $}}2269 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q22270 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q12271 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q02272 ; CHECK-NEXT: [[MULv8i16_:%[0-9]+]]:fpr128 = MULv8i16 [[COPY1]], [[COPY]]2273 ; CHECK-NEXT: [[SUBv8i16_:%[0-9]+]]:fpr128 = SUBv8i16 [[COPY2]], [[MULv8i16_]]2274 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SUBv8i16_]]2275 %4:fpr(<8 x s16>) = COPY $q22276 %3:fpr(<8 x s16>) = COPY $q12277 %2:fpr(<8 x s16>) = COPY $q02278 %0:fpr(<8 x s16>) = G_MUL %3, %42279 %1:fpr(<8 x s16>) = G_SUB %2, %02280 $noreg = PATCHABLE_RET %1(<8 x s16>)2281 2282...2283---2284name: test_rule983_id1314_at_idx645792285alignment: 42286legalized: true2287regBankSelected: true2288tracksRegLiveness: true2289registers:2290 - { id: 0, class: fpr }2291 - { id: 1, class: fpr }2292 - { id: 2, class: fpr }2293 - { id: 3, class: fpr }2294liveins:2295 - { reg: '$q0', virtual-reg: '%2' }2296 - { reg: '$d0', virtual-reg: '%3' }2297body: |2298 bb.0.entry:2299 liveins: $q0, $d02300 2301 ; CHECK-LABEL: name: test_rule983_id1314_at_idx645792302 ; CHECK: liveins: $q0, $d02303 ; CHECK-NEXT: {{ $}}2304 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d02305 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q02306 ; CHECK-NEXT: [[SSUBWv8i8_v8i16_:%[0-9]+]]:fpr128 = SSUBWv8i8_v8i16 [[COPY1]], [[COPY]]2307 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SSUBWv8i8_v8i16_]]2308 %3:fpr(<8 x s8>) = COPY $d02309 %2:fpr(<8 x s16>) = COPY $q02310 %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)2311 %1:fpr(<8 x s16>) = G_SUB %2, %02312 $noreg = PATCHABLE_RET %1(<8 x s16>)2313 2314...2315---2316name: test_rule984_id1316_at_idx646552317alignment: 42318legalized: true2319regBankSelected: true2320tracksRegLiveness: true2321registers:2322 - { id: 0, class: fpr }2323 - { id: 1, class: fpr }2324 - { id: 2, class: fpr }2325 - { id: 3, class: fpr }2326liveins:2327 - { reg: '$q0', virtual-reg: '%2' }2328 - { reg: '$d0', virtual-reg: '%3' }2329body: |2330 bb.0.entry:2331 liveins: $q0, $d02332 2333 ; CHECK-LABEL: name: test_rule984_id1316_at_idx646552334 ; CHECK: liveins: $q0, $d02335 ; CHECK-NEXT: {{ $}}2336 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d02337 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q02338 ; CHECK-NEXT: [[SSUBWv4i16_v4i32_:%[0-9]+]]:fpr128 = SSUBWv4i16_v4i32 [[COPY1]], [[COPY]]2339 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SSUBWv4i16_v4i32_]]2340 %3:fpr(<4 x s16>) = COPY $d02341 %2:fpr(<4 x s32>) = COPY $q02342 %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)2343 %1:fpr(<4 x s32>) = G_SUB %2, %02344 $noreg = PATCHABLE_RET %1(<4 x s32>)2345 2346...2347---2348name: test_rule985_id1318_at_idx647312349alignment: 42350legalized: true2351regBankSelected: true2352tracksRegLiveness: true2353registers:2354 - { id: 0, class: fpr }2355 - { id: 1, class: fpr }2356 - { id: 2, class: fpr }2357 - { id: 3, class: fpr }2358liveins:2359 - { reg: '$q0', virtual-reg: '%2' }2360 - { reg: '$d0', virtual-reg: '%3' }2361body: |2362 bb.0.entry:2363 liveins: $q0, $d02364 2365 ; CHECK-LABEL: name: test_rule985_id1318_at_idx647312366 ; CHECK: liveins: $q0, $d02367 ; CHECK-NEXT: {{ $}}2368 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d02369 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q02370 ; CHECK-NEXT: [[SSUBWv2i32_v2i64_:%[0-9]+]]:fpr128 = SSUBWv2i32_v2i64 [[COPY1]], [[COPY]]2371 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SSUBWv2i32_v2i64_]]2372 %3:fpr(<2 x s32>) = COPY $d02373 %2:fpr(<2 x s64>) = COPY $q02374 %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)2375 %1:fpr(<2 x s64>) = G_SUB %2, %02376 $noreg = PATCHABLE_RET %1(<2 x s64>)2377 2378...2379---2380name: test_rule986_id1362_at_idx648072381alignment: 42382legalized: true2383regBankSelected: true2384tracksRegLiveness: true2385registers:2386 - { id: 0, class: fpr }2387 - { id: 1, class: fpr }2388 - { id: 2, class: fpr }2389 - { id: 3, class: fpr }2390liveins:2391 - { reg: '$q0', virtual-reg: '%2' }2392 - { reg: '$d0', virtual-reg: '%3' }2393body: |2394 bb.0.entry:2395 liveins: $q0, $d02396 2397 ; CHECK-LABEL: name: test_rule986_id1362_at_idx648072398 ; CHECK: liveins: $q0, $d02399 ; CHECK-NEXT: {{ $}}2400 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d02401 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q02402 ; CHECK-NEXT: [[USUBWv8i8_v8i16_:%[0-9]+]]:fpr128 = USUBWv8i8_v8i16 [[COPY1]], [[COPY]]2403 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[USUBWv8i8_v8i16_]]2404 %3:fpr(<8 x s8>) = COPY $d02405 %2:fpr(<8 x s16>) = COPY $q02406 %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)2407 %1:fpr(<8 x s16>) = G_SUB %2, %02408 $noreg = PATCHABLE_RET %1(<8 x s16>)2409 2410...2411---2412name: test_rule987_id1364_at_idx648832413alignment: 42414legalized: true2415regBankSelected: true2416tracksRegLiveness: true2417registers:2418 - { id: 0, class: fpr }2419 - { id: 1, class: fpr }2420 - { id: 2, class: fpr }2421 - { id: 3, class: fpr }2422liveins:2423 - { reg: '$q0', virtual-reg: '%2' }2424 - { reg: '$d0', virtual-reg: '%3' }2425body: |2426 bb.0.entry:2427 liveins: $q0, $d02428 2429 ; CHECK-LABEL: name: test_rule987_id1364_at_idx648832430 ; CHECK: liveins: $q0, $d02431 ; CHECK-NEXT: {{ $}}2432 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d02433 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q02434 ; CHECK-NEXT: [[USUBWv4i16_v4i32_:%[0-9]+]]:fpr128 = USUBWv4i16_v4i32 [[COPY1]], [[COPY]]2435 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[USUBWv4i16_v4i32_]]2436 %3:fpr(<4 x s16>) = COPY $d02437 %2:fpr(<4 x s32>) = COPY $q02438 %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)2439 %1:fpr(<4 x s32>) = G_SUB %2, %02440 $noreg = PATCHABLE_RET %1(<4 x s32>)2441 2442...2443---2444name: test_rule988_id1366_at_idx649592445alignment: 42446legalized: true2447regBankSelected: true2448tracksRegLiveness: true2449registers:2450 - { id: 0, class: fpr }2451 - { id: 1, class: fpr }2452 - { id: 2, class: fpr }2453 - { id: 3, class: fpr }2454liveins:2455 - { reg: '$q0', virtual-reg: '%2' }2456 - { reg: '$d0', virtual-reg: '%3' }2457body: |2458 bb.0.entry:2459 liveins: $q0, $d02460 2461 ; CHECK-LABEL: name: test_rule988_id1366_at_idx649592462 ; CHECK: liveins: $q0, $d02463 ; CHECK-NEXT: {{ $}}2464 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d02465 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q02466 ; CHECK-NEXT: [[USUBWv2i32_v2i64_:%[0-9]+]]:fpr128 = USUBWv2i32_v2i64 [[COPY1]], [[COPY]]2467 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[USUBWv2i32_v2i64_]]2468 %3:fpr(<2 x s32>) = COPY $d02469 %2:fpr(<2 x s64>) = COPY $q02470 %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)2471 %1:fpr(<2 x s64>) = G_SUB %2, %02472 $noreg = PATCHABLE_RET %1(<2 x s64>)2473 2474...2475---2476name: test_rule990_id432_at_idx651232477alignment: 42478legalized: true2479regBankSelected: true2480tracksRegLiveness: true2481registers:2482 - { id: 0, class: fpr }2483 - { id: 1, class: fpr }2484 - { id: 2, class: fpr }2485 - { id: 3, class: fpr }2486 - { id: 4, class: fpr }2487liveins:2488 - { reg: '$s0', virtual-reg: '%2' }2489 - { reg: '$s1', virtual-reg: '%3' }2490 - { reg: '$s2', virtual-reg: '%4' }2491body: |2492 bb.0.entry:2493 liveins: $s0, $s1, $s22494 2495 ; CHECK-LABEL: name: test_rule990_id432_at_idx651232496 ; CHECK: liveins: $s0, $s1, $s22497 ; CHECK-NEXT: {{ $}}2498 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s22499 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s12500 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s02501 ; CHECK-NEXT: [[FNMADDSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMADDSrrr [[COPY2]], [[COPY1]], [[COPY]], implicit $fpcr2502 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMADDSrrr]]2503 %4:fpr(s32) = COPY $s22504 %3:fpr(s32) = COPY $s12505 %2:fpr(s32) = COPY $s02506 %0:fpr(s32) = G_FMA %2, %3, %42507 %1:fpr(s32) = G_FNEG %02508 $noreg = PATCHABLE_RET %1(s32)2509 2510...2511---2512name: test_rule991_id433_at_idx652112513alignment: 42514legalized: true2515regBankSelected: true2516tracksRegLiveness: true2517registers:2518 - { id: 0, class: fpr }2519 - { id: 1, class: fpr }2520 - { id: 2, class: fpr }2521 - { id: 3, class: fpr }2522 - { id: 4, class: fpr }2523liveins:2524 - { reg: '$d0', virtual-reg: '%2' }2525 - { reg: '$d1', virtual-reg: '%3' }2526 - { reg: '$d2', virtual-reg: '%4' }2527body: |2528 bb.0.entry:2529 liveins: $d0, $d1, $d22530 2531 ; CHECK-LABEL: name: test_rule991_id433_at_idx652112532 ; CHECK: liveins: $d0, $d1, $d22533 ; CHECK-NEXT: {{ $}}2534 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d22535 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d12536 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d02537 ; CHECK-NEXT: [[FNMADDDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMADDDrrr [[COPY2]], [[COPY1]], [[COPY]], implicit $fpcr2538 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMADDDrrr]]2539 %4:fpr(s64) = COPY $d22540 %3:fpr(s64) = COPY $d12541 %2:fpr(s64) = COPY $d02542 %0:fpr(s64) = G_FMA %2, %3, %42543 %1:fpr(s64) = G_FNEG %02544 $noreg = PATCHABLE_RET %1(s64)2545 2546...2547---2548name: test_rule993_id420_at_idx653752549alignment: 42550legalized: true2551regBankSelected: true2552tracksRegLiveness: true2553registers:2554 - { id: 0, class: fpr }2555 - { id: 1, class: fpr }2556 - { id: 2, class: fpr }2557 - { id: 3, class: fpr }2558liveins:2559 - { reg: '$s0', virtual-reg: '%2' }2560 - { reg: '$s1', virtual-reg: '%3' }2561body: |2562 bb.0.entry:2563 liveins: $s0, $s12564 2565 ; CHECK-LABEL: name: test_rule993_id420_at_idx653752566 ; CHECK: liveins: $s0, $s12567 ; CHECK-NEXT: {{ $}}2568 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s12569 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s02570 ; CHECK-NEXT: [[FNMULSrr:%[0-9]+]]:fpr32 = nofpexcept FNMULSrr [[COPY1]], [[COPY]], implicit $fpcr2571 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMULSrr]]2572 %3:fpr(s32) = COPY $s12573 %2:fpr(s32) = COPY $s02574 %0:fpr(s32) = G_FMUL %2, %32575 %1:fpr(s32) = G_FNEG %02576 $noreg = PATCHABLE_RET %1(s32)2577 2578...2579---2580name: test_rule994_id421_at_idx654512581alignment: 42582legalized: true2583regBankSelected: true2584tracksRegLiveness: true2585registers:2586 - { id: 0, class: fpr }2587 - { id: 1, class: fpr }2588 - { id: 2, class: fpr }2589 - { id: 3, class: fpr }2590liveins:2591 - { reg: '$d0', virtual-reg: '%2' }2592 - { reg: '$d1', virtual-reg: '%3' }2593body: |2594 bb.0.entry:2595 liveins: $d0, $d12596 2597 ; CHECK-LABEL: name: test_rule994_id421_at_idx654512598 ; CHECK: liveins: $d0, $d12599 ; CHECK-NEXT: {{ $}}2600 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d12601 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d02602 ; CHECK-NEXT: [[FNMULDrr:%[0-9]+]]:fpr64 = nofpexcept FNMULDrr [[COPY1]], [[COPY]], implicit $fpcr2603 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMULDrr]]2604 %3:fpr(s64) = COPY $d12605 %2:fpr(s64) = COPY $d02606 %0:fpr(s64) = G_FMUL %2, %32607 %1:fpr(s64) = G_FNEG %02608 $noreg = PATCHABLE_RET %1(s64)2609 2610...2611---2612name: test_rule1230_id2969_at_idx817842613alignment: 42614legalized: true2615regBankSelected: true2616tracksRegLiveness: true2617registers:2618 - { id: 0, class: gpr }2619 - { id: 1, class: gpr }2620liveins:2621 - { reg: '$x0', virtual-reg: '%0' }2622 - { reg: '$x1', virtual-reg: '%1' }2623body: |2624 bb.0.entry:2625 liveins: $x0, $x12626 2627 ; CHECK-LABEL: name: test_rule1230_id2969_at_idx817842628 ; CHECK: liveins: $x0, $x12629 ; CHECK-NEXT: {{ $}}2630 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x12631 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64all = COPY $x02632 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]]2633 ; CHECK-NEXT: ST1Onev8b [[COPY2]], [[COPY]] :: (store (<8 x s8>))2634 ; CHECK-NEXT: $noreg = PATCHABLE_RET2635 %1:gpr(p0) = COPY $x12636 %0:gpr(<8 x s8>) = COPY $x02637 G_STORE %0(<8 x s8>), %1(p0) :: (store (<8 x s8>))2638 $noreg = PATCHABLE_RET2639 2640...2641---2642name: test_rule1231_id2970_at_idx818162643alignment: 42644legalized: true2645regBankSelected: true2646tracksRegLiveness: true2647registers:2648 - { id: 0, class: gpr }2649 - { id: 1, class: gpr }2650liveins:2651 - { reg: '$x0', virtual-reg: '%0' }2652 - { reg: '$x1', virtual-reg: '%1' }2653body: |2654 bb.0.entry:2655 liveins: $x0, $x12656 2657 ; CHECK-LABEL: name: test_rule1231_id2970_at_idx818162658 ; CHECK: liveins: $x0, $x12659 ; CHECK-NEXT: {{ $}}2660 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x12661 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64all = COPY $x02662 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]]2663 ; CHECK-NEXT: ST1Onev4h [[COPY2]], [[COPY]] :: (store (<4 x s16>))2664 ; CHECK-NEXT: $noreg = PATCHABLE_RET2665 %1:gpr(p0) = COPY $x12666 %0:gpr(<4 x s16>) = COPY $x02667 G_STORE %0(<4 x s16>), %1(p0) :: (store (<4 x s16>))2668 $noreg = PATCHABLE_RET2669 2670...2671---2672name: test_rule1239_id894_at_idx822012673alignment: 42674legalized: true2675regBankSelected: true2676tracksRegLiveness: true2677registers:2678 - { id: 0, class: fpr }2679 - { id: 1, class: fpr }2680 - { id: 2, class: fpr }2681 - { id: 3, class: fpr }2682liveins:2683 - { reg: '$d0', virtual-reg: '%1' }2684 - { reg: '$d1', virtual-reg: '%2' }2685 - { reg: '$d2', virtual-reg: '%3' }2686body: |2687 bb.0.entry:2688 liveins: $d0, $d1, $d22689 2690 ; CHECK-LABEL: name: test_rule1239_id894_at_idx822012691 ; CHECK: liveins: $d0, $d1, $d22692 ; CHECK-NEXT: {{ $}}2693 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d22694 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d12695 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d02696 ; CHECK-NEXT: [[FMLAv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMLAv2f32 [[COPY]], [[COPY1]], [[COPY2]], implicit $fpcr2697 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLAv2f32_]]2698 %3:fpr(<2 x s32>) = COPY $d22699 %2:fpr(<2 x s32>) = COPY $d12700 %1:fpr(<2 x s32>) = COPY $d02701 %0:fpr(<2 x s32>) = G_FMA %1, %2, %32702 $noreg = PATCHABLE_RET %0(<2 x s32>)2703 2704...2705---2706name: test_rule1240_id895_at_idx822692707alignment: 42708legalized: true2709regBankSelected: true2710tracksRegLiveness: true2711registers:2712 - { id: 0, class: fpr }2713 - { id: 1, class: fpr }2714 - { id: 2, class: fpr }2715 - { id: 3, class: fpr }2716liveins:2717 - { reg: '$q0', virtual-reg: '%1' }2718 - { reg: '$q1', virtual-reg: '%2' }2719 - { reg: '$q2', virtual-reg: '%3' }2720body: |2721 bb.0.entry:2722 liveins: $q0, $q1, $q22723 2724 ; CHECK-LABEL: name: test_rule1240_id895_at_idx822692725 ; CHECK: liveins: $q0, $q1, $q22726 ; CHECK-NEXT: {{ $}}2727 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q22728 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q12729 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q02730 ; CHECK-NEXT: [[FMLAv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMLAv4f32 [[COPY]], [[COPY1]], [[COPY2]], implicit $fpcr2731 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLAv4f32_]]2732 %3:fpr(<4 x s32>) = COPY $q22733 %2:fpr(<4 x s32>) = COPY $q12734 %1:fpr(<4 x s32>) = COPY $q02735 %0:fpr(<4 x s32>) = G_FMA %1, %2, %32736 $noreg = PATCHABLE_RET %0(<4 x s32>)2737 2738...2739---2740name: test_rule1241_id896_at_idx823372741alignment: 42742legalized: true2743regBankSelected: true2744tracksRegLiveness: true2745registers:2746 - { id: 0, class: fpr }2747 - { id: 1, class: fpr }2748 - { id: 2, class: fpr }2749 - { id: 3, class: fpr }2750liveins:2751 - { reg: '$q0', virtual-reg: '%1' }2752 - { reg: '$q1', virtual-reg: '%2' }2753 - { reg: '$q2', virtual-reg: '%3' }2754body: |2755 bb.0.entry:2756 liveins: $q0, $q1, $q22757 2758 ; CHECK-LABEL: name: test_rule1241_id896_at_idx823372759 ; CHECK: liveins: $q0, $q1, $q22760 ; CHECK-NEXT: {{ $}}2761 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q22762 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q12763 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q02764 ; CHECK-NEXT: [[FMLAv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMLAv2f64 [[COPY]], [[COPY1]], [[COPY2]], implicit $fpcr2765 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLAv2f64_]]2766 %3:fpr(<2 x s64>) = COPY $q22767 %2:fpr(<2 x s64>) = COPY $q12768 %1:fpr(<2 x s64>) = COPY $q02769 %0:fpr(<2 x s64>) = G_FMA %1, %2, %32770 $noreg = PATCHABLE_RET %0(<2 x s64>)2771 2772...2773---2774name: test_rule1244_id751_at_idx824872775alignment: 42776legalized: true2777regBankSelected: true2778tracksRegLiveness: true2779registers:2780 - { id: 0, class: fpr }2781 - { id: 1, class: fpr }2782 - { id: 2, class: fpr }2783liveins:2784 - { reg: '$d0', virtual-reg: '%1' }2785 - { reg: '$d1', virtual-reg: '%2' }2786body: |2787 bb.0.entry:2788 liveins: $d0, $d12789 2790 ; CHECK-LABEL: name: test_rule1244_id751_at_idx824872791 ; CHECK: liveins: $d0, $d12792 ; CHECK-NEXT: {{ $}}2793 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d12794 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d02795 ; CHECK-NEXT: [[ADDv8i8_:%[0-9]+]]:fpr64 = ADDv8i8 [[COPY1]], [[COPY]]2796 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[ADDv8i8_]]2797 %2:fpr(<8 x s8>) = COPY $d12798 %1:fpr(<8 x s8>) = COPY $d02799 %0:fpr(<8 x s8>) = G_ADD %1, %22800 $noreg = PATCHABLE_RET %0(<8 x s8>)2801 2802...2803---2804name: test_rule1245_id752_at_idx825302805alignment: 42806legalized: true2807regBankSelected: true2808tracksRegLiveness: true2809registers:2810 - { id: 0, class: fpr }2811 - { id: 1, class: fpr }2812 - { id: 2, class: fpr }2813liveins:2814 - { reg: '$q0', virtual-reg: '%1' }2815 - { reg: '$q1', virtual-reg: '%2' }2816body: |2817 bb.0.entry:2818 liveins: $q0, $q12819 2820 ; CHECK-LABEL: name: test_rule1245_id752_at_idx825302821 ; CHECK: liveins: $q0, $q12822 ; CHECK-NEXT: {{ $}}2823 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q12824 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q02825 ; CHECK-NEXT: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[COPY1]], [[COPY]]2826 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[ADDv16i8_]]2827 %2:fpr(<16 x s8>) = COPY $q12828 %1:fpr(<16 x s8>) = COPY $q02829 %0:fpr(<16 x s8>) = G_ADD %1, %22830 $noreg = PATCHABLE_RET %0(<16 x s8>)2831 2832...2833---2834name: test_rule1246_id753_at_idx825732835alignment: 42836legalized: true2837regBankSelected: true2838tracksRegLiveness: true2839registers:2840 - { id: 0, class: fpr }2841 - { id: 1, class: fpr }2842 - { id: 2, class: fpr }2843liveins:2844 - { reg: '$d0', virtual-reg: '%1' }2845 - { reg: '$d1', virtual-reg: '%2' }2846body: |2847 bb.0.entry:2848 liveins: $d0, $d12849 2850 ; CHECK-LABEL: name: test_rule1246_id753_at_idx825732851 ; CHECK: liveins: $d0, $d12852 ; CHECK-NEXT: {{ $}}2853 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d12854 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d02855 ; CHECK-NEXT: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[COPY1]], [[COPY]]2856 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[ADDv4i16_]]2857 %2:fpr(<4 x s16>) = COPY $d12858 %1:fpr(<4 x s16>) = COPY $d02859 %0:fpr(<4 x s16>) = G_ADD %1, %22860 $noreg = PATCHABLE_RET %0(<4 x s16>)2861 2862...2863---2864name: test_rule1247_id754_at_idx826162865alignment: 42866legalized: true2867regBankSelected: true2868tracksRegLiveness: true2869registers:2870 - { id: 0, class: fpr }2871 - { id: 1, class: fpr }2872 - { id: 2, class: fpr }2873liveins:2874 - { reg: '$q0', virtual-reg: '%1' }2875 - { reg: '$q1', virtual-reg: '%2' }2876body: |2877 bb.0.entry:2878 liveins: $q0, $q12879 2880 ; CHECK-LABEL: name: test_rule1247_id754_at_idx826162881 ; CHECK: liveins: $q0, $q12882 ; CHECK-NEXT: {{ $}}2883 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q12884 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q02885 ; CHECK-NEXT: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[COPY1]], [[COPY]]2886 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[ADDv8i16_]]2887 %2:fpr(<8 x s16>) = COPY $q12888 %1:fpr(<8 x s16>) = COPY $q02889 %0:fpr(<8 x s16>) = G_ADD %1, %22890 $noreg = PATCHABLE_RET %0(<8 x s16>)2891 2892...2893---2894name: test_rule1254_id1162_at_idx829132895alignment: 42896legalized: true2897regBankSelected: true2898tracksRegLiveness: true2899registers:2900 - { id: 0, class: fpr }2901 - { id: 1, class: fpr }2902 - { id: 2, class: fpr }2903liveins:2904 - { reg: '$d0', virtual-reg: '%1' }2905 - { reg: '$d1', virtual-reg: '%2' }2906body: |2907 bb.0.entry:2908 liveins: $d0, $d12909 2910 ; CHECK-LABEL: name: test_rule1254_id1162_at_idx829132911 ; CHECK: liveins: $d0, $d12912 ; CHECK-NEXT: {{ $}}2913 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d12914 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d02915 ; CHECK-NEXT: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY]]2916 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[ANDv8i8_]]2917 %2:fpr(<8 x s8>) = COPY $d12918 %1:fpr(<8 x s8>) = COPY $d02919 %0:fpr(<8 x s8>) = G_AND %1, %22920 $noreg = PATCHABLE_RET %0(<8 x s8>)2921 2922...2923---2924name: test_rule1255_id1163_at_idx829562925alignment: 42926legalized: true2927regBankSelected: true2928tracksRegLiveness: true2929registers:2930 - { id: 0, class: fpr }2931 - { id: 1, class: fpr }2932 - { id: 2, class: fpr }2933liveins:2934 - { reg: '$q0', virtual-reg: '%1' }2935 - { reg: '$q1', virtual-reg: '%2' }2936body: |2937 bb.0.entry:2938 liveins: $q0, $q12939 2940 ; CHECK-LABEL: name: test_rule1255_id1163_at_idx829562941 ; CHECK: liveins: $q0, $q12942 ; CHECK-NEXT: {{ $}}2943 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q12944 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q02945 ; CHECK-NEXT: [[ANDv16i8_:%[0-9]+]]:fpr128 = ANDv16i8 [[COPY1]], [[COPY]]2946 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[ANDv16i8_]]2947 %2:fpr(<16 x s8>) = COPY $q12948 %1:fpr(<16 x s8>) = COPY $q02949 %0:fpr(<16 x s8>) = G_AND %1, %22950 $noreg = PATCHABLE_RET %0(<16 x s8>)2951 2952...2953---2954name: test_rule1256_id1751_at_idx829992955alignment: 42956legalized: true2957regBankSelected: true2958tracksRegLiveness: true2959registers:2960 - { id: 0, class: fpr }2961 - { id: 1, class: fpr }2962 - { id: 2, class: fpr }2963liveins:2964 - { reg: '$d0', virtual-reg: '%1' }2965 - { reg: '$d1', virtual-reg: '%2' }2966body: |2967 bb.0.entry:2968 liveins: $d0, $d12969 2970 ; CHECK-LABEL: name: test_rule1256_id1751_at_idx829992971 ; CHECK: liveins: $d0, $d12972 ; CHECK-NEXT: {{ $}}2973 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d12974 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d02975 ; CHECK-NEXT: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY]]2976 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[ANDv8i8_]]2977 %2:fpr(<4 x s16>) = COPY $d12978 %1:fpr(<4 x s16>) = COPY $d02979 %0:fpr(<4 x s16>) = G_AND %1, %22980 $noreg = PATCHABLE_RET %0(<4 x s16>)2981 2982...2983---2984name: test_rule1259_id1754_at_idx831282985alignment: 42986legalized: true2987regBankSelected: true2988tracksRegLiveness: true2989registers:2990 - { id: 0, class: fpr }2991 - { id: 1, class: fpr }2992 - { id: 2, class: fpr }2993liveins:2994 - { reg: '$q0', virtual-reg: '%1' }2995 - { reg: '$q1', virtual-reg: '%2' }2996body: |2997 bb.0.entry:2998 liveins: $q0, $q12999 3000 ; CHECK-LABEL: name: test_rule1259_id1754_at_idx831283001 ; CHECK: liveins: $q0, $q13002 ; CHECK-NEXT: {{ $}}3003 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q13004 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q03005 ; CHECK-NEXT: [[ANDv16i8_:%[0-9]+]]:fpr128 = ANDv16i8 [[COPY1]], [[COPY]]3006 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[ANDv16i8_]]3007 %2:fpr(<8 x s16>) = COPY $q13008 %1:fpr(<8 x s16>) = COPY $q03009 %0:fpr(<8 x s16>) = G_AND %1, %23010 $noreg = PATCHABLE_RET %0(<8 x s16>)3011 3012...3013---3014name: test_rule1268_id829_at_idx835133015alignment: 43016legalized: true3017regBankSelected: true3018tracksRegLiveness: true3019registers:3020 - { id: 0, class: fpr }3021 - { id: 1, class: fpr }3022 - { id: 2, class: fpr }3023liveins:3024 - { reg: '$d0', virtual-reg: '%1' }3025 - { reg: '$d1', virtual-reg: '%2' }3026body: |3027 bb.0.entry:3028 liveins: $d0, $d13029 3030 ; CHECK-LABEL: name: test_rule1268_id829_at_idx835133031 ; CHECK: liveins: $d0, $d13032 ; CHECK-NEXT: {{ $}}3033 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d13034 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d03035 ; CHECK-NEXT: [[FADDv2f32_:%[0-9]+]]:fpr64 = nofpexcept FADDv2f32 [[COPY1]], [[COPY]], implicit $fpcr3036 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FADDv2f32_]]3037 %2:fpr(<2 x s32>) = COPY $d13038 %1:fpr(<2 x s32>) = COPY $d03039 %0:fpr(<2 x s32>) = G_FADD %1, %23040 $noreg = PATCHABLE_RET %0(<2 x s32>)3041 3042...3043---3044name: test_rule1269_id830_at_idx835563045alignment: 43046legalized: true3047regBankSelected: true3048tracksRegLiveness: true3049registers:3050 - { id: 0, class: fpr }3051 - { id: 1, class: fpr }3052 - { id: 2, class: fpr }3053liveins:3054 - { reg: '$q0', virtual-reg: '%1' }3055 - { reg: '$q1', virtual-reg: '%2' }3056body: |3057 bb.0.entry:3058 liveins: $q0, $q13059 3060 ; CHECK-LABEL: name: test_rule1269_id830_at_idx835563061 ; CHECK: liveins: $q0, $q13062 ; CHECK-NEXT: {{ $}}3063 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q13064 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q03065 ; CHECK-NEXT: [[FADDv4f32_:%[0-9]+]]:fpr128 = nofpexcept FADDv4f32 [[COPY1]], [[COPY]], implicit $fpcr3066 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FADDv4f32_]]3067 %2:fpr(<4 x s32>) = COPY $q13068 %1:fpr(<4 x s32>) = COPY $q03069 %0:fpr(<4 x s32>) = G_FADD %1, %23070 $noreg = PATCHABLE_RET %0(<4 x s32>)3071 3072...3073---3074name: test_rule1270_id831_at_idx835993075alignment: 43076legalized: true3077regBankSelected: true3078tracksRegLiveness: true3079registers:3080 - { id: 0, class: fpr }3081 - { id: 1, class: fpr }3082 - { id: 2, class: fpr }3083liveins:3084 - { reg: '$q0', virtual-reg: '%1' }3085 - { reg: '$q1', virtual-reg: '%2' }3086body: |3087 bb.0.entry:3088 liveins: $q0, $q13089 3090 ; CHECK-LABEL: name: test_rule1270_id831_at_idx835993091 ; CHECK: liveins: $q0, $q13092 ; CHECK-NEXT: {{ $}}3093 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q13094 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q03095 ; CHECK-NEXT: [[FADDv2f64_:%[0-9]+]]:fpr128 = nofpexcept FADDv2f64 [[COPY1]], [[COPY]], implicit $fpcr3096 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FADDv2f64_]]3097 %2:fpr(<2 x s64>) = COPY $q13098 %1:fpr(<2 x s64>) = COPY $q03099 %0:fpr(<2 x s64>) = G_FADD %1, %23100 $noreg = PATCHABLE_RET %0(<2 x s64>)3101 3102...3103---3104name: test_rule1276_id849_at_idx838573105alignment: 43106legalized: true3107regBankSelected: true3108tracksRegLiveness: true3109registers:3110 - { id: 0, class: fpr }3111 - { id: 1, class: fpr }3112 - { id: 2, class: fpr }3113liveins:3114 - { reg: '$d0', virtual-reg: '%1' }3115 - { reg: '$d1', virtual-reg: '%2' }3116body: |3117 bb.0.entry:3118 liveins: $d0, $d13119 3120 ; CHECK-LABEL: name: test_rule1276_id849_at_idx838573121 ; CHECK: liveins: $d0, $d13122 ; CHECK-NEXT: {{ $}}3123 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d13124 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d03125 ; CHECK-NEXT: [[FDIVv2f32_:%[0-9]+]]:fpr64 = nofpexcept FDIVv2f32 [[COPY1]], [[COPY]], implicit $fpcr3126 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FDIVv2f32_]]3127 %2:fpr(<2 x s32>) = COPY $d13128 %1:fpr(<2 x s32>) = COPY $d03129 %0:fpr(<2 x s32>) = G_FDIV %1, %23130 $noreg = PATCHABLE_RET %0(<2 x s32>)3131 3132...3133---3134name: test_rule1277_id850_at_idx839003135alignment: 43136legalized: true3137regBankSelected: true3138tracksRegLiveness: true3139registers:3140 - { id: 0, class: fpr }3141 - { id: 1, class: fpr }3142 - { id: 2, class: fpr }3143liveins:3144 - { reg: '$q0', virtual-reg: '%1' }3145 - { reg: '$q1', virtual-reg: '%2' }3146body: |3147 bb.0.entry:3148 liveins: $q0, $q13149 3150 ; CHECK-LABEL: name: test_rule1277_id850_at_idx839003151 ; CHECK: liveins: $q0, $q13152 ; CHECK-NEXT: {{ $}}3153 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q13154 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q03155 ; CHECK-NEXT: [[FDIVv4f32_:%[0-9]+]]:fpr128 = nofpexcept FDIVv4f32 [[COPY1]], [[COPY]], implicit $fpcr3156 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FDIVv4f32_]]3157 %2:fpr(<4 x s32>) = COPY $q13158 %1:fpr(<4 x s32>) = COPY $q03159 %0:fpr(<4 x s32>) = G_FDIV %1, %23160 $noreg = PATCHABLE_RET %0(<4 x s32>)3161 3162...3163---3164name: test_rule1278_id851_at_idx839433165alignment: 43166legalized: true3167regBankSelected: true3168tracksRegLiveness: true3169registers:3170 - { id: 0, class: fpr }3171 - { id: 1, class: fpr }3172 - { id: 2, class: fpr }3173liveins:3174 - { reg: '$q0', virtual-reg: '%1' }3175 - { reg: '$q1', virtual-reg: '%2' }3176body: |3177 bb.0.entry:3178 liveins: $q0, $q13179 3180 ; CHECK-LABEL: name: test_rule1278_id851_at_idx839433181 ; CHECK: liveins: $q0, $q13182 ; CHECK-NEXT: {{ $}}3183 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q13184 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q03185 ; CHECK-NEXT: [[FDIVv2f64_:%[0-9]+]]:fpr128 = nofpexcept FDIVv2f64 [[COPY1]], [[COPY]], implicit $fpcr3186 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FDIVv2f64_]]3187 %2:fpr(<2 x s64>) = COPY $q13188 %1:fpr(<2 x s64>) = COPY $q03189 %0:fpr(<2 x s64>) = G_FDIV %1, %23190 $noreg = PATCHABLE_RET %0(<2 x s64>)3191 3192...3193---3194name: test_rule1284_id909_at_idx842013195alignment: 43196legalized: true3197regBankSelected: true3198tracksRegLiveness: true3199registers:3200 - { id: 0, class: fpr }3201 - { id: 1, class: fpr }3202 - { id: 2, class: fpr }3203liveins:3204 - { reg: '$d0', virtual-reg: '%1' }3205 - { reg: '$d1', virtual-reg: '%2' }3206body: |3207 bb.0.entry:3208 liveins: $d0, $d13209 3210 ; CHECK-LABEL: name: test_rule1284_id909_at_idx842013211 ; CHECK: liveins: $d0, $d13212 ; CHECK-NEXT: {{ $}}3213 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d13214 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d03215 ; CHECK-NEXT: [[FMULv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMULv2f32 [[COPY1]], [[COPY]], implicit $fpcr3216 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMULv2f32_]]3217 %2:fpr(<2 x s32>) = COPY $d13218 %1:fpr(<2 x s32>) = COPY $d03219 %0:fpr(<2 x s32>) = G_FMUL %1, %23220 $noreg = PATCHABLE_RET %0(<2 x s32>)3221 3222...3223---3224name: test_rule1285_id910_at_idx842443225alignment: 43226legalized: true3227regBankSelected: true3228tracksRegLiveness: true3229registers:3230 - { id: 0, class: fpr }3231 - { id: 1, class: fpr }3232 - { id: 2, class: fpr }3233liveins:3234 - { reg: '$q0', virtual-reg: '%1' }3235 - { reg: '$q1', virtual-reg: '%2' }3236body: |3237 bb.0.entry:3238 liveins: $q0, $q13239 3240 ; CHECK-LABEL: name: test_rule1285_id910_at_idx842443241 ; CHECK: liveins: $q0, $q13242 ; CHECK-NEXT: {{ $}}3243 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q13244 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q03245 ; CHECK-NEXT: [[FMULv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMULv4f32 [[COPY1]], [[COPY]], implicit $fpcr3246 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMULv4f32_]]3247 %2:fpr(<4 x s32>) = COPY $q13248 %1:fpr(<4 x s32>) = COPY $q03249 %0:fpr(<4 x s32>) = G_FMUL %1, %23250 $noreg = PATCHABLE_RET %0(<4 x s32>)3251 3252...3253---3254name: test_rule1286_id911_at_idx842873255alignment: 43256legalized: true3257regBankSelected: true3258tracksRegLiveness: true3259registers:3260 - { id: 0, class: fpr }3261 - { id: 1, class: fpr }3262 - { id: 2, class: fpr }3263liveins:3264 - { reg: '$q0', virtual-reg: '%1' }3265 - { reg: '$q1', virtual-reg: '%2' }3266body: |3267 bb.0.entry:3268 liveins: $q0, $q13269 3270 ; CHECK-LABEL: name: test_rule1286_id911_at_idx842873271 ; CHECK: liveins: $q0, $q13272 ; CHECK-NEXT: {{ $}}3273 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q13274 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q03275 ; CHECK-NEXT: [[FMULv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMULv2f64 [[COPY1]], [[COPY]], implicit $fpcr3276 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMULv2f64_]]3277 %2:fpr(<2 x s64>) = COPY $q13278 %1:fpr(<2 x s64>) = COPY $q03279 %0:fpr(<2 x s64>) = G_FMUL %1, %23280 $noreg = PATCHABLE_RET %0(<2 x s64>)3281 3282...3283---3284name: test_rule1292_id924_at_idx845453285alignment: 43286legalized: true3287regBankSelected: true3288tracksRegLiveness: true3289registers:3290 - { id: 0, class: fpr }3291 - { id: 1, class: fpr }3292 - { id: 2, class: fpr }3293liveins:3294 - { reg: '$d0', virtual-reg: '%1' }3295 - { reg: '$d1', virtual-reg: '%2' }3296body: |3297 bb.0.entry:3298 liveins: $d0, $d13299 3300 ; CHECK-LABEL: name: test_rule1292_id924_at_idx845453301 ; CHECK: liveins: $d0, $d13302 ; CHECK-NEXT: {{ $}}3303 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d13304 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d03305 ; CHECK-NEXT: [[FSUBv2f32_:%[0-9]+]]:fpr64 = nofpexcept FSUBv2f32 [[COPY1]], [[COPY]], implicit $fpcr3306 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FSUBv2f32_]]3307 %2:fpr(<2 x s32>) = COPY $d13308 %1:fpr(<2 x s32>) = COPY $d03309 %0:fpr(<2 x s32>) = G_FSUB %1, %23310 $noreg = PATCHABLE_RET %0(<2 x s32>)3311 3312...3313---3314name: test_rule1293_id925_at_idx845883315alignment: 43316legalized: true3317regBankSelected: true3318tracksRegLiveness: true3319registers:3320 - { id: 0, class: fpr }3321 - { id: 1, class: fpr }3322 - { id: 2, class: fpr }3323liveins:3324 - { reg: '$q0', virtual-reg: '%1' }3325 - { reg: '$q1', virtual-reg: '%2' }3326body: |3327 bb.0.entry:3328 liveins: $q0, $q13329 3330 ; CHECK-LABEL: name: test_rule1293_id925_at_idx845883331 ; CHECK: liveins: $q0, $q13332 ; CHECK-NEXT: {{ $}}3333 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q13334 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q03335 ; CHECK-NEXT: [[FSUBv4f32_:%[0-9]+]]:fpr128 = nofpexcept FSUBv4f32 [[COPY1]], [[COPY]], implicit $fpcr3336 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FSUBv4f32_]]3337 %2:fpr(<4 x s32>) = COPY $q13338 %1:fpr(<4 x s32>) = COPY $q03339 %0:fpr(<4 x s32>) = G_FSUB %1, %23340 $noreg = PATCHABLE_RET %0(<4 x s32>)3341 3342...3343---3344name: test_rule1294_id926_at_idx846313345alignment: 43346legalized: true3347regBankSelected: true3348tracksRegLiveness: true3349registers:3350 - { id: 0, class: fpr }3351 - { id: 1, class: fpr }3352 - { id: 2, class: fpr }3353liveins:3354 - { reg: '$q0', virtual-reg: '%1' }3355 - { reg: '$q1', virtual-reg: '%2' }3356body: |3357 bb.0.entry:3358 liveins: $q0, $q13359 3360 ; CHECK-LABEL: name: test_rule1294_id926_at_idx846313361 ; CHECK: liveins: $q0, $q13362 ; CHECK-NEXT: {{ $}}3363 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q13364 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q03365 ; CHECK-NEXT: [[FSUBv2f64_:%[0-9]+]]:fpr128 = nofpexcept FSUBv2f64 [[COPY1]], [[COPY]], implicit $fpcr3366 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FSUBv2f64_]]3367 %2:fpr(<2 x s64>) = COPY $q13368 %1:fpr(<2 x s64>) = COPY $q03369 %0:fpr(<2 x s64>) = G_FSUB %1, %23370 $noreg = PATCHABLE_RET %0(<2 x s64>)3371 3372...3373---3374name: test_rule1296_id939_at_idx847153375alignment: 43376legalized: true3377regBankSelected: true3378tracksRegLiveness: true3379registers:3380 - { id: 0, class: fpr }3381 - { id: 1, class: fpr }3382 - { id: 2, class: fpr }3383liveins:3384 - { reg: '$d0', virtual-reg: '%1' }3385 - { reg: '$d1', virtual-reg: '%2' }3386body: |3387 bb.0.entry:3388 liveins: $d0, $d13389 3390 ; CHECK-LABEL: name: test_rule1296_id939_at_idx847153391 ; CHECK: liveins: $d0, $d13392 ; CHECK-NEXT: {{ $}}3393 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d13394 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d03395 ; CHECK-NEXT: [[MULv8i8_:%[0-9]+]]:fpr64 = MULv8i8 [[COPY1]], [[COPY]]3396 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[MULv8i8_]]3397 %2:fpr(<8 x s8>) = COPY $d13398 %1:fpr(<8 x s8>) = COPY $d03399 %0:fpr(<8 x s8>) = G_MUL %1, %23400 $noreg = PATCHABLE_RET %0(<8 x s8>)3401 3402...3403---3404name: test_rule1297_id940_at_idx847583405alignment: 43406legalized: true3407regBankSelected: true3408tracksRegLiveness: true3409registers:3410 - { id: 0, class: fpr }3411 - { id: 1, class: fpr }3412 - { id: 2, class: fpr }3413liveins:3414 - { reg: '$q0', virtual-reg: '%1' }3415 - { reg: '$q1', virtual-reg: '%2' }3416body: |3417 bb.0.entry:3418 liveins: $q0, $q13419 3420 ; CHECK-LABEL: name: test_rule1297_id940_at_idx847583421 ; CHECK: liveins: $q0, $q13422 ; CHECK-NEXT: {{ $}}3423 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q13424 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q03425 ; CHECK-NEXT: [[MULv16i8_:%[0-9]+]]:fpr128 = MULv16i8 [[COPY1]], [[COPY]]3426 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[MULv16i8_]]3427 %2:fpr(<16 x s8>) = COPY $q13428 %1:fpr(<16 x s8>) = COPY $q03429 %0:fpr(<16 x s8>) = G_MUL %1, %23430 $noreg = PATCHABLE_RET %0(<16 x s8>)3431 3432...3433---3434name: test_rule1298_id941_at_idx848013435alignment: 43436legalized: true3437regBankSelected: true3438tracksRegLiveness: true3439registers:3440 - { id: 0, class: fpr }3441 - { id: 1, class: fpr }3442 - { id: 2, class: fpr }3443liveins:3444 - { reg: '$d0', virtual-reg: '%1' }3445 - { reg: '$d1', virtual-reg: '%2' }3446body: |3447 bb.0.entry:3448 liveins: $d0, $d13449 3450 ; CHECK-LABEL: name: test_rule1298_id941_at_idx848013451 ; CHECK: liveins: $d0, $d13452 ; CHECK-NEXT: {{ $}}3453 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d13454 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d03455 ; CHECK-NEXT: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY1]], [[COPY]]3456 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[MULv4i16_]]3457 %2:fpr(<4 x s16>) = COPY $d13458 %1:fpr(<4 x s16>) = COPY $d03459 %0:fpr(<4 x s16>) = G_MUL %1, %23460 $noreg = PATCHABLE_RET %0(<4 x s16>)3461 3462...3463---3464name: test_rule1299_id942_at_idx848443465alignment: 43466legalized: true3467regBankSelected: true3468tracksRegLiveness: true3469registers:3470 - { id: 0, class: fpr }3471 - { id: 1, class: fpr }3472 - { id: 2, class: fpr }3473liveins:3474 - { reg: '$q0', virtual-reg: '%1' }3475 - { reg: '$q1', virtual-reg: '%2' }3476body: |3477 bb.0.entry:3478 liveins: $q0, $q13479 3480 ; CHECK-LABEL: name: test_rule1299_id942_at_idx848443481 ; CHECK: liveins: $q0, $q13482 ; CHECK-NEXT: {{ $}}3483 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q13484 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q03485 ; CHECK-NEXT: [[MULv8i16_:%[0-9]+]]:fpr128 = MULv8i16 [[COPY1]], [[COPY]]3486 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[MULv8i16_]]3487 %2:fpr(<8 x s16>) = COPY $q13488 %1:fpr(<8 x s16>) = COPY $q03489 %0:fpr(<8 x s16>) = G_MUL %1, %23490 $noreg = PATCHABLE_RET %0(<8 x s16>)3491 3492...3493---3494name: test_rule1304_id1174_at_idx850553495alignment: 43496legalized: true3497regBankSelected: true3498tracksRegLiveness: true3499registers:3500 - { id: 0, class: fpr }3501 - { id: 1, class: fpr }3502 - { id: 2, class: fpr }3503liveins:3504 - { reg: '$d0', virtual-reg: '%1' }3505 - { reg: '$d1', virtual-reg: '%2' }3506body: |3507 bb.0.entry:3508 liveins: $d0, $d13509 3510 ; CHECK-LABEL: name: test_rule1304_id1174_at_idx850553511 ; CHECK: liveins: $d0, $d13512 ; CHECK-NEXT: {{ $}}3513 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d13514 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d03515 ; CHECK-NEXT: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY1]], [[COPY]]3516 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[ORRv8i8_]]3517 %2:fpr(<8 x s8>) = COPY $d13518 %1:fpr(<8 x s8>) = COPY $d03519 %0:fpr(<8 x s8>) = G_OR %1, %23520 $noreg = PATCHABLE_RET %0(<8 x s8>)3521 3522...3523---3524name: test_rule1305_id1175_at_idx850983525alignment: 43526legalized: true3527regBankSelected: true3528tracksRegLiveness: true3529registers:3530 - { id: 0, class: fpr }3531 - { id: 1, class: fpr }3532 - { id: 2, class: fpr }3533liveins:3534 - { reg: '$q0', virtual-reg: '%1' }3535 - { reg: '$q1', virtual-reg: '%2' }3536body: |3537 bb.0.entry:3538 liveins: $q0, $q13539 3540 ; CHECK-LABEL: name: test_rule1305_id1175_at_idx850983541 ; CHECK: liveins: $q0, $q13542 ; CHECK-NEXT: {{ $}}3543 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q13544 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q03545 ; CHECK-NEXT: [[ORRv16i8_:%[0-9]+]]:fpr128 = ORRv16i8 [[COPY1]], [[COPY]]3546 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[ORRv16i8_]]3547 %2:fpr(<16 x s8>) = COPY $q13548 %1:fpr(<16 x s8>) = COPY $q03549 %0:fpr(<16 x s8>) = G_OR %1, %23550 $noreg = PATCHABLE_RET %0(<16 x s8>)3551 3552...3553---3554name: test_rule1306_id1827_at_idx851413555alignment: 43556legalized: true3557regBankSelected: true3558tracksRegLiveness: true3559registers:3560 - { id: 0, class: fpr }3561 - { id: 1, class: fpr }3562 - { id: 2, class: fpr }3563liveins:3564 - { reg: '$d0', virtual-reg: '%1' }3565 - { reg: '$d1', virtual-reg: '%2' }3566body: |3567 bb.0.entry:3568 liveins: $d0, $d13569 3570 ; CHECK-LABEL: name: test_rule1306_id1827_at_idx851413571 ; CHECK: liveins: $d0, $d13572 ; CHECK-NEXT: {{ $}}3573 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d13574 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d03575 ; CHECK-NEXT: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY1]], [[COPY]]3576 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[ORRv8i8_]]3577 %2:fpr(<4 x s16>) = COPY $d13578 %1:fpr(<4 x s16>) = COPY $d03579 %0:fpr(<4 x s16>) = G_OR %1, %23580 $noreg = PATCHABLE_RET %0(<4 x s16>)3581 3582...3583---3584name: test_rule1309_id1830_at_idx852703585alignment: 43586legalized: true3587regBankSelected: true3588tracksRegLiveness: true3589registers:3590 - { id: 0, class: fpr }3591 - { id: 1, class: fpr }3592 - { id: 2, class: fpr }3593liveins:3594 - { reg: '$q0', virtual-reg: '%1' }3595 - { reg: '$q1', virtual-reg: '%2' }3596body: |3597 bb.0.entry:3598 liveins: $q0, $q13599 3600 ; CHECK-LABEL: name: test_rule1309_id1830_at_idx852703601 ; CHECK: liveins: $q0, $q13602 ; CHECK-NEXT: {{ $}}3603 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q13604 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q03605 ; CHECK-NEXT: [[ORRv16i8_:%[0-9]+]]:fpr128 = ORRv16i8 [[COPY1]], [[COPY]]3606 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[ORRv16i8_]]3607 %2:fpr(<8 x s16>) = COPY $q13608 %1:fpr(<8 x s16>) = COPY $q03609 %0:fpr(<8 x s16>) = G_OR %1, %23610 $noreg = PATCHABLE_RET %0(<8 x s16>)3611 3612...3613---3614name: test_rule1315_id1051_at_idx855223615alignment: 43616legalized: true3617regBankSelected: true3618tracksRegLiveness: true3619registers:3620 - { id: 0, class: fpr }3621 - { id: 1, class: fpr }3622 - { id: 2, class: fpr }3623liveins:3624 - { reg: '$d0', virtual-reg: '%1' }3625 - { reg: '$d1', virtual-reg: '%2' }3626body: |3627 bb.0.entry:3628 liveins: $d0, $d13629 3630 ; CHECK-LABEL: name: test_rule1315_id1051_at_idx855223631 ; CHECK: liveins: $d0, $d13632 ; CHECK-NEXT: {{ $}}3633 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d13634 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d03635 ; CHECK-NEXT: [[SUBv8i8_:%[0-9]+]]:fpr64 = SUBv8i8 [[COPY1]], [[COPY]]3636 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SUBv8i8_]]3637 %2:fpr(<8 x s8>) = COPY $d13638 %1:fpr(<8 x s8>) = COPY $d03639 %0:fpr(<8 x s8>) = G_SUB %1, %23640 $noreg = PATCHABLE_RET %0(<8 x s8>)3641 3642...3643---3644name: test_rule1316_id1052_at_idx855653645alignment: 43646legalized: true3647regBankSelected: true3648tracksRegLiveness: true3649registers:3650 - { id: 0, class: fpr }3651 - { id: 1, class: fpr }3652 - { id: 2, class: fpr }3653liveins:3654 - { reg: '$q0', virtual-reg: '%1' }3655 - { reg: '$q1', virtual-reg: '%2' }3656body: |3657 bb.0.entry:3658 liveins: $q0, $q13659 3660 ; CHECK-LABEL: name: test_rule1316_id1052_at_idx855653661 ; CHECK: liveins: $q0, $q13662 ; CHECK-NEXT: {{ $}}3663 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q13664 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q03665 ; CHECK-NEXT: [[SUBv16i8_:%[0-9]+]]:fpr128 = SUBv16i8 [[COPY1]], [[COPY]]3666 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SUBv16i8_]]3667 %2:fpr(<16 x s8>) = COPY $q13668 %1:fpr(<16 x s8>) = COPY $q03669 %0:fpr(<16 x s8>) = G_SUB %1, %23670 $noreg = PATCHABLE_RET %0(<16 x s8>)3671 3672...3673---3674name: test_rule1317_id1053_at_idx856083675alignment: 43676legalized: true3677regBankSelected: true3678tracksRegLiveness: true3679registers:3680 - { id: 0, class: fpr }3681 - { id: 1, class: fpr }3682 - { id: 2, class: fpr }3683liveins:3684 - { reg: '$d0', virtual-reg: '%1' }3685 - { reg: '$d1', virtual-reg: '%2' }3686body: |3687 bb.0.entry:3688 liveins: $d0, $d13689 3690 ; CHECK-LABEL: name: test_rule1317_id1053_at_idx856083691 ; CHECK: liveins: $d0, $d13692 ; CHECK-NEXT: {{ $}}3693 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d13694 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d03695 ; CHECK-NEXT: [[SUBv4i16_:%[0-9]+]]:fpr64 = SUBv4i16 [[COPY1]], [[COPY]]3696 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SUBv4i16_]]3697 %2:fpr(<4 x s16>) = COPY $d13698 %1:fpr(<4 x s16>) = COPY $d03699 %0:fpr(<4 x s16>) = G_SUB %1, %23700 $noreg = PATCHABLE_RET %0(<4 x s16>)3701 3702...3703---3704name: test_rule1318_id1054_at_idx856513705alignment: 43706legalized: true3707regBankSelected: true3708tracksRegLiveness: true3709registers:3710 - { id: 0, class: fpr }3711 - { id: 1, class: fpr }3712 - { id: 2, class: fpr }3713liveins:3714 - { reg: '$q0', virtual-reg: '%1' }3715 - { reg: '$q1', virtual-reg: '%2' }3716body: |3717 bb.0.entry:3718 liveins: $q0, $q13719 3720 ; CHECK-LABEL: name: test_rule1318_id1054_at_idx856513721 ; CHECK: liveins: $q0, $q13722 ; CHECK-NEXT: {{ $}}3723 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q13724 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q03725 ; CHECK-NEXT: [[SUBv8i16_:%[0-9]+]]:fpr128 = SUBv8i16 [[COPY1]], [[COPY]]3726 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SUBv8i16_]]3727 %2:fpr(<8 x s16>) = COPY $q13728 %1:fpr(<8 x s16>) = COPY $q03729 %0:fpr(<8 x s16>) = G_SUB %1, %23730 $noreg = PATCHABLE_RET %0(<8 x s16>)3731 3732...3733---3734name: test_rule1329_id1170_at_idx861183735alignment: 43736legalized: true3737regBankSelected: true3738tracksRegLiveness: true3739registers:3740 - { id: 0, class: fpr }3741 - { id: 1, class: fpr }3742 - { id: 2, class: fpr }3743liveins:3744 - { reg: '$d0', virtual-reg: '%1' }3745 - { reg: '$d1', virtual-reg: '%2' }3746body: |3747 bb.0.entry:3748 liveins: $d0, $d13749 3750 ; CHECK-LABEL: name: test_rule1329_id1170_at_idx861183751 ; CHECK: liveins: $d0, $d13752 ; CHECK-NEXT: {{ $}}3753 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d13754 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d03755 ; CHECK-NEXT: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY1]], [[COPY]]3756 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[EORv8i8_]]3757 %2:fpr(<8 x s8>) = COPY $d13758 %1:fpr(<8 x s8>) = COPY $d03759 %0:fpr(<8 x s8>) = G_XOR %1, %23760 $noreg = PATCHABLE_RET %0(<8 x s8>)3761 3762...3763---3764name: test_rule1330_id1171_at_idx861613765alignment: 43766legalized: true3767regBankSelected: true3768tracksRegLiveness: true3769registers:3770 - { id: 0, class: fpr }3771 - { id: 1, class: fpr }3772 - { id: 2, class: fpr }3773liveins:3774 - { reg: '$q0', virtual-reg: '%1' }3775 - { reg: '$q1', virtual-reg: '%2' }3776body: |3777 bb.0.entry:3778 liveins: $q0, $q13779 3780 ; CHECK-LABEL: name: test_rule1330_id1171_at_idx861613781 ; CHECK: liveins: $q0, $q13782 ; CHECK-NEXT: {{ $}}3783 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q13784 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q03785 ; CHECK-NEXT: [[EORv16i8_:%[0-9]+]]:fpr128 = EORv16i8 [[COPY1]], [[COPY]]3786 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[EORv16i8_]]3787 %2:fpr(<16 x s8>) = COPY $q13788 %1:fpr(<16 x s8>) = COPY $q03789 %0:fpr(<16 x s8>) = G_XOR %1, %23790 $noreg = PATCHABLE_RET %0(<16 x s8>)3791 3792...3793---3794name: test_rule1331_id1791_at_idx862043795alignment: 43796legalized: true3797regBankSelected: true3798tracksRegLiveness: true3799registers:3800 - { id: 0, class: fpr }3801 - { id: 1, class: fpr }3802 - { id: 2, class: fpr }3803liveins:3804 - { reg: '$d0', virtual-reg: '%1' }3805 - { reg: '$d1', virtual-reg: '%2' }3806body: |3807 bb.0.entry:3808 liveins: $d0, $d13809 3810 ; CHECK-LABEL: name: test_rule1331_id1791_at_idx862043811 ; CHECK: liveins: $d0, $d13812 ; CHECK-NEXT: {{ $}}3813 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d13814 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d03815 ; CHECK-NEXT: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY1]], [[COPY]]3816 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[EORv8i8_]]3817 %2:fpr(<4 x s16>) = COPY $d13818 %1:fpr(<4 x s16>) = COPY $d03819 %0:fpr(<4 x s16>) = G_XOR %1, %23820 $noreg = PATCHABLE_RET %0(<4 x s16>)3821 3822...3823---3824name: test_rule1334_id1794_at_idx863333825alignment: 43826legalized: true3827regBankSelected: true3828tracksRegLiveness: true3829registers:3830 - { id: 0, class: fpr }3831 - { id: 1, class: fpr }3832 - { id: 2, class: fpr }3833liveins:3834 - { reg: '$q0', virtual-reg: '%1' }3835 - { reg: '$q1', virtual-reg: '%2' }3836body: |3837 bb.0.entry:3838 liveins: $q0, $q13839 3840 ; CHECK-LABEL: name: test_rule1334_id1794_at_idx863333841 ; CHECK: liveins: $q0, $q13842 ; CHECK-NEXT: {{ $}}3843 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q13844 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q03845 ; CHECK-NEXT: [[EORv16i8_:%[0-9]+]]:fpr128 = EORv16i8 [[COPY1]], [[COPY]]3846 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[EORv16i8_]]3847 %2:fpr(<8 x s16>) = COPY $q13848 %1:fpr(<8 x s16>) = COPY $q03849 %0:fpr(<8 x s16>) = G_XOR %1, %23850 $noreg = PATCHABLE_RET %0(<8 x s16>)3851 3852...3853---3854name: test_rule1337_id2925_at_idx864623855alignment: 43856legalized: true3857regBankSelected: true3858tracksRegLiveness: true3859registers:3860 - { id: 0, class: fpr }3861 - { id: 1, class: fpr }3862liveins:3863 - { reg: '$d0', virtual-reg: '%1' }3864body: |3865 bb.0.entry:3866 liveins: $d03867 3868 ; CHECK-LABEL: name: test_rule1337_id2925_at_idx864623869 ; CHECK: liveins: $d03870 ; CHECK-NEXT: {{ $}}3871 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d03872 ; CHECK-NEXT: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 03873 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[USHLLv8i8_shift]]3874 %1:fpr(<8 x s8>) = COPY $d03875 %0:fpr(<8 x s16>) = G_ANYEXT %1(<8 x s8>)3876 $noreg = PATCHABLE_RET %0(<8 x s16>)3877 3878...3879---3880name: test_rule1338_id2928_at_idx865073881alignment: 43882legalized: true3883regBankSelected: true3884tracksRegLiveness: true3885registers:3886 - { id: 0, class: fpr }3887 - { id: 1, class: fpr }3888liveins:3889 - { reg: '$d0', virtual-reg: '%1' }3890body: |3891 bb.0.entry:3892 liveins: $d03893 3894 ; CHECK-LABEL: name: test_rule1338_id2928_at_idx865073895 ; CHECK: liveins: $d03896 ; CHECK-NEXT: {{ $}}3897 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d03898 ; CHECK-NEXT: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 03899 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[USHLLv4i16_shift]]3900 %1:fpr(<4 x s16>) = COPY $d03901 %0:fpr(<4 x s32>) = G_ANYEXT %1(<4 x s16>)3902 $noreg = PATCHABLE_RET %0(<4 x s32>)3903 3904...3905---3906name: test_rule1339_id2931_at_idx865523907alignment: 43908legalized: true3909regBankSelected: true3910tracksRegLiveness: true3911registers:3912 - { id: 0, class: fpr }3913 - { id: 1, class: fpr }3914liveins:3915 - { reg: '$d0', virtual-reg: '%1' }3916body: |3917 bb.0.entry:3918 liveins: $d03919 3920 ; CHECK-LABEL: name: test_rule1339_id2931_at_idx865523921 ; CHECK: liveins: $d03922 ; CHECK-NEXT: {{ $}}3923 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d03924 ; CHECK-NEXT: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 03925 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[USHLLv2i32_shift]]3926 %1:fpr(<2 x s32>) = COPY $d03927 %0:fpr(<2 x s64>) = G_ANYEXT %1(<2 x s32>)3928 $noreg = PATCHABLE_RET %0(<2 x s64>)3929 3930...3931---3932name: test_rule1582_id372_at_idx970753933alignment: 43934legalized: true3935regBankSelected: true3936tracksRegLiveness: true3937registers:3938 - { id: 0, class: fpr }3939 - { id: 1, class: fpr }3940liveins:3941 - { reg: '$s0', virtual-reg: '%1' }3942body: |3943 bb.0.entry:3944 liveins: $s03945 3946 ; CHECK-LABEL: name: test_rule1582_id372_at_idx970753947 ; CHECK: liveins: $s03948 ; CHECK-NEXT: {{ $}}3949 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s03950 ; CHECK-NEXT: [[FNEGSr:%[0-9]+]]:fpr32 = FNEGSr [[COPY]]3951 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNEGSr]]3952 %1:fpr(s32) = COPY $s03953 %0:fpr(s32) = G_FNEG %13954 $noreg = PATCHABLE_RET %0(s32)3955 3956...3957---3958name: test_rule1583_id373_at_idx971103959alignment: 43960legalized: true3961regBankSelected: true3962tracksRegLiveness: true3963registers:3964 - { id: 0, class: fpr }3965 - { id: 1, class: fpr }3966liveins:3967 - { reg: '$d0', virtual-reg: '%1' }3968body: |3969 bb.0.entry:3970 liveins: $d03971 3972 ; CHECK-LABEL: name: test_rule1583_id373_at_idx971103973 ; CHECK: liveins: $d03974 ; CHECK-NEXT: {{ $}}3975 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d03976 ; CHECK-NEXT: [[FNEGDr:%[0-9]+]]:fpr64 = FNEGDr [[COPY]]3977 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNEGDr]]3978 %1:fpr(s64) = COPY $d03979 %0:fpr(s64) = G_FNEG %13980 $noreg = PATCHABLE_RET %0(s64)3981 3982...3983---3984name: test_rule1586_id597_at_idx972153985alignment: 43986legalized: true3987regBankSelected: true3988tracksRegLiveness: true3989registers:3990 - { id: 0, class: fpr }3991 - { id: 1, class: fpr }3992liveins:3993 - { reg: '$d0', virtual-reg: '%1' }3994body: |3995 bb.0.entry:3996 liveins: $d03997 3998 ; CHECK-LABEL: name: test_rule1586_id597_at_idx972153999 ; CHECK: liveins: $d04000 ; CHECK-NEXT: {{ $}}4001 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d04002 ; CHECK-NEXT: [[FNEGv2f32_:%[0-9]+]]:fpr64 = FNEGv2f32 [[COPY]]4003 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNEGv2f32_]]4004 %1:fpr(<2 x s32>) = COPY $d04005 %0:fpr(<2 x s32>) = G_FNEG %14006 $noreg = PATCHABLE_RET %0(<2 x s32>)4007 4008...4009---4010name: test_rule1587_id598_at_idx972504011alignment: 44012legalized: true4013regBankSelected: true4014tracksRegLiveness: true4015registers:4016 - { id: 0, class: fpr }4017 - { id: 1, class: fpr }4018liveins:4019 - { reg: '$q0', virtual-reg: '%1' }4020body: |4021 bb.0.entry:4022 liveins: $q04023 4024 ; CHECK-LABEL: name: test_rule1587_id598_at_idx972504025 ; CHECK: liveins: $q04026 ; CHECK-NEXT: {{ $}}4027 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q04028 ; CHECK-NEXT: [[FNEGv4f32_:%[0-9]+]]:fpr128 = FNEGv4f32 [[COPY]]4029 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNEGv4f32_]]4030 %1:fpr(<4 x s32>) = COPY $q04031 %0:fpr(<4 x s32>) = G_FNEG %14032 $noreg = PATCHABLE_RET %0(<4 x s32>)4033 4034...4035---4036name: test_rule1588_id599_at_idx972854037alignment: 44038legalized: true4039regBankSelected: true4040tracksRegLiveness: true4041registers:4042 - { id: 0, class: fpr }4043 - { id: 1, class: fpr }4044liveins:4045 - { reg: '$q0', virtual-reg: '%1' }4046body: |4047 bb.0.entry:4048 liveins: $q04049 4050 ; CHECK-LABEL: name: test_rule1588_id599_at_idx972854051 ; CHECK: liveins: $q04052 ; CHECK-NEXT: {{ $}}4053 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q04054 ; CHECK-NEXT: [[FNEGv2f64_:%[0-9]+]]:fpr128 = FNEGv2f64 [[COPY]]4055 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNEGv2f64_]]4056 %1:fpr(<2 x s64>) = COPY $q04057 %0:fpr(<2 x s64>) = G_FNEG %14058 $noreg = PATCHABLE_RET %0(<2 x s64>)4059 4060...4061---4062name: test_rule1592_id2383_at_idx974254063alignment: 44064legalized: true4065regBankSelected: true4066tracksRegLiveness: true4067registers:4068 - { id: 0, class: fpr }4069 - { id: 1, class: fpr }4070liveins:4071 - { reg: '$d0', virtual-reg: '%1' }4072body: |4073 bb.0.entry:4074 liveins: $d04075 4076 ; CHECK-LABEL: name: test_rule1592_id2383_at_idx974254077 ; CHECK: liveins: $d04078 ; CHECK-NEXT: {{ $}}4079 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d04080 ; CHECK-NEXT: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv2i32 [[COPY]], implicit $fpcr4081 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTLv2i32_]]4082 %1:fpr(<2 x s32>) = COPY $d04083 %0:fpr(<2 x s64>) = G_FPEXT %1(<2 x s32>)4084 $noreg = PATCHABLE_RET %0(<2 x s64>)4085 4086...4087---4088name: test_rule1593_id2385_at_idx974584089alignment: 44090legalized: true4091regBankSelected: true4092tracksRegLiveness: true4093registers:4094 - { id: 0, class: fpr }4095 - { id: 1, class: fpr }4096liveins:4097 - { reg: '$d0', virtual-reg: '%1' }4098body: |4099 bb.0.entry:4100 liveins: $d04101 4102 ; CHECK-LABEL: name: test_rule1593_id2385_at_idx974584103 ; CHECK: liveins: $d04104 ; CHECK-NEXT: {{ $}}4105 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d04106 ; CHECK-NEXT: [[FCVTLv4i16_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv4i16 [[COPY]], implicit $fpcr4107 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTLv4i16_]]4108 %1:fpr(<4 x s16>) = COPY $d04109 %0:fpr(<4 x s32>) = G_FPEXT %1(<4 x s16>)4110 $noreg = PATCHABLE_RET %0(<4 x s32>)4111 4112...4113---4114name: test_rule1602_id587_at_idx977714115alignment: 44116legalized: true4117regBankSelected: true4118tracksRegLiveness: true4119registers:4120 - { id: 0, class: fpr }4121 - { id: 1, class: fpr }4122liveins:4123 - { reg: '$d0', virtual-reg: '%1' }4124body: |4125 bb.0.entry:4126 liveins: $d04127 4128 ; CHECK-LABEL: name: test_rule1602_id587_at_idx977714129 ; CHECK: liveins: $d04130 ; CHECK-NEXT: {{ $}}4131 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d04132 ; CHECK-NEXT: [[FCVTZSv2f32_:%[0-9]+]]:fpr64 = nofpexcept FCVTZSv2f32 [[COPY]], implicit $fpcr4133 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTZSv2f32_]]4134 %1:fpr(<2 x s32>) = COPY $d04135 %0:fpr(<2 x s32>) = G_FPTOSI %1(<2 x s32>)4136 $noreg = PATCHABLE_RET %0(<2 x s32>)4137 4138...4139---4140name: test_rule1603_id588_at_idx978064141alignment: 44142legalized: true4143regBankSelected: true4144tracksRegLiveness: true4145registers:4146 - { id: 0, class: fpr }4147 - { id: 1, class: fpr }4148liveins:4149 - { reg: '$q0', virtual-reg: '%1' }4150body: |4151 bb.0.entry:4152 liveins: $q04153 4154 ; CHECK-LABEL: name: test_rule1603_id588_at_idx978064155 ; CHECK: liveins: $q04156 ; CHECK-NEXT: {{ $}}4157 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q04158 ; CHECK-NEXT: [[FCVTZSv4f32_:%[0-9]+]]:fpr128 = nofpexcept FCVTZSv4f32 [[COPY]], implicit $fpcr4159 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTZSv4f32_]]4160 %1:fpr(<4 x s32>) = COPY $q04161 %0:fpr(<4 x s32>) = G_FPTOSI %1(<4 x s32>)4162 $noreg = PATCHABLE_RET %0(<4 x s32>)4163 4164...4165---4166name: test_rule1604_id589_at_idx978414167alignment: 44168legalized: true4169regBankSelected: true4170tracksRegLiveness: true4171registers:4172 - { id: 0, class: fpr }4173 - { id: 1, class: fpr }4174liveins:4175 - { reg: '$q0', virtual-reg: '%1' }4176body: |4177 bb.0.entry:4178 liveins: $q04179 4180 ; CHECK-LABEL: name: test_rule1604_id589_at_idx978414181 ; CHECK: liveins: $q04182 ; CHECK-NEXT: {{ $}}4183 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q04184 ; CHECK-NEXT: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZSv2f64 [[COPY]], implicit $fpcr4185 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTZSv2f64_]]4186 %1:fpr(<2 x s64>) = COPY $q04187 %0:fpr(<2 x s64>) = G_FPTOSI %1(<2 x s64>)4188 $noreg = PATCHABLE_RET %0(<2 x s64>)4189 4190...4191---4192name: test_rule1613_id592_at_idx981564193alignment: 44194legalized: true4195regBankSelected: true4196tracksRegLiveness: true4197registers:4198 - { id: 0, class: fpr }4199 - { id: 1, class: fpr }4200liveins:4201 - { reg: '$d0', virtual-reg: '%1' }4202body: |4203 bb.0.entry:4204 liveins: $d04205 4206 ; CHECK-LABEL: name: test_rule1613_id592_at_idx981564207 ; CHECK: liveins: $d04208 ; CHECK-NEXT: {{ $}}4209 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d04210 ; CHECK-NEXT: [[FCVTZUv2f32_:%[0-9]+]]:fpr64 = nofpexcept FCVTZUv2f32 [[COPY]], implicit $fpcr4211 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTZUv2f32_]]4212 %1:fpr(<2 x s32>) = COPY $d04213 %0:fpr(<2 x s32>) = G_FPTOUI %1(<2 x s32>)4214 $noreg = PATCHABLE_RET %0(<2 x s32>)4215 4216...4217---4218name: test_rule1614_id593_at_idx981914219alignment: 44220legalized: true4221regBankSelected: true4222tracksRegLiveness: true4223registers:4224 - { id: 0, class: fpr }4225 - { id: 1, class: fpr }4226liveins:4227 - { reg: '$q0', virtual-reg: '%1' }4228body: |4229 bb.0.entry:4230 liveins: $q04231 4232 ; CHECK-LABEL: name: test_rule1614_id593_at_idx981914233 ; CHECK: liveins: $q04234 ; CHECK-NEXT: {{ $}}4235 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q04236 ; CHECK-NEXT: [[FCVTZUv4f32_:%[0-9]+]]:fpr128 = nofpexcept FCVTZUv4f32 [[COPY]], implicit $fpcr4237 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTZUv4f32_]]4238 %1:fpr(<4 x s32>) = COPY $q04239 %0:fpr(<4 x s32>) = G_FPTOUI %1(<4 x s32>)4240 $noreg = PATCHABLE_RET %0(<4 x s32>)4241 4242...4243---4244name: test_rule1615_id594_at_idx982264245alignment: 44246legalized: true4247regBankSelected: true4248tracksRegLiveness: true4249registers:4250 - { id: 0, class: fpr }4251 - { id: 1, class: fpr }4252liveins:4253 - { reg: '$q0', virtual-reg: '%1' }4254body: |4255 bb.0.entry:4256 liveins: $q04257 4258 ; CHECK-LABEL: name: test_rule1615_id594_at_idx982264259 ; CHECK: liveins: $q04260 ; CHECK-NEXT: {{ $}}4261 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q04262 ; CHECK-NEXT: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZUv2f64 [[COPY]], implicit $fpcr4263 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTZUv2f64_]]4264 %1:fpr(<2 x s64>) = COPY $q04265 %0:fpr(<2 x s64>) = G_FPTOUI %1(<2 x s64>)4266 $noreg = PATCHABLE_RET %0(<2 x s64>)4267 4268...4269---4270name: test_rule1619_id2389_at_idx983664271alignment: 44272legalized: true4273regBankSelected: true4274tracksRegLiveness: true4275registers:4276 - { id: 0, class: fpr }4277 - { id: 1, class: fpr }4278liveins:4279 - { reg: '$q0', virtual-reg: '%1' }4280body: |4281 bb.0.entry:4282 liveins: $q04283 4284 ; CHECK-LABEL: name: test_rule1619_id2389_at_idx983664285 ; CHECK: liveins: $q04286 ; CHECK-NEXT: {{ $}}4287 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q04288 ; CHECK-NEXT: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv2i32 [[COPY]], implicit $fpcr4289 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTNv2i32_]]4290 %1:fpr(<2 x s64>) = COPY $q04291 %0:fpr(<2 x s32>) = G_FPTRUNC %1(<2 x s64>)4292 $noreg = PATCHABLE_RET %0(<2 x s32>)4293 4294...4295---4296name: test_rule1620_id2390_at_idx983994297alignment: 44298legalized: true4299regBankSelected: true4300tracksRegLiveness: true4301registers:4302 - { id: 0, class: fpr }4303 - { id: 1, class: fpr }4304liveins:4305 - { reg: '$q0', virtual-reg: '%1' }4306body: |4307 bb.0.entry:4308 liveins: $q04309 4310 ; CHECK-LABEL: name: test_rule1620_id2390_at_idx983994311 ; CHECK: liveins: $q04312 ; CHECK-NEXT: {{ $}}4313 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q04314 ; CHECK-NEXT: [[FCVTNv4i16_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv4i16 [[COPY]], implicit $fpcr4315 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTNv4i16_]]4316 %1:fpr(<4 x s32>) = COPY $q04317 %0:fpr(<4 x s16>) = G_FPTRUNC %1(<4 x s32>)4318 $noreg = PATCHABLE_RET %0(<4 x s16>)4319 4320...4321---4322name: test_rule1621_id2923_at_idx984324323alignment: 44324legalized: true4325regBankSelected: true4326tracksRegLiveness: true4327registers:4328 - { id: 0, class: fpr }4329 - { id: 1, class: fpr }4330liveins:4331 - { reg: '$d0', virtual-reg: '%1' }4332body: |4333 bb.0.entry:4334 liveins: $d04335 4336 ; CHECK-LABEL: name: test_rule1621_id2923_at_idx984324337 ; CHECK: liveins: $d04338 ; CHECK-NEXT: {{ $}}4339 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d04340 ; CHECK-NEXT: [[SSHLLv8i8_shift:%[0-9]+]]:fpr128 = SSHLLv8i8_shift [[COPY]], 04341 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SSHLLv8i8_shift]]4342 %1:fpr(<8 x s8>) = COPY $d04343 %0:fpr(<8 x s16>) = G_SEXT %1(<8 x s8>)4344 $noreg = PATCHABLE_RET %0(<8 x s16>)4345 4346...4347---4348name: test_rule1622_id2926_at_idx984774349alignment: 44350legalized: true4351regBankSelected: true4352tracksRegLiveness: true4353registers:4354 - { id: 0, class: fpr }4355 - { id: 1, class: fpr }4356liveins:4357 - { reg: '$d0', virtual-reg: '%1' }4358body: |4359 bb.0.entry:4360 liveins: $d04361 4362 ; CHECK-LABEL: name: test_rule1622_id2926_at_idx984774363 ; CHECK: liveins: $d04364 ; CHECK-NEXT: {{ $}}4365 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d04366 ; CHECK-NEXT: [[SSHLLv4i16_shift:%[0-9]+]]:fpr128 = SSHLLv4i16_shift [[COPY]], 04367 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SSHLLv4i16_shift]]4368 %1:fpr(<4 x s16>) = COPY $d04369 %0:fpr(<4 x s32>) = G_SEXT %1(<4 x s16>)4370 $noreg = PATCHABLE_RET %0(<4 x s32>)4371 4372...4373---4374name: test_rule1623_id2929_at_idx985224375alignment: 44376legalized: true4377regBankSelected: true4378tracksRegLiveness: true4379registers:4380 - { id: 0, class: fpr }4381 - { id: 1, class: fpr }4382liveins:4383 - { reg: '$d0', virtual-reg: '%1' }4384body: |4385 bb.0.entry:4386 liveins: $d04387 4388 ; CHECK-LABEL: name: test_rule1623_id2929_at_idx985224389 ; CHECK: liveins: $d04390 ; CHECK-NEXT: {{ $}}4391 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d04392 ; CHECK-NEXT: [[SSHLLv2i32_shift:%[0-9]+]]:fpr128 = SSHLLv2i32_shift [[COPY]], 04393 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SSHLLv2i32_shift]]4394 %1:fpr(<2 x s32>) = COPY $d04395 %0:fpr(<2 x s64>) = G_SEXT %1(<2 x s32>)4396 $noreg = PATCHABLE_RET %0(<2 x s64>)4397 4398...4399---4400name: test_rule1632_id687_at_idx988474401alignment: 44402legalized: true4403regBankSelected: true4404tracksRegLiveness: true4405registers:4406 - { id: 0, class: fpr }4407 - { id: 1, class: fpr }4408liveins:4409 - { reg: '$d0', virtual-reg: '%1' }4410body: |4411 bb.0.entry:4412 liveins: $d04413 4414 ; CHECK-LABEL: name: test_rule1632_id687_at_idx988474415 ; CHECK: liveins: $d04416 ; CHECK-NEXT: {{ $}}4417 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d04418 ; CHECK-NEXT: [[SCVTFv2f32_:%[0-9]+]]:fpr64 = nofpexcept SCVTFv2f32 [[COPY]], implicit $fpcr4419 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SCVTFv2f32_]]4420 %1:fpr(<2 x s32>) = COPY $d04421 %0:fpr(<2 x s32>) = G_SITOFP %1(<2 x s32>)4422 $noreg = PATCHABLE_RET %0(<2 x s32>)4423 4424...4425---4426name: test_rule1633_id688_at_idx988824427alignment: 44428legalized: true4429regBankSelected: true4430tracksRegLiveness: true4431registers:4432 - { id: 0, class: fpr }4433 - { id: 1, class: fpr }4434liveins:4435 - { reg: '$q0', virtual-reg: '%1' }4436body: |4437 bb.0.entry:4438 liveins: $q04439 4440 ; CHECK-LABEL: name: test_rule1633_id688_at_idx988824441 ; CHECK: liveins: $q04442 ; CHECK-NEXT: {{ $}}4443 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q04444 ; CHECK-NEXT: [[SCVTFv4f32_:%[0-9]+]]:fpr128 = nofpexcept SCVTFv4f32 [[COPY]], implicit $fpcr4445 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SCVTFv4f32_]]4446 %1:fpr(<4 x s32>) = COPY $q04447 %0:fpr(<4 x s32>) = G_SITOFP %1(<4 x s32>)4448 $noreg = PATCHABLE_RET %0(<4 x s32>)4449 4450...4451---4452name: test_rule1634_id689_at_idx989174453alignment: 44454legalized: true4455regBankSelected: true4456tracksRegLiveness: true4457registers:4458 - { id: 0, class: fpr }4459 - { id: 1, class: fpr }4460liveins:4461 - { reg: '$q0', virtual-reg: '%1' }4462body: |4463 bb.0.entry:4464 liveins: $q04465 4466 ; CHECK-LABEL: name: test_rule1634_id689_at_idx989174467 ; CHECK: liveins: $q04468 ; CHECK-NEXT: {{ $}}4469 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q04470 ; CHECK-NEXT: [[SCVTFv2f64_:%[0-9]+]]:fpr128 = nofpexcept SCVTFv2f64 [[COPY]], implicit $fpcr4471 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[SCVTFv2f64_]]4472 %1:fpr(<2 x s64>) = COPY $q04473 %0:fpr(<2 x s64>) = G_SITOFP %1(<2 x s64>)4474 $noreg = PATCHABLE_RET %0(<2 x s64>)4475 4476...4477---4478name: test_rule1635_id748_at_idx989524479alignment: 44480legalized: true4481regBankSelected: true4482tracksRegLiveness: true4483registers:4484 - { id: 0, class: fpr }4485 - { id: 1, class: fpr }4486liveins:4487 - { reg: '$q0', virtual-reg: '%1' }4488body: |4489 bb.0.entry:4490 liveins: $q04491 4492 ; CHECK-LABEL: name: test_rule1635_id748_at_idx989524493 ; CHECK: liveins: $q04494 ; CHECK-NEXT: {{ $}}4495 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q04496 ; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[COPY]]4497 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[XTNv8i8_]]4498 %1:fpr(<8 x s16>) = COPY $q04499 %0:fpr(<8 x s8>) = G_TRUNC %1(<8 x s16>)4500 $noreg = PATCHABLE_RET %0(<8 x s8>)4501 4502...4503---4504name: test_rule1636_id749_at_idx989874505alignment: 44506legalized: true4507regBankSelected: true4508tracksRegLiveness: true4509registers:4510 - { id: 0, class: fpr }4511 - { id: 1, class: fpr }4512liveins:4513 - { reg: '$q0', virtual-reg: '%1' }4514body: |4515 bb.0.entry:4516 liveins: $q04517 4518 ; CHECK-LABEL: name: test_rule1636_id749_at_idx989874519 ; CHECK: liveins: $q04520 ; CHECK-NEXT: {{ $}}4521 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q04522 ; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[COPY]]4523 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[XTNv4i16_]]4524 %1:fpr(<4 x s32>) = COPY $q04525 %0:fpr(<4 x s16>) = G_TRUNC %1(<4 x s32>)4526 $noreg = PATCHABLE_RET %0(<4 x s16>)4527 4528...4529---4530name: test_rule1637_id750_at_idx990224531alignment: 44532legalized: true4533regBankSelected: true4534tracksRegLiveness: true4535registers:4536 - { id: 0, class: fpr }4537 - { id: 1, class: fpr }4538liveins:4539 - { reg: '$q0', virtual-reg: '%1' }4540body: |4541 bb.0.entry:4542 liveins: $q04543 4544 ; CHECK-LABEL: name: test_rule1637_id750_at_idx990224545 ; CHECK: liveins: $q04546 ; CHECK-NEXT: {{ $}}4547 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q04548 ; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[COPY]]4549 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[XTNv2i32_]]4550 %1:fpr(<2 x s64>) = COPY $q04551 %0:fpr(<2 x s32>) = G_TRUNC %1(<2 x s64>)4552 $noreg = PATCHABLE_RET %0(<2 x s32>)4553 4554...4555---4556name: test_rule1647_id731_at_idx993864557alignment: 44558legalized: true4559regBankSelected: true4560tracksRegLiveness: true4561registers:4562 - { id: 0, class: fpr }4563 - { id: 1, class: fpr }4564liveins:4565 - { reg: '$d0', virtual-reg: '%1' }4566body: |4567 bb.0.entry:4568 liveins: $d04569 4570 ; CHECK-LABEL: name: test_rule1647_id731_at_idx993864571 ; CHECK: liveins: $d04572 ; CHECK-NEXT: {{ $}}4573 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d04574 ; CHECK-NEXT: [[UCVTFv2f32_:%[0-9]+]]:fpr64 = nofpexcept UCVTFv2f32 [[COPY]], implicit $fpcr4575 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[UCVTFv2f32_]]4576 %1:fpr(<2 x s32>) = COPY $d04577 %0:fpr(<2 x s32>) = G_UITOFP %1(<2 x s32>)4578 $noreg = PATCHABLE_RET %0(<2 x s32>)4579 4580...4581---4582name: test_rule1648_id732_at_idx994214583alignment: 44584legalized: true4585regBankSelected: true4586tracksRegLiveness: true4587registers:4588 - { id: 0, class: fpr }4589 - { id: 1, class: fpr }4590liveins:4591 - { reg: '$q0', virtual-reg: '%1' }4592body: |4593 bb.0.entry:4594 liveins: $q04595 4596 ; CHECK-LABEL: name: test_rule1648_id732_at_idx994214597 ; CHECK: liveins: $q04598 ; CHECK-NEXT: {{ $}}4599 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q04600 ; CHECK-NEXT: [[UCVTFv4f32_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv4f32 [[COPY]], implicit $fpcr4601 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[UCVTFv4f32_]]4602 %1:fpr(<4 x s32>) = COPY $q04603 %0:fpr(<4 x s32>) = G_UITOFP %1(<4 x s32>)4604 $noreg = PATCHABLE_RET %0(<4 x s32>)4605 4606...4607---4608name: test_rule1649_id733_at_idx994564609alignment: 44610legalized: true4611regBankSelected: true4612tracksRegLiveness: true4613registers:4614 - { id: 0, class: fpr }4615 - { id: 1, class: fpr }4616liveins:4617 - { reg: '$q0', virtual-reg: '%1' }4618body: |4619 bb.0.entry:4620 liveins: $q04621 4622 ; CHECK-LABEL: name: test_rule1649_id733_at_idx994564623 ; CHECK: liveins: $q04624 ; CHECK-NEXT: {{ $}}4625 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q04626 ; CHECK-NEXT: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv2f64 [[COPY]], implicit $fpcr4627 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[UCVTFv2f64_]]4628 %1:fpr(<2 x s64>) = COPY $q04629 %0:fpr(<2 x s64>) = G_UITOFP %1(<2 x s64>)4630 $noreg = PATCHABLE_RET %0(<2 x s64>)4631 4632...4633---4634name: test_rule1650_id2924_at_idx994914635alignment: 44636legalized: true4637regBankSelected: true4638tracksRegLiveness: true4639registers:4640 - { id: 0, class: fpr }4641 - { id: 1, class: fpr }4642liveins:4643 - { reg: '$d0', virtual-reg: '%1' }4644body: |4645 bb.0.entry:4646 liveins: $d04647 4648 ; CHECK-LABEL: name: test_rule1650_id2924_at_idx994914649 ; CHECK: liveins: $d04650 ; CHECK-NEXT: {{ $}}4651 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d04652 ; CHECK-NEXT: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 04653 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[USHLLv8i8_shift]]4654 %1:fpr(<8 x s8>) = COPY $d04655 %0:fpr(<8 x s16>) = G_ZEXT %1(<8 x s8>)4656 $noreg = PATCHABLE_RET %0(<8 x s16>)4657 4658...4659---4660name: test_rule1651_id2927_at_idx995364661alignment: 44662legalized: true4663regBankSelected: true4664tracksRegLiveness: true4665registers:4666 - { id: 0, class: fpr }4667 - { id: 1, class: fpr }4668liveins:4669 - { reg: '$d0', virtual-reg: '%1' }4670body: |4671 bb.0.entry:4672 liveins: $d04673 4674 ; CHECK-LABEL: name: test_rule1651_id2927_at_idx995364675 ; CHECK: liveins: $d04676 ; CHECK-NEXT: {{ $}}4677 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d04678 ; CHECK-NEXT: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 04679 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[USHLLv4i16_shift]]4680 %1:fpr(<4 x s16>) = COPY $d04681 %0:fpr(<4 x s32>) = G_ZEXT %1(<4 x s16>)4682 $noreg = PATCHABLE_RET %0(<4 x s32>)4683 4684...4685---4686name: test_rule1652_id2930_at_idx995814687alignment: 44688legalized: true4689regBankSelected: true4690tracksRegLiveness: true4691registers:4692 - { id: 0, class: fpr }4693 - { id: 1, class: fpr }4694liveins:4695 - { reg: '$d0', virtual-reg: '%1' }4696body: |4697 bb.0.entry:4698 liveins: $d04699 4700 ; CHECK-LABEL: name: test_rule1652_id2930_at_idx995814701 ; CHECK: liveins: $d04702 ; CHECK-NEXT: {{ $}}4703 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d04704 ; CHECK-NEXT: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 04705 ; CHECK-NEXT: $noreg = PATCHABLE_RET [[USHLLv2i32_shift]]4706 %1:fpr(<2 x s32>) = COPY $d04707 %0:fpr(<2 x s64>) = G_ZEXT %1(<2 x s32>)4708 $noreg = PATCHABLE_RET %0(<2 x s64>)4709 4710...4711