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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4---5name: zextload_s32_from_s166legalized: true7regBankSelected: true8body: |9 bb.0:10 liveins: $x011 12 ; CHECK-LABEL: name: zextload_s32_from_s1613 ; CHECK: liveins: $x014 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x016 ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))17 ; CHECK-NEXT: $w0 = COPY [[LDRHHui]]18 %0:gpr(p0) = COPY $x019 %1:gpr(s32) = G_ZEXTLOAD %0 :: (load (s16))20 $w0 = COPY %1(s32)21...22---23name: zextload_s32_from_s16_not_combined24legalized: true25regBankSelected: true26body: |27 bb.0:28 liveins: $x029 30 ; CHECK-LABEL: name: zextload_s32_from_s16_not_combined31 ; CHECK: liveins: $x032 ; CHECK-NEXT: {{ $}}33 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x034 ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))35 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]36 ; CHECK-NEXT: $w0 = COPY [[COPY1]]37 %0:gpr(p0) = COPY $x038 %1:gpr(s16) = G_LOAD %0 :: (load (s16))39 %2:gpr(s32) = G_ZEXT %140 $w0 = COPY %2(s32)41...42---43name: i32_to_i6444legalized: true45regBankSelected: true46body: |47 bb.0:48 liveins: $x049 50 ; CHECK-LABEL: name: i32_to_i6451 ; CHECK: liveins: $x052 ; CHECK-NEXT: {{ $}}53 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x054 ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (s32))55 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRWui]], %subreg.sub_3256 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]57 ; CHECK-NEXT: RET_ReallyLR implicit $x058 %0:gpr(p0) = COPY $x059 %2:gpr(s64) = G_ZEXTLOAD %0(p0) :: (load (s32))60 $x0 = COPY %2(s64)61 RET_ReallyLR implicit $x062 63...64---65name: i16_to_i6466legalized: true67regBankSelected: true68body: |69 bb.0:70 liveins: $x071 72 ; CHECK-LABEL: name: i16_to_i6473 ; CHECK: liveins: $x074 ; CHECK-NEXT: {{ $}}75 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x076 ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))77 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRHHui]], %subreg.sub_3278 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]79 ; CHECK-NEXT: RET_ReallyLR implicit $x080 %0:gpr(p0) = COPY $x081 %2:gpr(s64) = G_ZEXTLOAD %0(p0) :: (load (s16))82 $x0 = COPY %2(s64)83 RET_ReallyLR implicit $x084 85...86---87name: i8_to_i6488legalized: true89regBankSelected: true90body: |91 bb.0:92 liveins: $x093 94 ; CHECK-LABEL: name: i8_to_i6495 ; CHECK: liveins: $x096 ; CHECK-NEXT: {{ $}}97 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x098 ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))99 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRBBui]], %subreg.sub_32100 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]101 ; CHECK-NEXT: RET_ReallyLR implicit $x0102 %0:gpr(p0) = COPY $x0103 %2:gpr(s64) = G_ZEXTLOAD %0(p0) :: (load (s8))104 $x0 = COPY %2(s64)105 RET_ReallyLR implicit $x0106 107...108---109name: i8_to_i32110legalized: true111regBankSelected: true112body: |113 bb.0:114 liveins: $x0115 116 ; CHECK-LABEL: name: i8_to_i32117 ; CHECK: liveins: $x0118 ; CHECK-NEXT: {{ $}}119 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0120 ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))121 ; CHECK-NEXT: $w0 = COPY [[LDRBBui]]122 ; CHECK-NEXT: RET_ReallyLR implicit $w0123 %0:gpr(p0) = COPY $x0124 %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load (s8))125 $w0 = COPY %2(s32)126 RET_ReallyLR implicit $w0127 128...129---130name: i16_to_i32131legalized: true132regBankSelected: true133body: |134 bb.0:135 liveins: $x0136 137 ; CHECK-LABEL: name: i16_to_i32138 ; CHECK: liveins: $x0139 ; CHECK-NEXT: {{ $}}140 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0141 ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))142 ; CHECK-NEXT: $w0 = COPY [[LDRHHui]]143 ; CHECK-NEXT: RET_ReallyLR implicit $w0144 %0:gpr(p0) = COPY $x0145 %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load (s16))146 $w0 = COPY %2(s32)147 RET_ReallyLR implicit $w0148 149...150 151---152name: zextload_s32_from_s8_atomic_unordered153legalized: true154regBankSelected: true155body: |156 bb.0:157 liveins: $x0158 159 ; CHECK-LABEL: name: zextload_s32_from_s8_atomic_unordered160 ; CHECK: liveins: $x0161 ; CHECK-NEXT: {{ $}}162 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0163 ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load unordered (s8))164 ; CHECK-NEXT: $w0 = COPY [[LDRBBui]]165 ; CHECK-NEXT: RET_ReallyLR implicit $w0166 %0:gpr(p0) = COPY $x0167 %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load unordered (s8))168 $w0 = COPY %2169 RET_ReallyLR implicit $w0170 171...172 173---174name: zextload_s32_from_s8_atomic_monotonic175legalized: true176regBankSelected: true177body: |178 bb.0:179 liveins: $x0180 181 ; CHECK-LABEL: name: zextload_s32_from_s8_atomic_monotonic182 ; CHECK: liveins: $x0183 ; CHECK-NEXT: {{ $}}184 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0185 ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load monotonic (s8))186 ; CHECK-NEXT: $w0 = COPY [[LDRBBui]]187 ; CHECK-NEXT: RET_ReallyLR implicit $w0188 %0:gpr(p0) = COPY $x0189 %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load monotonic (s8))190 $w0 = COPY %2191 RET_ReallyLR implicit $w0192 193...194 195---196name: zextload_s32_from_s8_atomic_acquire197legalized: true198regBankSelected: true199body: |200 bb.0:201 liveins: $x0202 203 ; CHECK-LABEL: name: zextload_s32_from_s8_atomic_acquire204 ; CHECK: liveins: $x0205 ; CHECK-NEXT: {{ $}}206 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0207 ; CHECK-NEXT: [[LDARB:%[0-9]+]]:gpr32 = LDARB [[COPY]] :: (load acquire (s8))208 ; CHECK-NEXT: $w0 = COPY [[LDARB]]209 ; CHECK-NEXT: RET_ReallyLR implicit $w0210 %0:gpr(p0) = COPY $x0211 %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load acquire (s8))212 $w0 = COPY %2213 RET_ReallyLR implicit $w0214 215...216 217---218name: zextload_s32_from_s8_atomic_seq_cst219legalized: true220regBankSelected: true221body: |222 bb.0:223 liveins: $x0224 225 ; CHECK-LABEL: name: zextload_s32_from_s8_atomic_seq_cst226 ; CHECK: liveins: $x0227 ; CHECK-NEXT: {{ $}}228 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0229 ; CHECK-NEXT: [[LDARB:%[0-9]+]]:gpr32 = LDARB [[COPY]] :: (load seq_cst (s8))230 ; CHECK-NEXT: $w0 = COPY [[LDARB]]231 ; CHECK-NEXT: RET_ReallyLR implicit $w0232 %0:gpr(p0) = COPY $x0233 %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load seq_cst (s8))234 $w0 = COPY %2235 RET_ReallyLR implicit $w0236 237...238 239---240name: zextload_s32_from_s16_atomic_unordered241legalized: true242regBankSelected: true243body: |244 bb.0:245 liveins: $x0246 247 ; CHECK-LABEL: name: zextload_s32_from_s16_atomic_unordered248 ; CHECK: liveins: $x0249 ; CHECK-NEXT: {{ $}}250 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0251 ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load unordered (s16))252 ; CHECK-NEXT: $w0 = COPY [[LDRHHui]]253 ; CHECK-NEXT: RET_ReallyLR implicit $w0254 %0:gpr(p0) = COPY $x0255 %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load unordered (s16))256 $w0 = COPY %2257 RET_ReallyLR implicit $w0258 259...260 261---262name: zextload_s32_from_s16_atomic_monotonic263legalized: true264regBankSelected: true265body: |266 bb.0:267 liveins: $x0268 269 ; CHECK-LABEL: name: zextload_s32_from_s16_atomic_monotonic270 ; CHECK: liveins: $x0271 ; CHECK-NEXT: {{ $}}272 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0273 ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load monotonic (s16))274 ; CHECK-NEXT: $w0 = COPY [[LDRHHui]]275 ; CHECK-NEXT: RET_ReallyLR implicit $w0276 %0:gpr(p0) = COPY $x0277 %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load monotonic (s16))278 $w0 = COPY %2279 RET_ReallyLR implicit $w0280 281...282 283---284name: zextload_s32_from_s16_atomic_acquire285legalized: true286regBankSelected: true287body: |288 bb.0:289 liveins: $x0290 291 ; CHECK-LABEL: name: zextload_s32_from_s16_atomic_acquire292 ; CHECK: liveins: $x0293 ; CHECK-NEXT: {{ $}}294 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0295 ; CHECK-NEXT: [[LDARH:%[0-9]+]]:gpr32 = LDARH [[COPY]] :: (load acquire (s16))296 ; CHECK-NEXT: $w0 = COPY [[LDARH]]297 ; CHECK-NEXT: RET_ReallyLR implicit $w0298 %0:gpr(p0) = COPY $x0299 %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load acquire (s16))300 $w0 = COPY %2301 RET_ReallyLR implicit $w0302 303...304 305---306name: zextload_s32_from_s16_atomic_seq_cst307legalized: true308regBankSelected: true309body: |310 bb.0:311 liveins: $x0312 313 ; CHECK-LABEL: name: zextload_s32_from_s16_atomic_seq_cst314 ; CHECK: liveins: $x0315 ; CHECK-NEXT: {{ $}}316 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0317 ; CHECK-NEXT: [[LDARH:%[0-9]+]]:gpr32 = LDARH [[COPY]] :: (load seq_cst (s16))318 ; CHECK-NEXT: $w0 = COPY [[LDARH]]319 ; CHECK-NEXT: RET_ReallyLR implicit $w0320 %0:gpr(p0) = COPY $x0321 %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load seq_cst (s16))322 $w0 = COPY %2323 RET_ReallyLR implicit $w0324 325...326