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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3--- |4 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"5 target triple = "aarch64"6 7 @x = dso_local global i32 -32768, align 48 9 define dso_local i32 @check_sext_not_lost(ptr %ptr) {10 entry:11 %ptr.addr = alloca ptr, align 812 store ptr %ptr, ptr %ptr.addr, align 813 %0 = load ptr, ptr %ptr.addr, align 814 %1 = load i32, ptr @x, align 415 %sub = sub nsw i32 %1, 3276816 %conv = trunc i32 %sub to i1617 %idxprom = sext i16 %conv to i6418 %arrayidx = getelementptr inbounds i32, ptr %0, i64 %idxprom19 %2 = load i32, ptr %arrayidx, align 420 ret i32 %221 }22 23...24---25name: check_sext_not_lost26alignment: 427legalized: true28regBankSelected: true29tracksRegLiveness: true30registers:31 - { id: 0, class: gpr }32 - { id: 1, class: gpr }33 - { id: 2, class: gpr }34 - { id: 3, class: gpr }35 - { id: 4, class: gpr }36 - { id: 5, class: gpr }37 - { id: 6, class: gpr }38 - { id: 7, class: _ }39 - { id: 8, class: gpr }40 - { id: 9, class: _ }41 - { id: 10, class: gpr }42 - { id: 11, class: gpr }43 - { id: 12, class: _ }44 - { id: 13, class: gpr }45 - { id: 14, class: gpr }46 - { id: 15, class: gpr64 }47 - { id: 16, class: gpr }48liveins:49 - { reg: '$x0' }50frameInfo:51 maxAlignment: 852 maxCallFrameSize: 053stack:54 - { id: 0, name: ptr.addr, size: 8, alignment: 8 }55machineFunctionInfo: {}56body: |57 bb.0.entry:58 liveins: $x059 60 ; CHECK-LABEL: name: check_sext_not_lost61 ; CHECK: liveins: $x062 ; CHECK-NEXT: {{ $}}63 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64all = COPY $x064 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]65 ; CHECK-NEXT: STRXui [[COPY1]], %stack.0.ptr.addr, 0 :: (store (p0) into %ir.ptr.addr)66 ; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64common = LDRXui %stack.0.ptr.addr, 0 :: (dereferenceable load (p0) from %ir.ptr.addr)67 ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @x68 ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @x :: (dereferenceable load (s32) from @x)69 ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = nsw SUBSWri [[LDRWui]], 8, 12, implicit-def dead $nzcv70 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF71 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[SUBSWri]], %subreg.sub_3272 ; CHECK-NEXT: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[INSERT_SUBREG]], 0, 1573 ; CHECK-NEXT: [[LDRWroX:%[0-9]+]]:gpr32 = LDRWroX [[LDRXui]], [[SBFMXri]], 0, 1 :: (load (s32) from %ir.arrayidx)74 ; CHECK-NEXT: $w0 = COPY [[LDRWroX]]75 ; CHECK-NEXT: RET_ReallyLR implicit $w076 %0:gpr(p0) = COPY $x077 %1:gpr(p0) = G_FRAME_INDEX %stack.0.ptr.addr78 G_STORE %0(p0), %1(p0) :: (store (p0) into %ir.ptr.addr)79 %2:gpr(p0) = G_LOAD %1(p0) :: (dereferenceable load (p0) from %ir.ptr.addr)80 %15:gpr64(p0) = ADRP target-flags(aarch64-page) @x81 %4:gpr(p0) = G_ADD_LOW %15(p0), target-flags(aarch64-pageoff, aarch64-nc) @x82 %3:gpr(s32) = G_LOAD %4(p0) :: (dereferenceable load (s32) from @x)83 %5:gpr(s32) = G_CONSTANT i32 3276884 %6:gpr(s32) = nsw G_SUB %3, %585 %16:gpr(s64) = G_ANYEXT %6(s32)86 %8:gpr(s64) = G_SEXT_INREG %16, 1687 %14:gpr(s64) = G_CONSTANT i64 288 %10:gpr(s64) = G_SHL %8, %14(s64)89 %11:gpr(p0) = G_PTR_ADD %2, %10(s64)90 %13:gpr(s32) = G_LOAD %11(p0) :: (load (s32) from %ir.arrayidx)91 $w0 = COPY %13(s32)92 RET_ReallyLR implicit $w093 94...95