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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -run-pass=loadstore-opt -verify-machineinstrs %s -o - | FileCheck %s3--- |4 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"5 target triple = "aarch64"6 7 define void @test_simple_2xs8(ptr %ptr) {8 %addr11 = bitcast ptr %ptr to ptr9 store i8 4, ptr %addr11, align 110 %addr2 = getelementptr i8, ptr %ptr, i64 111 store i8 5, ptr %addr2, align 112 ret void13 }14 15 define void @test_simple_2xs16(ptr %ptr) {16 %addr11 = bitcast ptr %ptr to ptr17 store i16 4, ptr %addr11, align 218 %addr2 = getelementptr i16, ptr %ptr, i64 119 store i16 5, ptr %addr2, align 220 ret void21 }22 23 define void @test_simple_4xs16(ptr %ptr) {24 %addr11 = bitcast ptr %ptr to ptr25 store i16 4, ptr %addr11, align 226 %addr2 = getelementptr i16, ptr %ptr, i64 127 store i16 5, ptr %addr2, align 228 %addr3 = getelementptr i16, ptr %ptr, i64 229 store i16 9, ptr %addr3, align 230 %addr4 = getelementptr i16, ptr %ptr, i64 331 store i16 14, ptr %addr4, align 232 ret void33 }34 35 define void @test_simple_2xs32(ptr %ptr) {36 %addr11 = bitcast ptr %ptr to ptr37 store i32 4, ptr %addr11, align 438 %addr2 = getelementptr i32, ptr %ptr, i64 139 store i32 5, ptr %addr2, align 440 ret void41 }42 43 define void @test_simple_2xs64_illegal(ptr %ptr) {44 %addr11 = bitcast ptr %ptr to ptr45 store i64 4, ptr %addr11, align 846 %addr2 = getelementptr i64, ptr %ptr, i64 147 store i64 5, ptr %addr2, align 848 ret void49 }50 51 define void @test_simple_vector(ptr %ptr) {52 %addr11 = bitcast ptr %ptr to ptr53 store <2 x i16> <i16 4, i16 7>, ptr %addr11, align 454 %addr2 = getelementptr <2 x i16>, ptr %ptr, i64 155 store <2 x i16> <i16 5, i16 8>, ptr %addr2, align 456 ret void57 }58 59 define i32 @test_unknown_alias(ptr %ptr, ptr %aliasptr) {60 %addr11 = bitcast ptr %ptr to ptr61 store i32 4, ptr %addr11, align 462 %ld = load i32, ptr %aliasptr, align 463 %addr2 = getelementptr i32, ptr %ptr, i64 164 store i32 5, ptr %addr2, align 465 ret i32 %ld66 }67 68 define void @test_2x_2xs32(ptr %ptr, ptr %ptr2) {69 %addr11 = bitcast ptr %ptr to ptr70 store i32 4, ptr %addr11, align 471 %addr2 = getelementptr i32, ptr %ptr, i64 172 store i32 5, ptr %addr2, align 473 %addr32 = bitcast ptr %ptr2 to ptr74 store i32 9, ptr %addr32, align 475 %addr4 = getelementptr i32, ptr %ptr2, i64 176 store i32 17, ptr %addr4, align 477 ret void78 }79 80 define void @test_simple_var_2xs8(ptr %ptr, i8 %v1, i8 %v2) {81 %addr11 = bitcast ptr %ptr to ptr82 store i8 %v1, ptr %addr11, align 183 %addr2 = getelementptr i8, ptr %ptr, i64 184 store i8 %v2, ptr %addr2, align 185 ret void86 }87 88 define void @test_simple_var_2xs16(ptr %ptr, i16 %v1, i16 %v2) {89 %addr11 = bitcast ptr %ptr to ptr90 store i16 %v1, ptr %addr11, align 291 %addr2 = getelementptr i16, ptr %ptr, i64 192 store i16 %v2, ptr %addr2, align 293 ret void94 }95 96 define void @test_simple_var_2xs32(ptr %ptr, i32 %v1, i32 %v2) {97 %addr11 = bitcast ptr %ptr to ptr98 store i32 %v1, ptr %addr11, align 499 %addr2 = getelementptr i32, ptr %ptr, i64 1100 store i32 %v2, ptr %addr2, align 4101 ret void102 }103 104 define void @test_alias_4xs16(ptr %ptr, ptr %ptr2) {105 %addr11 = bitcast ptr %ptr to ptr106 store i16 4, ptr %addr11, align 2107 %addr2 = getelementptr i16, ptr %ptr, i64 1108 store i16 5, ptr %addr2, align 2109 %addr3 = getelementptr i16, ptr %ptr, i64 2110 store i16 9, ptr %addr3, align 2111 store i16 0, ptr %ptr2, align 2112 %addr4 = getelementptr i16, ptr %ptr, i64 3113 store i16 14, ptr %addr4, align 2114 ret void115 }116 117 define void @test_alias2_4xs16(ptr %ptr, ptr %ptr2, ptr %ptr3) {118 %addr11 = bitcast ptr %ptr to ptr119 store i16 4, ptr %addr11, align 2120 %addr2 = getelementptr i16, ptr %ptr, i64 1121 store i16 0, ptr %ptr3, align 2122 store i16 5, ptr %addr2, align 2123 %addr3 = getelementptr i16, ptr %ptr, i64 2124 store i16 9, ptr %addr3, align 2125 store i16 0, ptr %ptr2, align 2126 %addr4 = getelementptr i16, ptr %ptr, i64 3127 store i16 14, ptr %addr4, align 2128 ret void129 }130 131 define void @test_alias3_4xs16(ptr %ptr, ptr %ptr2, ptr %ptr3, ptr %ptr4) {132 %addr11 = bitcast ptr %ptr to ptr133 store i16 4, ptr %addr11, align 2134 %addr2 = getelementptr i16, ptr %ptr, i64 1135 store i16 0, ptr %ptr3, align 2136 store i16 5, ptr %addr2, align 2137 store i16 0, ptr %ptr4, align 2138 %addr3 = getelementptr i16, ptr %ptr, i64 2139 store i16 9, ptr %addr3, align 2140 store i16 0, ptr %ptr2, align 2141 %addr4 = getelementptr i16, ptr %ptr, i64 3142 store i16 14, ptr %addr4, align 2143 ret void144 }145 146 define i32 @test_alias_allocas_2xs32(ptr %ptr) {147 %a1 = alloca [6 x i32], align 4148 %a2 = alloca i32, align 4149 %addr11 = bitcast ptr %a1 to ptr150 store i32 4, ptr %addr11, align 4151 %ld = load i32, ptr %a2, align 4152 %addr2 = getelementptr [6 x i32], ptr %a1, i64 0, i32 1153 store i32 5, ptr %addr2, align 4154 ret i32 %ld155 }156 157 define void @test_simple_2xs32_with_align(ptr %ptr) {158 %addr11 = bitcast ptr %ptr to ptr159 store i32 4, ptr %addr11, align 4160 %addr2 = getelementptr i32, ptr %ptr, i64 1161 store i32 5, ptr %addr2, align 4162 ret void163 }164 165 @G = external global [10 x i32]166 define void @invalid_zero_offset_no_merge(i64 %0) {167 %2 = getelementptr [10 x i32], ptr @G, i64 0, i64 %0168 store i32 0, ptr %2, align 4169 store i32 0, ptr getelementptr inbounds ([10 x i32], ptr @G, i64 0, i64 1), align 4170 ret void171 }172...173---174name: test_simple_2xs8175alignment: 4176tracksRegLiveness: true177liveins:178 - { reg: '$x0' }179frameInfo:180 maxAlignment: 1181machineFunctionInfo: {}182body: |183 bb.1 (%ir-block.0):184 liveins: $x0185 186 ; CHECK-LABEL: name: test_simple_2xs8187 ; CHECK: liveins: $x0188 ; CHECK-NEXT: {{ $}}189 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0190 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 4191 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 5192 ; CHECK-NEXT: G_STORE [[C]](s8), [[COPY]](p0) :: (store (s8) into %ir.addr11)193 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1194 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)195 ; CHECK-NEXT: G_STORE [[C1]](s8), [[PTR_ADD]](p0) :: (store (s8) into %ir.addr2)196 ; CHECK-NEXT: RET_ReallyLR197 %0:_(p0) = COPY $x0198 %1:_(s8) = G_CONSTANT i8 4199 %4:_(s8) = G_CONSTANT i8 5200 G_STORE %1(s8), %0(p0) :: (store (s8) into %ir.addr11)201 %2:_(s64) = G_CONSTANT i64 1202 %3:_(p0) = G_PTR_ADD %0, %2(s64)203 G_STORE %4(s8), %3(p0) :: (store (s8) into %ir.addr2)204 RET_ReallyLR205 206...207---208name: test_simple_2xs16209alignment: 4210tracksRegLiveness: true211liveins:212 - { reg: '$x0' }213frameInfo:214 maxAlignment: 1215machineFunctionInfo: {}216body: |217 bb.1 (%ir-block.0):218 liveins: $x0219 220 ; CHECK-LABEL: name: test_simple_2xs16221 ; CHECK: liveins: $x0222 ; CHECK-NEXT: {{ $}}223 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0224 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 327684225 ; CHECK-NEXT: G_STORE [[C]](s32), [[COPY]](p0) :: (store (s32) into %ir.addr11, align 2)226 ; CHECK-NEXT: RET_ReallyLR227 %0:_(p0) = COPY $x0228 %1:_(s16) = G_CONSTANT i16 4229 %4:_(s16) = G_CONSTANT i16 5230 G_STORE %1(s16), %0(p0) :: (store (s16) into %ir.addr11)231 %2:_(s64) = G_CONSTANT i64 2232 %3:_(p0) = G_PTR_ADD %0, %2(s64)233 G_STORE %4(s16), %3(p0) :: (store (s16) into %ir.addr2)234 RET_ReallyLR235 236...237---238name: test_simple_4xs16239alignment: 4240tracksRegLiveness: true241liveins:242 - { reg: '$x0' }243frameInfo:244 maxAlignment: 1245machineFunctionInfo: {}246body: |247 bb.1 (%ir-block.0):248 liveins: $x0249 250 ; CHECK-LABEL: name: test_simple_4xs16251 ; CHECK: liveins: $x0252 ; CHECK-NEXT: {{ $}}253 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0254 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3940688328982532255 ; CHECK-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s64) into %ir.addr11, align 2)256 ; CHECK-NEXT: RET_ReallyLR257 %0:_(p0) = COPY $x0258 %1:_(s16) = G_CONSTANT i16 4259 %4:_(s16) = G_CONSTANT i16 5260 %7:_(s16) = G_CONSTANT i16 9261 %10:_(s16) = G_CONSTANT i16 14262 G_STORE %1(s16), %0(p0) :: (store (s16) into %ir.addr11)263 %2:_(s64) = G_CONSTANT i64 2264 %3:_(p0) = G_PTR_ADD %0, %2(s64)265 G_STORE %4(s16), %3(p0) :: (store (s16) into %ir.addr2)266 %5:_(s64) = G_CONSTANT i64 4267 %6:_(p0) = G_PTR_ADD %0, %5(s64)268 G_STORE %7(s16), %6(p0) :: (store (s16) into %ir.addr3)269 %8:_(s64) = G_CONSTANT i64 6270 %9:_(p0) = G_PTR_ADD %0, %8(s64)271 G_STORE %10(s16), %9(p0) :: (store (s16) into %ir.addr4)272 RET_ReallyLR273 274...275---276name: test_simple_2xs32277alignment: 4278tracksRegLiveness: true279liveins:280 - { reg: '$x0' }281frameInfo:282 maxAlignment: 1283machineFunctionInfo: {}284body: |285 bb.1 (%ir-block.0):286 liveins: $x0287 288 ; CHECK-LABEL: name: test_simple_2xs32289 ; CHECK: liveins: $x0290 ; CHECK-NEXT: {{ $}}291 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0292 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 21474836484293 ; CHECK-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s64) into %ir.addr11, align 4)294 ; CHECK-NEXT: RET_ReallyLR295 %0:_(p0) = COPY $x0296 %1:_(s32) = G_CONSTANT i32 4297 %4:_(s32) = G_CONSTANT i32 5298 G_STORE %1(s32), %0(p0) :: (store (s32) into %ir.addr11)299 %2:_(s64) = G_CONSTANT i64 4300 %3:_(p0) = G_PTR_ADD %0, %2(s64)301 G_STORE %4(s32), %3(p0) :: (store (s32) into %ir.addr2)302 RET_ReallyLR303 304...305---306name: test_simple_2xs64_illegal307alignment: 4308tracksRegLiveness: true309liveins:310 - { reg: '$x0' }311frameInfo:312 maxAlignment: 1313machineFunctionInfo: {}314body: |315 bb.1 (%ir-block.0):316 liveins: $x0317 318 ; CHECK-LABEL: name: test_simple_2xs64_illegal319 ; CHECK: liveins: $x0320 ; CHECK-NEXT: {{ $}}321 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0322 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4323 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 5324 ; CHECK-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s64) into %ir.addr11)325 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8326 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)327 ; CHECK-NEXT: G_STORE [[C1]](s64), [[PTR_ADD]](p0) :: (store (s64) into %ir.addr2)328 ; CHECK-NEXT: RET_ReallyLR329 %0:_(p0) = COPY $x0330 %1:_(s64) = G_CONSTANT i64 4331 %4:_(s64) = G_CONSTANT i64 5332 G_STORE %1(s64), %0(p0) :: (store (s64) into %ir.addr11)333 %2:_(s64) = G_CONSTANT i64 8334 %3:_(p0) = G_PTR_ADD %0, %2(s64)335 G_STORE %4(s64), %3(p0) :: (store (s64) into %ir.addr2)336 RET_ReallyLR337 338...339---340name: test_simple_vector341alignment: 4342tracksRegLiveness: true343liveins:344 - { reg: '$x0' }345frameInfo:346 maxAlignment: 1347machineFunctionInfo: {}348body: |349 bb.1 (%ir-block.0):350 liveins: $x0351 352 ; CHECK-LABEL: name: test_simple_vector353 ; CHECK: liveins: $x0354 ; CHECK-NEXT: {{ $}}355 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0356 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 4357 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 7358 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C1]](s16)359 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 5360 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8361 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C2]](s16), [[C3]](s16)362 ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s16>), [[COPY]](p0) :: (store (<2 x s16>) into %ir.addr11)363 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4364 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C4]](s64)365 ; CHECK-NEXT: G_STORE [[BUILD_VECTOR1]](<2 x s16>), [[PTR_ADD]](p0) :: (store (<2 x s16>) into %ir.addr2)366 ; CHECK-NEXT: RET_ReallyLR367 %0:_(p0) = COPY $x0368 %2:_(s16) = G_CONSTANT i16 4369 %3:_(s16) = G_CONSTANT i16 7370 %1:_(<2 x s16>) = G_BUILD_VECTOR %2(s16), %3(s16)371 %7:_(s16) = G_CONSTANT i16 5372 %8:_(s16) = G_CONSTANT i16 8373 %6:_(<2 x s16>) = G_BUILD_VECTOR %7(s16), %8(s16)374 G_STORE %1(<2 x s16>), %0(p0) :: (store (<2 x s16>) into %ir.addr11)375 %4:_(s64) = G_CONSTANT i64 4376 %5:_(p0) = G_PTR_ADD %0, %4(s64)377 G_STORE %6(<2 x s16>), %5(p0) :: (store (<2 x s16>) into %ir.addr2)378 RET_ReallyLR379 380...381---382name: test_unknown_alias383alignment: 4384tracksRegLiveness: true385liveins:386 - { reg: '$x0' }387 - { reg: '$x1' }388frameInfo:389 maxAlignment: 1390machineFunctionInfo: {}391body: |392 bb.1 (%ir-block.0):393 liveins: $x0, $x1394 395 ; CHECK-LABEL: name: test_unknown_alias396 ; CHECK: liveins: $x0, $x1397 ; CHECK-NEXT: {{ $}}398 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0399 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1400 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4401 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5402 ; CHECK-NEXT: G_STORE [[C]](s32), [[COPY]](p0) :: (store (s32) into %ir.addr11)403 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load (s32) from %ir.aliasptr)404 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4405 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)406 ; CHECK-NEXT: G_STORE [[C1]](s32), [[PTR_ADD]](p0) :: (store (s32) into %ir.addr2)407 ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)408 ; CHECK-NEXT: RET_ReallyLR implicit $w0409 %0:_(p0) = COPY $x0410 %1:_(p0) = COPY $x1411 %2:_(s32) = G_CONSTANT i32 4412 %6:_(s32) = G_CONSTANT i32 5413 G_STORE %2(s32), %0(p0) :: (store (s32) into %ir.addr11)414 %3:_(s32) = G_LOAD %1(p0) :: (load (s32) from %ir.aliasptr)415 %4:_(s64) = G_CONSTANT i64 4416 %5:_(p0) = G_PTR_ADD %0, %4(s64)417 G_STORE %6(s32), %5(p0) :: (store (s32) into %ir.addr2)418 $w0 = COPY %3(s32)419 RET_ReallyLR implicit $w0420 421...422---423name: test_2x_2xs32424alignment: 4425tracksRegLiveness: true426liveins:427 - { reg: '$x0' }428 - { reg: '$x1' }429frameInfo:430 maxAlignment: 1431machineFunctionInfo: {}432body: |433 bb.1 (%ir-block.0):434 liveins: $x0, $x1435 436 ; CHECK-LABEL: name: test_2x_2xs32437 ; CHECK: liveins: $x0, $x1438 ; CHECK-NEXT: {{ $}}439 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0440 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1441 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4442 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5443 ; CHECK-NEXT: G_STORE [[C]](s32), [[COPY]](p0) :: (store (s32) into %ir.addr11)444 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4445 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)446 ; CHECK-NEXT: G_STORE [[C1]](s32), [[PTR_ADD]](p0) :: (store (s32) into %ir.addr2)447 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 73014444041448 ; CHECK-NEXT: G_STORE [[C3]](s64), [[COPY1]](p0) :: (store (s64) into %ir.addr32, align 4)449 ; CHECK-NEXT: RET_ReallyLR450 %0:_(p0) = COPY $x0451 %1:_(p0) = COPY $x1452 %2:_(s32) = G_CONSTANT i32 4453 %5:_(s32) = G_CONSTANT i32 5454 %6:_(s32) = G_CONSTANT i32 9455 %8:_(s32) = G_CONSTANT i32 17456 G_STORE %2(s32), %0(p0) :: (store (s32) into %ir.addr11)457 %3:_(s64) = G_CONSTANT i64 4458 %4:_(p0) = G_PTR_ADD %0, %3(s64)459 G_STORE %5(s32), %4(p0) :: (store (s32) into %ir.addr2)460 G_STORE %6(s32), %1(p0) :: (store (s32) into %ir.addr32)461 %7:_(p0) = G_PTR_ADD %1, %3(s64)462 G_STORE %8(s32), %7(p0) :: (store (s32) into %ir.addr4)463 RET_ReallyLR464 465...466---467name: test_simple_var_2xs8468alignment: 4469tracksRegLiveness: true470liveins:471 - { reg: '$x0' }472 - { reg: '$w1' }473 - { reg: '$w2' }474frameInfo:475 maxAlignment: 1476machineFunctionInfo: {}477body: |478 bb.1 (%ir-block.0):479 liveins: $w1, $w2, $x0480 481 ; CHECK-LABEL: name: test_simple_var_2xs8482 ; CHECK: liveins: $w1, $w2, $x0483 ; CHECK-NEXT: {{ $}}484 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0485 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1486 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)487 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2488 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)489 ; CHECK-NEXT: G_STORE [[TRUNC]](s8), [[COPY]](p0) :: (store (s8) into %ir.addr11)490 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1491 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)492 ; CHECK-NEXT: G_STORE [[TRUNC1]](s8), [[PTR_ADD]](p0) :: (store (s8) into %ir.addr2)493 ; CHECK-NEXT: RET_ReallyLR494 %0:_(p0) = COPY $x0495 %3:_(s32) = COPY $w1496 %1:_(s8) = G_TRUNC %3(s32)497 %4:_(s32) = COPY $w2498 %2:_(s8) = G_TRUNC %4(s32)499 G_STORE %1(s8), %0(p0) :: (store (s8) into %ir.addr11)500 %5:_(s64) = G_CONSTANT i64 1501 %6:_(p0) = G_PTR_ADD %0, %5(s64)502 G_STORE %2(s8), %6(p0) :: (store (s8) into %ir.addr2)503 RET_ReallyLR504 505...506---507name: test_simple_var_2xs16508alignment: 4509tracksRegLiveness: true510liveins:511 - { reg: '$x0' }512 - { reg: '$w1' }513 - { reg: '$w2' }514frameInfo:515 maxAlignment: 1516machineFunctionInfo: {}517body: |518 bb.1 (%ir-block.0):519 liveins: $w1, $w2, $x0520 521 ; CHECK-LABEL: name: test_simple_var_2xs16522 ; CHECK: liveins: $w1, $w2, $x0523 ; CHECK-NEXT: {{ $}}524 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0525 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1526 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)527 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2528 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)529 ; CHECK-NEXT: G_STORE [[TRUNC]](s16), [[COPY]](p0) :: (store (s16) into %ir.addr11)530 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2531 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)532 ; CHECK-NEXT: G_STORE [[TRUNC1]](s16), [[PTR_ADD]](p0) :: (store (s16) into %ir.addr2)533 ; CHECK-NEXT: RET_ReallyLR534 %0:_(p0) = COPY $x0535 %3:_(s32) = COPY $w1536 %1:_(s16) = G_TRUNC %3(s32)537 %4:_(s32) = COPY $w2538 %2:_(s16) = G_TRUNC %4(s32)539 G_STORE %1(s16), %0(p0) :: (store (s16) into %ir.addr11)540 %5:_(s64) = G_CONSTANT i64 2541 %6:_(p0) = G_PTR_ADD %0, %5(s64)542 G_STORE %2(s16), %6(p0) :: (store (s16) into %ir.addr2)543 RET_ReallyLR544 545...546---547name: test_simple_var_2xs32548alignment: 4549tracksRegLiveness: true550liveins:551 - { reg: '$x0' }552 - { reg: '$w1' }553 - { reg: '$w2' }554frameInfo:555 maxAlignment: 1556machineFunctionInfo: {}557body: |558 bb.1 (%ir-block.0):559 liveins: $w1, $w2, $x0560 561 ; CHECK-LABEL: name: test_simple_var_2xs32562 ; CHECK: liveins: $w1, $w2, $x0563 ; CHECK-NEXT: {{ $}}564 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0565 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1566 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2567 ; CHECK-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.addr11)568 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4569 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)570 ; CHECK-NEXT: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s32) into %ir.addr2)571 ; CHECK-NEXT: RET_ReallyLR572 %0:_(p0) = COPY $x0573 %1:_(s32) = COPY $w1574 %2:_(s32) = COPY $w2575 G_STORE %1(s32), %0(p0) :: (store (s32) into %ir.addr11)576 %3:_(s64) = G_CONSTANT i64 4577 %4:_(p0) = G_PTR_ADD %0, %3(s64)578 G_STORE %2(s32), %4(p0) :: (store (s32) into %ir.addr2)579 RET_ReallyLR580 581...582---583name: test_alias_4xs16584alignment: 4585tracksRegLiveness: true586liveins:587 - { reg: '$x0' }588 - { reg: '$x1' }589frameInfo:590 maxAlignment: 1591machineFunctionInfo: {}592# The store to ptr2 prevents merging into a single store.593# We can still merge the stores into addr1 and addr2.594body: |595 bb.1 (%ir-block.0):596 liveins: $x0, $x1597 ; CHECK-LABEL: name: test_alias_4xs16598 ; CHECK: liveins: $x0, $x1599 ; CHECK-NEXT: {{ $}}600 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0601 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1602 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 9603 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 0604 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 14605 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 327684606 ; CHECK-NEXT: G_STORE [[C3]](s32), [[COPY]](p0) :: (store (s32) into %ir.addr11, align 2)607 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4608 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C4]](s64)609 ; CHECK-NEXT: G_STORE [[C]](s16), [[PTR_ADD]](p0) :: (store (s16) into %ir.addr3)610 ; CHECK-NEXT: G_STORE [[C1]](s16), [[COPY1]](p0) :: (store (s16) into %ir.ptr2)611 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 6612 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C5]](s64)613 ; CHECK-NEXT: G_STORE [[C2]](s16), [[PTR_ADD1]](p0) :: (store (s16) into %ir.addr4)614 ; CHECK-NEXT: RET_ReallyLR615 %0:_(p0) = COPY $x0616 %1:_(p0) = COPY $x1617 %2:_(s16) = G_CONSTANT i16 4618 %5:_(s16) = G_CONSTANT i16 5619 %8:_(s16) = G_CONSTANT i16 9620 %9:_(s16) = G_CONSTANT i16 0621 %12:_(s16) = G_CONSTANT i16 14622 G_STORE %2(s16), %0(p0) :: (store (s16) into %ir.addr11)623 %3:_(s64) = G_CONSTANT i64 2624 %4:_(p0) = G_PTR_ADD %0, %3(s64)625 G_STORE %5(s16), %4(p0) :: (store (s16) into %ir.addr2)626 %6:_(s64) = G_CONSTANT i64 4627 %7:_(p0) = G_PTR_ADD %0, %6(s64)628 G_STORE %8(s16), %7(p0) :: (store (s16) into %ir.addr3)629 G_STORE %9(s16), %1(p0) :: (store (s16) into %ir.ptr2)630 %10:_(s64) = G_CONSTANT i64 6631 %11:_(p0) = G_PTR_ADD %0, %10(s64)632 G_STORE %12(s16), %11(p0) :: (store (s16) into %ir.addr4)633 RET_ReallyLR634 635...636---637name: test_alias2_4xs16638alignment: 4639tracksRegLiveness: true640liveins:641 - { reg: '$x0' }642 - { reg: '$x1' }643 - { reg: '$x2' }644frameInfo:645 maxAlignment: 1646machineFunctionInfo: {}647# Here store of 5 and 9 can be merged, others have aliasing barriers.648body: |649 bb.1 (%ir-block.0):650 liveins: $x0, $x1, $x2651 ; CHECK-LABEL: name: test_alias2_4xs16652 ; CHECK: liveins: $x0, $x1, $x2653 ; CHECK-NEXT: {{ $}}654 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0655 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1656 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x2657 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 4658 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 0659 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 14660 ; CHECK-NEXT: G_STORE [[C]](s16), [[COPY]](p0) :: (store (s16) into %ir.addr11)661 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2662 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C3]](s64)663 ; CHECK-NEXT: G_STORE [[C1]](s16), [[COPY2]](p0) :: (store (s16) into %ir.ptr3)664 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 589829665 ; CHECK-NEXT: G_STORE [[C4]](s32), [[PTR_ADD]](p0) :: (store (s32) into %ir.addr2, align 2)666 ; CHECK-NEXT: G_STORE [[C1]](s16), [[COPY1]](p0) :: (store (s16) into %ir.ptr2)667 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 6668 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C5]](s64)669 ; CHECK-NEXT: G_STORE [[C2]](s16), [[PTR_ADD1]](p0) :: (store (s16) into %ir.addr4)670 ; CHECK-NEXT: RET_ReallyLR671 %0:_(p0) = COPY $x0672 %1:_(p0) = COPY $x1673 %2:_(p0) = COPY $x2674 %3:_(s16) = G_CONSTANT i16 4675 %6:_(s16) = G_CONSTANT i16 0676 %7:_(s16) = G_CONSTANT i16 5677 %10:_(s16) = G_CONSTANT i16 9678 %13:_(s16) = G_CONSTANT i16 14679 G_STORE %3(s16), %0(p0) :: (store (s16) into %ir.addr11)680 %4:_(s64) = G_CONSTANT i64 2681 %5:_(p0) = G_PTR_ADD %0, %4(s64)682 G_STORE %6(s16), %2(p0) :: (store (s16) into %ir.ptr3)683 G_STORE %7(s16), %5(p0) :: (store (s16) into %ir.addr2)684 %8:_(s64) = G_CONSTANT i64 4685 %9:_(p0) = G_PTR_ADD %0, %8(s64)686 G_STORE %10(s16), %9(p0) :: (store (s16) into %ir.addr3)687 G_STORE %6(s16), %1(p0) :: (store (s16) into %ir.ptr2)688 %11:_(s64) = G_CONSTANT i64 6689 %12:_(p0) = G_PTR_ADD %0, %11(s64)690 G_STORE %13(s16), %12(p0) :: (store (s16) into %ir.addr4)691 RET_ReallyLR692 693...694---695name: test_alias3_4xs16696alignment: 4697tracksRegLiveness: true698liveins:699 - { reg: '$x0' }700 - { reg: '$x1' }701 - { reg: '$x2' }702 - { reg: '$x3' }703frameInfo:704 maxAlignment: 1705machineFunctionInfo: {}706# No merging can be done here.707body: |708 bb.1 (%ir-block.0):709 liveins: $x0, $x1, $x2, $x3710 711 ; CHECK-LABEL: name: test_alias3_4xs16712 ; CHECK: liveins: $x0, $x1, $x2, $x3713 ; CHECK-NEXT: {{ $}}714 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0715 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1716 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x2717 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x3718 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 4719 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 0720 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 5721 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 9722 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 14723 ; CHECK-NEXT: G_STORE [[C]](s16), [[COPY]](p0) :: (store (s16) into %ir.addr11)724 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 2725 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C5]](s64)726 ; CHECK-NEXT: G_STORE [[C1]](s16), [[COPY2]](p0) :: (store (s16) into %ir.ptr3)727 ; CHECK-NEXT: G_STORE [[C2]](s16), [[PTR_ADD]](p0) :: (store (s16) into %ir.addr2)728 ; CHECK-NEXT: G_STORE [[C1]](s16), [[COPY3]](p0) :: (store (s16) into %ir.ptr4)729 ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4730 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C6]](s64)731 ; CHECK-NEXT: G_STORE [[C3]](s16), [[PTR_ADD1]](p0) :: (store (s16) into %ir.addr3)732 ; CHECK-NEXT: G_STORE [[C1]](s16), [[COPY1]](p0) :: (store (s16) into %ir.ptr2)733 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 6734 ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C7]](s64)735 ; CHECK-NEXT: G_STORE [[C4]](s16), [[PTR_ADD2]](p0) :: (store (s16) into %ir.addr4)736 ; CHECK-NEXT: RET_ReallyLR737 %0:_(p0) = COPY $x0738 %1:_(p0) = COPY $x1739 %2:_(p0) = COPY $x2740 %3:_(p0) = COPY $x3741 %4:_(s16) = G_CONSTANT i16 4742 %7:_(s16) = G_CONSTANT i16 0743 %8:_(s16) = G_CONSTANT i16 5744 %11:_(s16) = G_CONSTANT i16 9745 %14:_(s16) = G_CONSTANT i16 14746 G_STORE %4(s16), %0(p0) :: (store (s16) into %ir.addr11)747 %5:_(s64) = G_CONSTANT i64 2748 %6:_(p0) = G_PTR_ADD %0, %5(s64)749 G_STORE %7(s16), %2(p0) :: (store (s16) into %ir.ptr3)750 G_STORE %8(s16), %6(p0) :: (store (s16) into %ir.addr2)751 G_STORE %7(s16), %3(p0) :: (store (s16) into %ir.ptr4)752 %9:_(s64) = G_CONSTANT i64 4753 %10:_(p0) = G_PTR_ADD %0, %9(s64)754 G_STORE %11(s16), %10(p0) :: (store (s16) into %ir.addr3)755 G_STORE %7(s16), %1(p0) :: (store (s16) into %ir.ptr2)756 %12:_(s64) = G_CONSTANT i64 6757 %13:_(p0) = G_PTR_ADD %0, %12(s64)758 G_STORE %14(s16), %13(p0) :: (store (s16) into %ir.addr4)759 RET_ReallyLR760 761...762---763name: test_alias_allocas_2xs32764alignment: 4765tracksRegLiveness: true766liveins:767 - { reg: '$x0' }768frameInfo:769 maxAlignment: 4770stack:771 - { id: 0, name: a1, size: 24, alignment: 4 }772 - { id: 1, name: a2, size: 4, alignment: 4 }773machineFunctionInfo: {}774# Can merge because the load is from a different alloca and can't alias.775body: |776 bb.1 (%ir-block.0):777 liveins: $x0778 ; CHECK-LABEL: name: test_alias_allocas_2xs32779 ; CHECK: liveins: $x0780 ; CHECK-NEXT: {{ $}}781 ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.a1782 ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.a2783 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (dereferenceable load (s32) from %ir.a2)784 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 21474836484785 ; CHECK-NEXT: G_STORE [[C]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %ir.addr11, align 4)786 ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)787 ; CHECK-NEXT: RET_ReallyLR implicit $w0788 %3:_(s32) = G_CONSTANT i32 4789 %7:_(s32) = G_CONSTANT i32 5790 %1:_(p0) = G_FRAME_INDEX %stack.0.a1791 %2:_(p0) = G_FRAME_INDEX %stack.1.a2792 G_STORE %3(s32), %1(p0) :: (store (s32) into %ir.addr11)793 %4:_(s32) = G_LOAD %2(p0) :: (dereferenceable load (s32) from %ir.a2)794 %5:_(s64) = G_CONSTANT i64 4795 %6:_(p0) = G_PTR_ADD %1, %5(s64)796 G_STORE %7(s32), %6(p0) :: (store (s32) into %ir.addr2)797 $w0 = COPY %4(s32)798 RET_ReallyLR implicit $w0799 800...801---802name: test_simple_2xs32_with_align803alignment: 4804tracksRegLiveness: true805liveins:806 - { reg: '$x0' }807frameInfo:808 maxAlignment: 1809machineFunctionInfo: {}810body: |811 bb.1 (%ir-block.0):812 liveins: $x0813 814 ; CHECK-LABEL: name: test_simple_2xs32_with_align815 ; CHECK: liveins: $x0816 ; CHECK-NEXT: {{ $}}817 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0818 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 21474836484819 ; CHECK-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s64) into %ir.addr11, align 2)820 ; CHECK-NEXT: RET_ReallyLR821 %0:_(p0) = COPY $x0822 %1:_(s32) = G_CONSTANT i32 4823 %4:_(s32) = G_CONSTANT i32 5824 G_STORE %1(s32), %0(p0) :: (store (s32) into %ir.addr11, align 2)825 %2:_(s64) = G_CONSTANT i64 4826 %3:_(p0) = G_PTR_ADD %0, %2(s64)827 G_STORE %4(s32), %3(p0) :: (store (s32) into %ir.addr2, align 2)828 RET_ReallyLR829 830...831---832name: invalid_zero_offset_no_merge833alignment: 4834tracksRegLiveness: true835liveins:836 - { reg: '$x0' }837frameInfo:838 maxAlignment: 1839machineFunctionInfo: {}840body: |841 bb.1 (%ir-block.1):842 liveins: $x0843 844 ; CHECK-LABEL: name: invalid_zero_offset_no_merge845 ; CHECK: liveins: $x0846 ; CHECK-NEXT: {{ $}}847 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0848 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2849 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)850 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @G851 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[GV]], [[SHL]](s64)852 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0853 ; CHECK-NEXT: G_STORE [[C1]](s32), [[PTR_ADD]](p0) :: (store (s32) into %ir.2)854 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4855 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[GV]], [[C2]](s64)856 ; CHECK-NEXT: G_STORE [[C1]](s32), [[PTR_ADD1]](p0) :: (store (s32) into `ptr getelementptr inbounds ([10 x i32], ptr @G, i64 0, i64 1)`)857 ; CHECK-NEXT: RET_ReallyLR858 %0:_(s64) = COPY $x0859 %9:_(s64) = G_CONSTANT i64 2860 %3:_(s64) = G_SHL %0, %9(s64)861 %1:_(p0) = G_GLOBAL_VALUE @G862 %4:_(p0) = G_PTR_ADD %1, %3(s64)863 %6:_(s32) = G_CONSTANT i32 0864 G_STORE %6(s32), %4(p0) :: (store (s32) into %ir.2)865 %8:_(s64) = G_CONSTANT i64 4866 %7:_(p0) = nuw G_PTR_ADD %1, %8(s64)867 G_STORE %6(s32), %7(p0) :: (store (s32) into `ptr getelementptr inbounds ([10 x i32], ptr @G, i64 0, i64 1)`)868 RET_ReallyLR869 870...871