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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -global-isel -global-isel-abort=1 -aarch64-enable-gisel-sve=1 %s -o - | FileCheck %s3 4;; Test the correct usage of the Z registers with multiple SVE arguments.5 6define void @formal_argument_nxv16i8_2(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, ptr %p) {7; CHECK-LABEL: formal_argument_nxv16i8_2:8; CHECK: // %bb.0:9; CHECK-NEXT: ptrue p0.b10; CHECK-NEXT: st1b { z0.b }, p0, [x0]11; CHECK-NEXT: st1b { z1.b }, p0, [x0]12; CHECK-NEXT: ret13 store <vscale x 16 x i8> %0, ptr %p, align 1614 store <vscale x 16 x i8> %1, ptr %p, align 1615 ret void16}17 18define void @formal_argument_nxv16i8_8(19; CHECK-LABEL: formal_argument_nxv16i8_8:20; CHECK: // %bb.0:21; CHECK-NEXT: ptrue p0.b22; CHECK-NEXT: st1b { z0.b }, p0, [x0]23; CHECK-NEXT: st1b { z1.b }, p0, [x0]24; CHECK-NEXT: st1b { z2.b }, p0, [x0]25; CHECK-NEXT: st1b { z3.b }, p0, [x0]26; CHECK-NEXT: st1b { z4.b }, p0, [x0]27; CHECK-NEXT: st1b { z5.b }, p0, [x0]28; CHECK-NEXT: st1b { z6.b }, p0, [x0]29; CHECK-NEXT: st1b { z7.b }, p0, [x0]30; CHECK-NEXT: ret31 <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3,32 <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7,33 ptr %p) {34 35 store <vscale x 16 x i8> %0, ptr %p, align 1636 store <vscale x 16 x i8> %1, ptr %p, align 1637 store <vscale x 16 x i8> %2, ptr %p, align 1638 store <vscale x 16 x i8> %3, ptr %p, align 1639 store <vscale x 16 x i8> %4, ptr %p, align 1640 store <vscale x 16 x i8> %5, ptr %p, align 1641 store <vscale x 16 x i8> %6, ptr %p, align 1642 store <vscale x 16 x i8> %7, ptr %p, align 1643 ret void44}45