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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc < %s -mtriple aarch64 -mattr=+sve -aarch64-enable-gisel-sve=1 | FileCheck %s3; RUN: llc < %s -mtriple aarch64 -mattr=+sve -global-isel -aarch64-enable-gisel-sve=1 | FileCheck %s4 5;; add6define <vscale x 2 x i64> @addnxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {7; CHECK-LABEL: addnxv2i64:8; CHECK: // %bb.0: // %entry9; CHECK-NEXT: add z0.d, z0.d, z1.d10; CHECK-NEXT: ret11entry:12 %c = add <vscale x 2 x i64> %a, %b13 ret <vscale x 2 x i64> %c14}15 16define <vscale x 4 x i32> @addnxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {17; CHECK-LABEL: addnxv4i32:18; CHECK: // %bb.0: // %entry19; CHECK-NEXT: add z0.s, z0.s, z1.s20; CHECK-NEXT: ret21entry:22 %c = add <vscale x 4 x i32> %a, %b23 ret <vscale x 4 x i32> %c24}25 26define <vscale x 8 x i16> @addnxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, ptr %p) {27; CHECK-LABEL: addnxv8i16:28; CHECK: // %bb.0: // %entry29; CHECK-NEXT: add z0.h, z0.h, z1.h30; CHECK-NEXT: ret31entry:32 %c = add <vscale x 8 x i16> %a, %b33 ret <vscale x 8 x i16> %c34}35 36define <vscale x 16 x i8> @addnxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {37; CHECK-LABEL: addnxv16i8:38; CHECK: // %bb.0: // %entry39; CHECK-NEXT: add z0.b, z0.b, z1.b40; CHECK-NEXT: ret41entry:42 %c = add <vscale x 16 x i8> %a, %b43 ret <vscale x 16 x i8> %c44}45 46;; sub47define <vscale x 2 x i64> @subnxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {48; CHECK-LABEL: subnxv2i64:49; CHECK: // %bb.0: // %entry50; CHECK-NEXT: sub z0.d, z0.d, z1.d51; CHECK-NEXT: ret52entry:53 %c = sub <vscale x 2 x i64> %a, %b54 ret <vscale x 2 x i64> %c55}56 57define <vscale x 4 x i32> @subnxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {58; CHECK-LABEL: subnxv4i32:59; CHECK: // %bb.0: // %entry60; CHECK-NEXT: sub z0.s, z0.s, z1.s61; CHECK-NEXT: ret62entry:63 %c = sub <vscale x 4 x i32> %a, %b64 ret <vscale x 4 x i32> %c65}66 67define <vscale x 8 x i16> @subnxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, ptr %p) {68; CHECK-LABEL: subnxv8i16:69; CHECK: // %bb.0: // %entry70; CHECK-NEXT: sub z0.h, z0.h, z1.h71; CHECK-NEXT: ret72entry:73 %c = sub <vscale x 8 x i16> %a, %b74 ret <vscale x 8 x i16> %c75}76 77define <vscale x 16 x i8> @subnxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {78; CHECK-LABEL: subnxv16i8:79; CHECK: // %bb.0: // %entry80; CHECK-NEXT: sub z0.b, z0.b, z1.b81; CHECK-NEXT: ret82entry:83 %c = sub <vscale x 16 x i8> %a, %b84 ret <vscale x 16 x i8> %c85}86 87;; and88define <vscale x 2 x i64> @andnxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {89; CHECK-LABEL: andnxv2i64:90; CHECK: // %bb.0: // %entry91; CHECK-NEXT: and z0.d, z0.d, z1.d92; CHECK-NEXT: ret93entry:94 %c = and <vscale x 2 x i64> %a, %b95 ret <vscale x 2 x i64> %c96}97 98define <vscale x 4 x i32> @andnxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {99; CHECK-LABEL: andnxv4i32:100; CHECK: // %bb.0: // %entry101; CHECK-NEXT: and z0.d, z0.d, z1.d102; CHECK-NEXT: ret103entry:104 %c = and <vscale x 4 x i32> %a, %b105 ret <vscale x 4 x i32> %c106}107 108define <vscale x 8 x i16> @andnxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, ptr %p) {109; CHECK-LABEL: andnxv8i16:110; CHECK: // %bb.0: // %entry111; CHECK-NEXT: and z0.d, z0.d, z1.d112; CHECK-NEXT: ret113entry:114 %c = and <vscale x 8 x i16> %a, %b115 ret <vscale x 8 x i16> %c116}117 118define <vscale x 16 x i8> @andnxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {119; CHECK-LABEL: andnxv16i8:120; CHECK: // %bb.0: // %entry121; CHECK-NEXT: and z0.d, z0.d, z1.d122; CHECK-NEXT: ret123entry:124 %c = and <vscale x 16 x i8> %a, %b125 ret <vscale x 16 x i8> %c126}127 128;; or129define <vscale x 2 x i64> @ornxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {130; CHECK-LABEL: ornxv2i64:131; CHECK: // %bb.0: // %entry132; CHECK-NEXT: orr z0.d, z0.d, z1.d133; CHECK-NEXT: ret134entry:135 %c = or <vscale x 2 x i64> %a, %b136 ret <vscale x 2 x i64> %c137}138 139define <vscale x 4 x i32> @ornxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {140; CHECK-LABEL: ornxv4i32:141; CHECK: // %bb.0: // %entry142; CHECK-NEXT: orr z0.d, z0.d, z1.d143; CHECK-NEXT: ret144entry:145 %c = or <vscale x 4 x i32> %a, %b146 ret <vscale x 4 x i32> %c147}148 149define <vscale x 8 x i16> @ornxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, ptr %p) {150; CHECK-LABEL: ornxv8i16:151; CHECK: // %bb.0: // %entry152; CHECK-NEXT: orr z0.d, z0.d, z1.d153; CHECK-NEXT: ret154entry:155 %c = or <vscale x 8 x i16> %a, %b156 ret <vscale x 8 x i16> %c157}158 159define <vscale x 16 x i8> @ornxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {160; CHECK-LABEL: ornxv16i8:161; CHECK: // %bb.0: // %entry162; CHECK-NEXT: orr z0.d, z0.d, z1.d163; CHECK-NEXT: ret164entry:165 %c = or <vscale x 16 x i8> %a, %b166 ret <vscale x 16 x i8> %c167}168 169;; xor170define <vscale x 2 x i64> @xornxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {171; CHECK-LABEL: xornxv2i64:172; CHECK: // %bb.0: // %entry173; CHECK-NEXT: eor z0.d, z0.d, z1.d174; CHECK-NEXT: ret175entry:176 %c = xor <vscale x 2 x i64> %a, %b177 ret <vscale x 2 x i64> %c178}179 180define <vscale x 4 x i32> @xornxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {181; CHECK-LABEL: xornxv4i32:182; CHECK: // %bb.0: // %entry183; CHECK-NEXT: eor z0.d, z0.d, z1.d184; CHECK-NEXT: ret185entry:186 %c = xor <vscale x 4 x i32> %a, %b187 ret <vscale x 4 x i32> %c188}189 190define <vscale x 8 x i16> @xornxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, ptr %p) {191; CHECK-LABEL: xornxv8i16:192; CHECK: // %bb.0: // %entry193; CHECK-NEXT: eor z0.d, z0.d, z1.d194; CHECK-NEXT: ret195entry:196 %c = xor <vscale x 8 x i16> %a, %b197 ret <vscale x 8 x i16> %c198}199 200define <vscale x 16 x i8> @xornxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {201; CHECK-LABEL: xornxv16i8:202; CHECK: // %bb.0: // %entry203; CHECK-NEXT: eor z0.d, z0.d, z1.d204; CHECK-NEXT: ret205entry:206 %c = xor <vscale x 16 x i8> %a, %b207 ret <vscale x 16 x i8> %c208}209