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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -mtriple=arm64-apple-ios %s -o - -global-isel -global-isel-abort=1 -stop-after=irtranslator | FileCheck %s3 4define i128 @func_i128(ptr %ptr) {5 6 ; CHECK-LABEL: name: func_i1287 ; CHECK: bb.1 (%ir-block.0):8 ; CHECK-NEXT: liveins: $x09 ; CHECK-NEXT: {{ $}}10 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x011 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load (s128) from %ir.ptr)12 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)13 ; CHECK-NEXT: $x0 = COPY [[UV]](s64)14 ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)15 ; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x116 %val = load i128, ptr %ptr17 ret i128 %val18}19 20define <8 x float> @func_v8f32(ptr %ptr) {21 22 ; CHECK-LABEL: name: func_v8f3223 ; CHECK: bb.1 (%ir-block.0):24 ; CHECK-NEXT: liveins: $x025 ; CHECK-NEXT: {{ $}}26 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x027 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p0) :: (load (<8 x s32>) from %ir.ptr)28 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[LOAD]](<8 x s32>)29 ; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)30 ; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)31 ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q132 %val = load <8 x float>, ptr %ptr33 ret <8 x float> %val34}35 36; A bit weird, but s0-s5 is what SDAG does too.37define <6 x float> @func_v6f32(ptr %ptr) {38 39 ; CHECK-LABEL: name: func_v6f3240 ; CHECK: bb.1 (%ir-block.0):41 ; CHECK-NEXT: liveins: $x042 ; CHECK-NEXT: {{ $}}43 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x044 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<6 x s32>) = G_LOAD [[COPY]](p0) :: (load (<6 x s32>) from %ir.ptr, align 32)45 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<6 x s32>)46 ; CHECK-NEXT: $s0 = COPY [[UV]](s32)47 ; CHECK-NEXT: $s1 = COPY [[UV1]](s32)48 ; CHECK-NEXT: $s2 = COPY [[UV2]](s32)49 ; CHECK-NEXT: $s3 = COPY [[UV3]](s32)50 ; CHECK-NEXT: $s4 = COPY [[UV4]](s32)51 ; CHECK-NEXT: $s5 = COPY [[UV5]](s32)52 ; CHECK-NEXT: RET_ReallyLR implicit $s0, implicit $s1, implicit $s2, implicit $s3, implicit $s4, implicit $s553 %val = load <6 x float>, ptr %ptr54 ret <6 x float> %val55}56 57define i128 @ABIi128(i128 %arg1) {58 ; CHECK-LABEL: name: ABIi12859 ; CHECK: bb.1 (%ir-block.0):60 ; CHECK-NEXT: liveins: $x0, $x161 ; CHECK-NEXT: {{ $}}62 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x063 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x164 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)65 ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s128) = G_FPTOUI [[MV]](s128)66 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[FPTOUI]](s128)67 ; CHECK-NEXT: $x0 = COPY [[UV]](s64)68 ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)69 ; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x170 %farg1 = bitcast i128 %arg1 to fp12871 %res = fptoui fp128 %farg1 to i12872 ret i128 %res73}74