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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -o - %s -mtriple=aarch64 -run-pass=machine-scheduler -verify-machineinstrs | FileCheck %s3# RUN: llc -o - %s -mtriple=aarch64 -passes=machine-scheduler | FileCheck %s4--- |5 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"6 target triple = "aarch64"7 8 @a = dso_local global i32 2, align 49 @b = dso_local global i32 4, align 410 11 define i32 @fuseaddress(i32 %num) #0 {12 entry:13 %0 = load i32, ptr @a, align 414 %1 = load i32, ptr @b, align 415 %mul = mul nsw i32 %0, %116 ret i32 %mul17 }18 19 attributes #0 = { "target-cpu"="cortex-a55" }20 21---22name: fuseaddress23legalized: true24regBankSelected: true25tracksRegLiveness: true26liveins:27 - { reg: '$w0' }28body: |29 bb.0.entry:30 liveins: $w031 ; CHECK-LABEL: name: fuseaddress32 ; CHECK: liveins: $w033 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @a34 ; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @a :: (dereferenceable load (s32) from @a)35 ; CHECK: [[ADRP1:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @b36 ; CHECK: [[LDRWui1:%[0-9]+]]:gpr32 = LDRWui [[ADRP1]], target-flags(aarch64-pageoff, aarch64-nc) @b :: (dereferenceable load (s32) from @b)37 ; CHECK: [[MADDWrrr:%[0-9]+]]:gpr32 = nsw MADDWrrr [[LDRWui]], [[LDRWui1]], $wzr38 ; CHECK: $w0 = COPY [[MADDWrrr]]39 ; CHECK: RET_ReallyLR implicit $w040 %1:gpr64common = ADRP target-flags(aarch64-page) @a41 %4:gpr64common = ADRP target-flags(aarch64-page) @b42 %2:gpr32 = LDRWui killed %1:gpr64common, target-flags(aarch64-pageoff, aarch64-nc) @a :: (dereferenceable load (s32) from @a)43 %5:gpr32 = LDRWui killed %4:gpr64common, target-flags(aarch64-pageoff, aarch64-nc) @b :: (dereferenceable load (s32) from @b)44 %6:gpr32 = nsw MADDWrrr killed %2:gpr32, killed %5:gpr32, $wzr45 $w0 = COPY %6:gpr3246 RET_ReallyLR implicit $w047