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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64 -aarch64-neon-syntax=generic | FileCheck %s -check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=aarch64 -global-isel=1 -aarch64-neon-syntax=generic | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5declare i8 @llvm.vector.reduce.add.v2i8(<2 x i8>)6declare i8 @llvm.vector.reduce.add.v3i8(<3 x i8>)7declare i8 @llvm.vector.reduce.add.v4i8(<4 x i8>)8declare i8 @llvm.vector.reduce.add.v8i8(<8 x i8>)9declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>)10declare i8 @llvm.vector.reduce.add.v32i8(<32 x i8>)11declare i16 @llvm.vector.reduce.add.v2i16(<2 x i16>)12declare i16 @llvm.vector.reduce.add.v3i16(<3 x i16>)13declare i16 @llvm.vector.reduce.add.v4i16(<4 x i16>)14declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>)15declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>)16declare i32 @llvm.vector.reduce.add.v2i32(<2 x i32>)17declare i32 @llvm.vector.reduce.add.v3i32(<3 x i32>)18declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)19declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)20declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>)21declare i64 @llvm.vector.reduce.add.v3i64(<3 x i64>)22declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)23declare i128 @llvm.vector.reduce.add.v2i128(<2 x i128>)24 25 26define i8 @add_B(ptr %arr) {27; CHECK-LABEL: add_B:28; CHECK: // %bb.0:29; CHECK-NEXT: ldr q0, [x0]30; CHECK-NEXT: addv b0, v0.16b31; CHECK-NEXT: fmov w0, s032; CHECK-NEXT: ret33 %bin.rdx = load <16 x i8>, ptr %arr34 %r = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %bin.rdx)35 ret i8 %r36}37 38define i16 @add_H(ptr %arr) {39; CHECK-LABEL: add_H:40; CHECK: // %bb.0:41; CHECK-NEXT: ldr q0, [x0]42; CHECK-NEXT: addv h0, v0.8h43; CHECK-NEXT: fmov w0, s044; CHECK-NEXT: ret45 %bin.rdx = load <8 x i16>, ptr %arr46 %r = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %bin.rdx)47 ret i16 %r48}49 50define i32 @add_S( ptr %arr) {51; CHECK-LABEL: add_S:52; CHECK: // %bb.0:53; CHECK-NEXT: ldr q0, [x0]54; CHECK-NEXT: addv s0, v0.4s55; CHECK-NEXT: fmov w0, s056; CHECK-NEXT: ret57 %bin.rdx = load <4 x i32>, ptr %arr58 %r = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %bin.rdx)59 ret i32 %r60}61 62define i64 @add_D(ptr %arr) {63; CHECK-LABEL: add_D:64; CHECK: // %bb.0:65; CHECK-NEXT: ldr q0, [x0]66; CHECK-NEXT: addp d0, v0.2d67; CHECK-NEXT: fmov x0, d068; CHECK-NEXT: ret69 %bin.rdx = load <2 x i64>, ptr %arr70 %r = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %bin.rdx)71 ret i64 %r72}73 74 75define i32 @oversized_ADDV_256(ptr noalias nocapture readonly %arg1, ptr noalias nocapture readonly %arg2) {76; CHECK-SD-LABEL: oversized_ADDV_256:77; CHECK-SD: // %bb.0: // %entry78; CHECK-SD-NEXT: ldr d0, [x0]79; CHECK-SD-NEXT: ldr d1, [x1]80; CHECK-SD-NEXT: uabdl v0.8h, v0.8b, v1.8b81; CHECK-SD-NEXT: uaddlv s0, v0.8h82; CHECK-SD-NEXT: fmov w0, s083; CHECK-SD-NEXT: ret84;85; CHECK-GI-LABEL: oversized_ADDV_256:86; CHECK-GI: // %bb.0: // %entry87; CHECK-GI-NEXT: ldr d1, [x0]88; CHECK-GI-NEXT: ldr d2, [x1]89; CHECK-GI-NEXT: movi v0.2d, #000000000000000090; CHECK-GI-NEXT: usubl v1.8h, v1.8b, v2.8b91; CHECK-GI-NEXT: sshll v2.4s, v1.4h, #092; CHECK-GI-NEXT: sshll2 v3.4s, v1.8h, #093; CHECK-GI-NEXT: ssubw2 v0.4s, v0.4s, v1.8h94; CHECK-GI-NEXT: cmlt v4.4s, v2.4s, #095; CHECK-GI-NEXT: cmlt v5.4s, v3.4s, #096; CHECK-GI-NEXT: neg v6.4s, v2.4s97; CHECK-GI-NEXT: mov v1.16b, v4.16b98; CHECK-GI-NEXT: bif v0.16b, v3.16b, v5.16b99; CHECK-GI-NEXT: bsl v1.16b, v6.16b, v2.16b100; CHECK-GI-NEXT: add v0.4s, v1.4s, v0.4s101; CHECK-GI-NEXT: addv s0, v0.4s102; CHECK-GI-NEXT: fmov w0, s0103; CHECK-GI-NEXT: ret104entry:105 %0 = load <8 x i8>, ptr %arg1, align 1106 %1 = zext <8 x i8> %0 to <8 x i32>107 %2 = load <8 x i8>, ptr %arg2, align 1108 %3 = zext <8 x i8> %2 to <8 x i32>109 %4 = sub nsw <8 x i32> %1, %3110 %5 = icmp slt <8 x i32> %4, zeroinitializer111 %6 = sub nsw <8 x i32> zeroinitializer, %4112 %7 = select <8 x i1> %5, <8 x i32> %6, <8 x i32> %4113 %r = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %7)114 ret i32 %r115}116 117declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)118 119define i32 @oversized_ADDV_512(ptr %arr) {120; CHECK-SD-LABEL: oversized_ADDV_512:121; CHECK-SD: // %bb.0:122; CHECK-SD-NEXT: ldp q0, q1, [x0, #32]123; CHECK-SD-NEXT: ldp q2, q3, [x0]124; CHECK-SD-NEXT: add v1.4s, v3.4s, v1.4s125; CHECK-SD-NEXT: add v0.4s, v2.4s, v0.4s126; CHECK-SD-NEXT: add v0.4s, v0.4s, v1.4s127; CHECK-SD-NEXT: addv s0, v0.4s128; CHECK-SD-NEXT: fmov w0, s0129; CHECK-SD-NEXT: ret130;131; CHECK-GI-LABEL: oversized_ADDV_512:132; CHECK-GI: // %bb.0:133; CHECK-GI-NEXT: ldp q0, q1, [x0]134; CHECK-GI-NEXT: ldp q2, q3, [x0, #32]135; CHECK-GI-NEXT: add v0.4s, v0.4s, v1.4s136; CHECK-GI-NEXT: add v1.4s, v2.4s, v3.4s137; CHECK-GI-NEXT: add v0.4s, v0.4s, v1.4s138; CHECK-GI-NEXT: addv s0, v0.4s139; CHECK-GI-NEXT: fmov w0, s0140; CHECK-GI-NEXT: ret141 %bin.rdx = load <16 x i32>, ptr %arr142 %r = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %bin.rdx)143 ret i32 %r144}145 146define i8 @addv_combine_i8(<8 x i8> %a1, <8 x i8> %a2) {147; CHECK-SD-LABEL: addv_combine_i8:148; CHECK-SD: // %bb.0: // %entry149; CHECK-SD-NEXT: add v0.8b, v0.8b, v1.8b150; CHECK-SD-NEXT: addv b0, v0.8b151; CHECK-SD-NEXT: fmov w0, s0152; CHECK-SD-NEXT: ret153;154; CHECK-GI-LABEL: addv_combine_i8:155; CHECK-GI: // %bb.0: // %entry156; CHECK-GI-NEXT: addv b0, v0.8b157; CHECK-GI-NEXT: addv b1, v1.8b158; CHECK-GI-NEXT: fmov w8, s0159; CHECK-GI-NEXT: fmov w9, s1160; CHECK-GI-NEXT: add w0, w9, w8, uxtb161; CHECK-GI-NEXT: ret162entry:163 %rdx.1 = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %a1)164 %rdx.2 = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %a2)165 %r = add i8 %rdx.1, %rdx.2166 ret i8 %r167}168 169define i16 @addv_combine_i16(<4 x i16> %a1, <4 x i16> %a2) {170; CHECK-SD-LABEL: addv_combine_i16:171; CHECK-SD: // %bb.0: // %entry172; CHECK-SD-NEXT: add v0.4h, v0.4h, v1.4h173; CHECK-SD-NEXT: addv h0, v0.4h174; CHECK-SD-NEXT: fmov w0, s0175; CHECK-SD-NEXT: ret176;177; CHECK-GI-LABEL: addv_combine_i16:178; CHECK-GI: // %bb.0: // %entry179; CHECK-GI-NEXT: addv h0, v0.4h180; CHECK-GI-NEXT: addv h1, v1.4h181; CHECK-GI-NEXT: fmov w8, s0182; CHECK-GI-NEXT: fmov w9, s1183; CHECK-GI-NEXT: add w0, w9, w8, uxth184; CHECK-GI-NEXT: ret185entry:186 %rdx.1 = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %a1)187 %rdx.2 = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %a2)188 %r = add i16 %rdx.1, %rdx.2189 ret i16 %r190}191 192define i32 @addv_combine_i32(<4 x i32> %a1, <4 x i32> %a2) {193; CHECK-SD-LABEL: addv_combine_i32:194; CHECK-SD: // %bb.0: // %entry195; CHECK-SD-NEXT: add v0.4s, v0.4s, v1.4s196; CHECK-SD-NEXT: addv s0, v0.4s197; CHECK-SD-NEXT: fmov w0, s0198; CHECK-SD-NEXT: ret199;200; CHECK-GI-LABEL: addv_combine_i32:201; CHECK-GI: // %bb.0: // %entry202; CHECK-GI-NEXT: addv s0, v0.4s203; CHECK-GI-NEXT: addv s1, v1.4s204; CHECK-GI-NEXT: fmov w8, s0205; CHECK-GI-NEXT: fmov w9, s1206; CHECK-GI-NEXT: add w0, w8, w9207; CHECK-GI-NEXT: ret208entry:209 %rdx.1 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a1)210 %rdx.2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a2)211 %r = add i32 %rdx.1, %rdx.2212 ret i32 %r213}214 215define i64 @addv_combine_i64(<2 x i64> %a1, <2 x i64> %a2) {216; CHECK-SD-LABEL: addv_combine_i64:217; CHECK-SD: // %bb.0: // %entry218; CHECK-SD-NEXT: add v0.2d, v0.2d, v1.2d219; CHECK-SD-NEXT: addp d0, v0.2d220; CHECK-SD-NEXT: fmov x0, d0221; CHECK-SD-NEXT: ret222;223; CHECK-GI-LABEL: addv_combine_i64:224; CHECK-GI: // %bb.0: // %entry225; CHECK-GI-NEXT: addp d0, v0.2d226; CHECK-GI-NEXT: addp d1, v1.2d227; CHECK-GI-NEXT: fmov x8, d0228; CHECK-GI-NEXT: fmov x9, d1229; CHECK-GI-NEXT: add x0, x8, x9230; CHECK-GI-NEXT: ret231entry:232 %rdx.1 = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %a1)233 %rdx.2 = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %a2)234 %r = add i64 %rdx.1, %rdx.2235 ret i64 %r236}237 238define i8 @addv_v2i8(<2 x i8> %a) {239; CHECK-LABEL: addv_v2i8:240; CHECK: // %bb.0: // %entry241; CHECK-NEXT: addp v0.2s, v0.2s, v0.2s242; CHECK-NEXT: fmov w0, s0243; CHECK-NEXT: ret244entry:245 %arg1 = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> %a)246 ret i8 %arg1247}248 249define i8 @addv_v3i8(<3 x i8> %a) {250; CHECK-SD-LABEL: addv_v3i8:251; CHECK-SD: // %bb.0: // %entry252; CHECK-SD-NEXT: movi v0.2d, #0000000000000000253; CHECK-SD-NEXT: mov v0.h[0], w0254; CHECK-SD-NEXT: mov v0.h[1], w1255; CHECK-SD-NEXT: mov v0.h[2], w2256; CHECK-SD-NEXT: addv h0, v0.4h257; CHECK-SD-NEXT: fmov w0, s0258; CHECK-SD-NEXT: ret259;260; CHECK-GI-LABEL: addv_v3i8:261; CHECK-GI: // %bb.0: // %entry262; CHECK-GI-NEXT: fmov s0, w0263; CHECK-GI-NEXT: mov w8, #0 // =0x0264; CHECK-GI-NEXT: mov v0.h[1], w1265; CHECK-GI-NEXT: mov v0.h[2], w2266; CHECK-GI-NEXT: mov v0.h[3], w8267; CHECK-GI-NEXT: addv h0, v0.4h268; CHECK-GI-NEXT: fmov w0, s0269; CHECK-GI-NEXT: ret270entry:271 %arg1 = call i8 @llvm.vector.reduce.add.v3i8(<3 x i8> %a)272 ret i8 %arg1273}274 275define i8 @addv_v4i8(<4 x i8> %a) {276; CHECK-LABEL: addv_v4i8:277; CHECK: // %bb.0: // %entry278; CHECK-NEXT: addv h0, v0.4h279; CHECK-NEXT: fmov w0, s0280; CHECK-NEXT: ret281entry:282 %arg1 = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> %a)283 ret i8 %arg1284}285 286define i8 @addv_v8i8(<8 x i8> %a) {287; CHECK-LABEL: addv_v8i8:288; CHECK: // %bb.0: // %entry289; CHECK-NEXT: addv b0, v0.8b290; CHECK-NEXT: fmov w0, s0291; CHECK-NEXT: ret292entry:293 %arg1 = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %a)294 ret i8 %arg1295}296 297define i8 @addv_v16i8(<16 x i8> %a) {298; CHECK-LABEL: addv_v16i8:299; CHECK: // %bb.0: // %entry300; CHECK-NEXT: addv b0, v0.16b301; CHECK-NEXT: fmov w0, s0302; CHECK-NEXT: ret303entry:304 %arg1 = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %a)305 ret i8 %arg1306}307 308define i8 @addv_v32i8(<32 x i8> %a) {309; CHECK-LABEL: addv_v32i8:310; CHECK: // %bb.0: // %entry311; CHECK-NEXT: add v0.16b, v0.16b, v1.16b312; CHECK-NEXT: addv b0, v0.16b313; CHECK-NEXT: fmov w0, s0314; CHECK-NEXT: ret315entry:316 %arg1 = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> %a)317 ret i8 %arg1318}319 320define i16 @addv_v2i16(<2 x i16> %a) {321; CHECK-LABEL: addv_v2i16:322; CHECK: // %bb.0: // %entry323; CHECK-NEXT: addp v0.2s, v0.2s, v0.2s324; CHECK-NEXT: fmov w0, s0325; CHECK-NEXT: ret326entry:327 %arg1 = call i16 @llvm.vector.reduce.add.v2i16(<2 x i16> %a)328 ret i16 %arg1329}330 331define i16 @addv_v3i16(<3 x i16> %a) {332; CHECK-SD-LABEL: addv_v3i16:333; CHECK-SD: // %bb.0: // %entry334; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0335; CHECK-SD-NEXT: mov v0.h[3], wzr336; CHECK-SD-NEXT: addv h0, v0.4h337; CHECK-SD-NEXT: fmov w0, s0338; CHECK-SD-NEXT: ret339;340; CHECK-GI-LABEL: addv_v3i16:341; CHECK-GI: // %bb.0: // %entry342; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0343; CHECK-GI-NEXT: mov w8, #0 // =0x0344; CHECK-GI-NEXT: mov v0.h[3], w8345; CHECK-GI-NEXT: addv h0, v0.4h346; CHECK-GI-NEXT: fmov w0, s0347; CHECK-GI-NEXT: ret348entry:349 %arg1 = call i16 @llvm.vector.reduce.add.v3i16(<3 x i16> %a)350 ret i16 %arg1351}352 353define i16 @addv_v4i16(<4 x i16> %a) {354; CHECK-LABEL: addv_v4i16:355; CHECK: // %bb.0: // %entry356; CHECK-NEXT: addv h0, v0.4h357; CHECK-NEXT: fmov w0, s0358; CHECK-NEXT: ret359entry:360 %arg1 = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %a)361 ret i16 %arg1362}363 364define i16 @addv_v8i16(<8 x i16> %a) {365; CHECK-LABEL: addv_v8i16:366; CHECK: // %bb.0: // %entry367; CHECK-NEXT: addv h0, v0.8h368; CHECK-NEXT: fmov w0, s0369; CHECK-NEXT: ret370entry:371 %arg1 = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %a)372 ret i16 %arg1373}374 375define i16 @addv_v16i16(<16 x i16> %a) {376; CHECK-LABEL: addv_v16i16:377; CHECK: // %bb.0: // %entry378; CHECK-NEXT: add v0.8h, v0.8h, v1.8h379; CHECK-NEXT: addv h0, v0.8h380; CHECK-NEXT: fmov w0, s0381; CHECK-NEXT: ret382entry:383 %arg1 = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %a)384 ret i16 %arg1385}386 387define i32 @addv_v2i32(<2 x i32> %a) {388; CHECK-LABEL: addv_v2i32:389; CHECK: // %bb.0: // %entry390; CHECK-NEXT: addp v0.2s, v0.2s, v0.2s391; CHECK-NEXT: fmov w0, s0392; CHECK-NEXT: ret393entry:394 %arg1 = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> %a)395 ret i32 %arg1396}397 398define i32 @addv_v3i32(<3 x i32> %a) {399; CHECK-LABEL: addv_v3i32:400; CHECK: // %bb.0: // %entry401; CHECK-NEXT: mov v0.s[3], wzr402; CHECK-NEXT: addv s0, v0.4s403; CHECK-NEXT: fmov w0, s0404; CHECK-NEXT: ret405entry:406 %arg1 = call i32 @llvm.vector.reduce.add.v3i32(<3 x i32> %a)407 ret i32 %arg1408}409 410define i32 @addv_v4i32(<4 x i32> %a) {411; CHECK-LABEL: addv_v4i32:412; CHECK: // %bb.0: // %entry413; CHECK-NEXT: addv s0, v0.4s414; CHECK-NEXT: fmov w0, s0415; CHECK-NEXT: ret416entry:417 %arg1 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a)418 ret i32 %arg1419}420 421define i32 @addv_v8i32(<8 x i32> %a) {422; CHECK-LABEL: addv_v8i32:423; CHECK: // %bb.0: // %entry424; CHECK-NEXT: add v0.4s, v0.4s, v1.4s425; CHECK-NEXT: addv s0, v0.4s426; CHECK-NEXT: fmov w0, s0427; CHECK-NEXT: ret428entry:429 %arg1 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %a)430 ret i32 %arg1431}432 433define i64 @addv_v2i64(<2 x i64> %a) {434; CHECK-LABEL: addv_v2i64:435; CHECK: // %bb.0: // %entry436; CHECK-NEXT: addp d0, v0.2d437; CHECK-NEXT: fmov x0, d0438; CHECK-NEXT: ret439entry:440 %arg1 = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %a)441 ret i64 %arg1442}443 444define i64 @addv_v3i64(<3 x i64> %a) {445; CHECK-SD-LABEL: addv_v3i64:446; CHECK-SD: // %bb.0: // %entry447; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2448; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0449; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1450; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]451; CHECK-SD-NEXT: mov v2.d[1], xzr452; CHECK-SD-NEXT: add v0.2d, v0.2d, v2.2d453; CHECK-SD-NEXT: addp d0, v0.2d454; CHECK-SD-NEXT: fmov x0, d0455; CHECK-SD-NEXT: ret456;457; CHECK-GI-LABEL: addv_v3i64:458; CHECK-GI: // %bb.0: // %entry459; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0460; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2461; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1462; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]463; CHECK-GI-NEXT: mov v2.d[1], xzr464; CHECK-GI-NEXT: add v0.2d, v0.2d, v2.2d465; CHECK-GI-NEXT: addp d0, v0.2d466; CHECK-GI-NEXT: fmov x0, d0467; CHECK-GI-NEXT: ret468entry:469 %arg1 = call i64 @llvm.vector.reduce.add.v3i64(<3 x i64> %a)470 ret i64 %arg1471}472 473define i64 @addv_v4i64(<4 x i64> %a) {474; CHECK-LABEL: addv_v4i64:475; CHECK: // %bb.0: // %entry476; CHECK-NEXT: add v0.2d, v0.2d, v1.2d477; CHECK-NEXT: addp d0, v0.2d478; CHECK-NEXT: fmov x0, d0479; CHECK-NEXT: ret480entry:481 %arg1 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %a)482 ret i64 %arg1483}484 485define i128 @addv_v2i128(<2 x i128> %a) {486; CHECK-LABEL: addv_v2i128:487; CHECK: // %bb.0: // %entry488; CHECK-NEXT: adds x0, x0, x2489; CHECK-NEXT: adc x1, x1, x3490; CHECK-NEXT: ret491entry:492 %arg1 = call i128 @llvm.vector.reduce.add.v2i128(<2 x i128> %a)493 ret i128 %arg1494}495 496define i16 @addv_zero_lanes_v4i16(ptr %arr) {497; CHECK-SD-LABEL: addv_zero_lanes_v4i16:498; CHECK-SD: // %bb.0:499; CHECK-SD-NEXT: ldrb w0, [x0]500; CHECK-SD-NEXT: ret501;502; CHECK-GI-LABEL: addv_zero_lanes_v4i16:503; CHECK-GI: // %bb.0:504; CHECK-GI-NEXT: ldrb w8, [x0]505; CHECK-GI-NEXT: fmov d0, x8506; CHECK-GI-NEXT: addv h0, v0.4h507; CHECK-GI-NEXT: fmov w0, s0508; CHECK-GI-NEXT: ret509 %v = load i64, ptr %arr510 %and = and i64 %v, 255511 %vec = bitcast i64 %and to <4 x i16>512 %r = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %vec)513 ret i16 %r514}515 516define i8 @addv_zero_lanes_v8i8(ptr %arr) {517; CHECK-SD-LABEL: addv_zero_lanes_v8i8:518; CHECK-SD: // %bb.0:519; CHECK-SD-NEXT: ldrb w0, [x0]520; CHECK-SD-NEXT: ret521;522; CHECK-GI-LABEL: addv_zero_lanes_v8i8:523; CHECK-GI: // %bb.0:524; CHECK-GI-NEXT: ldrb w8, [x0]525; CHECK-GI-NEXT: fmov d0, x8526; CHECK-GI-NEXT: addv b0, v0.8b527; CHECK-GI-NEXT: fmov w0, s0528; CHECK-GI-NEXT: ret529 %v = load i64, ptr %arr530 %and = and i64 %v, 255531 %vec = bitcast i64 %and to <8 x i8>532 %r = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %vec)533 ret i8 %r534}535 536define i8 @addv_zero_lanes_negative_v8i8(ptr %arr) {537; CHECK-LABEL: addv_zero_lanes_negative_v8i8:538; CHECK: // %bb.0:539; CHECK-NEXT: ldr x8, [x0]540; CHECK-NEXT: and x8, x8, #0x100541; CHECK-NEXT: fmov d0, x8542; CHECK-NEXT: addv b0, v0.8b543; CHECK-NEXT: fmov w0, s0544; CHECK-NEXT: ret545 %v = load i64, ptr %arr546 %and = and i64 %v, 256547 %vec = bitcast i64 %and to <8 x i8>548 %r = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %vec)549 ret i8 %r550}551 552 553define i8 @addv_zero_lanes_v16i8(ptr %arr) {554; CHECK-SD-LABEL: addv_zero_lanes_v16i8:555; CHECK-SD: // %bb.0:556; CHECK-SD-NEXT: movi v0.2d, #0000000000000000557; CHECK-SD-NEXT: ldrb w8, [x0]558; CHECK-SD-NEXT: mov v0.d[0], x8559; CHECK-SD-NEXT: addv b0, v0.16b560; CHECK-SD-NEXT: fmov w0, s0561; CHECK-SD-NEXT: ret562;563; CHECK-GI-LABEL: addv_zero_lanes_v16i8:564; CHECK-GI: // %bb.0:565; CHECK-GI-NEXT: ldrb w8, [x0]566; CHECK-GI-NEXT: mov v0.d[0], x8567; CHECK-GI-NEXT: mov v0.d[1], xzr568; CHECK-GI-NEXT: addv b0, v0.16b569; CHECK-GI-NEXT: fmov w0, s0570; CHECK-GI-NEXT: ret571 %v = load i128, ptr %arr572 %and = and i128 %v, 255573 %vec = bitcast i128 %and to <16 x i8>574 %r = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %vec)575 ret i8 %r576}577 578define i16 @addv_zero_lanes_v8i16(ptr %arr) {579; CHECK-SD-LABEL: addv_zero_lanes_v8i16:580; CHECK-SD: // %bb.0:581; CHECK-SD-NEXT: movi v0.2d, #0000000000000000582; CHECK-SD-NEXT: ldrh w8, [x0]583; CHECK-SD-NEXT: mov v0.d[0], x8584; CHECK-SD-NEXT: addv h0, v0.8h585; CHECK-SD-NEXT: fmov w0, s0586; CHECK-SD-NEXT: ret587;588; CHECK-GI-LABEL: addv_zero_lanes_v8i16:589; CHECK-GI: // %bb.0:590; CHECK-GI-NEXT: ldrh w8, [x0]591; CHECK-GI-NEXT: mov v0.d[0], x8592; CHECK-GI-NEXT: mov v0.d[1], xzr593; CHECK-GI-NEXT: addv h0, v0.8h594; CHECK-GI-NEXT: fmov w0, s0595; CHECK-GI-NEXT: ret596 %v = load i128, ptr %arr597 %and = and i128 %v, u0xFFFF598 %vec = bitcast i128 %and to <8 x i16>599 %r = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %vec)600 ret i16 %r601}602 603define i32 @addv_zero_lanes_v4i32(ptr %arr) {604; CHECK-SD-LABEL: addv_zero_lanes_v4i32:605; CHECK-SD: // %bb.0:606; CHECK-SD-NEXT: movi v0.2d, #0000000000000000607; CHECK-SD-NEXT: ldr w8, [x0]608; CHECK-SD-NEXT: mov v0.d[0], x8609; CHECK-SD-NEXT: addv s0, v0.4s610; CHECK-SD-NEXT: fmov w0, s0611; CHECK-SD-NEXT: ret612;613; CHECK-GI-LABEL: addv_zero_lanes_v4i32:614; CHECK-GI: // %bb.0:615; CHECK-GI-NEXT: ldr w8, [x0]616; CHECK-GI-NEXT: mov v0.d[0], x8617; CHECK-GI-NEXT: mov v0.d[1], xzr618; CHECK-GI-NEXT: addv s0, v0.4s619; CHECK-GI-NEXT: fmov w0, s0620; CHECK-GI-NEXT: ret621 %v = load i128, ptr %arr622 %and = and i128 %v, u0xFFFFFFFF623 %vec = bitcast i128 %and to <4 x i32>624 %r = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %vec)625 ret i32 %r626}627 628define i32 @addv_zero_lanes_v2i32(ptr %arr) {629; CHECK-SD-LABEL: addv_zero_lanes_v2i32:630; CHECK-SD: // %bb.0:631; CHECK-SD-NEXT: ldr w0, [x0]632; CHECK-SD-NEXT: ret633;634; CHECK-GI-LABEL: addv_zero_lanes_v2i32:635; CHECK-GI: // %bb.0:636; CHECK-GI-NEXT: ldr w8, [x0]637; CHECK-GI-NEXT: fmov d0, x8638; CHECK-GI-NEXT: addp v0.2s, v0.2s, v0.2s639; CHECK-GI-NEXT: fmov w0, s0640; CHECK-GI-NEXT: ret641 %v = load i64, ptr %arr642 %and = and i64 %v, u0xFFFFFFFF643 %vec = bitcast i64 %and to <2 x i32>644 %r = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> %vec)645 ret i32 %r646}647