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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64-unknown-linux-gnu -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5; BIT Bitwise Insert if True6;7; 8-bit vectors tests8 9define <1 x i8> @test_bit_v1i8(<1 x i8> %A, <1 x i8> %B, <1 x i8> %C) {10; CHECK-SD-LABEL: test_bit_v1i8:11; CHECK-SD: // %bb.0:12; CHECK-SD-NEXT: bit v0.8b, v1.8b, v2.8b13; CHECK-SD-NEXT: ret14;15; CHECK-GI-LABEL: test_bit_v1i8:16; CHECK-GI: // %bb.0:17; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q018; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q119; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q220; CHECK-GI-NEXT: umov w8, v2.b[0]21; CHECK-GI-NEXT: umov w9, v1.b[0]22; CHECK-GI-NEXT: umov w10, v0.b[0]23; CHECK-GI-NEXT: and w9, w8, w924; CHECK-GI-NEXT: bic w8, w10, w825; CHECK-GI-NEXT: orr w8, w9, w826; CHECK-GI-NEXT: fmov s0, w827; CHECK-GI-NEXT: ret28 %and = and <1 x i8> %C, %B29 %neg = xor <1 x i8> %C, <i8 -1>30 %and1 = and <1 x i8> %neg, %A31 %or = or <1 x i8> %and, %and132 ret <1 x i8> %or33}34 35; 16-bit vectors tests36 37define <1 x i16> @test_bit_v1i16(<1 x i16> %A, <1 x i16> %B, <1 x i16> %C) {38; CHECK-SD-LABEL: test_bit_v1i16:39; CHECK-SD: // %bb.0:40; CHECK-SD-NEXT: bit v0.8b, v1.8b, v2.8b41; CHECK-SD-NEXT: ret42;43; CHECK-GI-LABEL: test_bit_v1i16:44; CHECK-GI: // %bb.0:45; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q046; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q147; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q248; CHECK-GI-NEXT: umov w8, v2.h[0]49; CHECK-GI-NEXT: umov w9, v1.h[0]50; CHECK-GI-NEXT: umov w10, v0.h[0]51; CHECK-GI-NEXT: and w9, w8, w952; CHECK-GI-NEXT: bic w8, w10, w853; CHECK-GI-NEXT: orr w8, w9, w854; CHECK-GI-NEXT: fmov s0, w855; CHECK-GI-NEXT: ret56 %and = and <1 x i16> %C, %B57 %neg = xor <1 x i16> %C, <i16 -1>58 %and1 = and <1 x i16> %neg, %A59 %or = or <1 x i16> %and, %and160 ret <1 x i16> %or61}62 63; 32-bit vectors tests64 65define <1 x i32> @test_bit_v1i32(<1 x i32> %A, <1 x i32> %B, <1 x i32> %C) {66; CHECK-SD-LABEL: test_bit_v1i32:67; CHECK-SD: // %bb.0:68; CHECK-SD-NEXT: bit v0.8b, v1.8b, v2.8b69; CHECK-SD-NEXT: ret70;71; CHECK-GI-LABEL: test_bit_v1i32:72; CHECK-GI: // %bb.0:73; CHECK-GI-NEXT: fmov w8, s274; CHECK-GI-NEXT: fmov w9, s175; CHECK-GI-NEXT: fmov w10, s076; CHECK-GI-NEXT: and w9, w8, w977; CHECK-GI-NEXT: bic w8, w10, w878; CHECK-GI-NEXT: orr w8, w9, w879; CHECK-GI-NEXT: fmov s0, w880; CHECK-GI-NEXT: ret81 %and = and <1 x i32> %C, %B82 %neg = xor <1 x i32> %C, <i32 -1>83 %and1 = and <1 x i32> %neg, %A84 %or = or <1 x i32> %and, %and185 ret <1 x i32> %or86}87 88; 64-bit vectors tests89 90define <1 x i64> @test_bit_v1i64(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C) {91; CHECK-SD-LABEL: test_bit_v1i64:92; CHECK-SD: // %bb.0:93; CHECK-SD-NEXT: bit v0.8b, v1.8b, v2.8b94; CHECK-SD-NEXT: ret95;96; CHECK-GI-LABEL: test_bit_v1i64:97; CHECK-GI: // %bb.0:98; CHECK-GI-NEXT: fmov x8, d299; CHECK-GI-NEXT: fmov x9, d1100; CHECK-GI-NEXT: fmov x10, d0101; CHECK-GI-NEXT: and x9, x8, x9102; CHECK-GI-NEXT: bic x8, x10, x8103; CHECK-GI-NEXT: orr x8, x9, x8104; CHECK-GI-NEXT: fmov d0, x8105; CHECK-GI-NEXT: ret106 %and = and <1 x i64> %C, %B107 %neg = xor <1 x i64> %C, <i64 -1>108 %and1 = and <1 x i64> %neg, %A109 %or = or <1 x i64> %and, %and1110 ret <1 x i64> %or111}112 113define <2 x i32> @test_bit_v2i32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C) {114; CHECK-LABEL: test_bit_v2i32:115; CHECK: // %bb.0:116; CHECK-NEXT: bit v0.8b, v1.8b, v2.8b117; CHECK-NEXT: ret118 %and = and <2 x i32> %C, %B119 %neg = xor <2 x i32> %C, <i32 -1, i32 -1>120 %and1 = and <2 x i32> %neg, %A121 %or = or <2 x i32> %and, %and1122 ret <2 x i32> %or123}124 125define <4 x i16> @test_bit_v4i16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C) {126; CHECK-LABEL: test_bit_v4i16:127; CHECK: // %bb.0:128; CHECK-NEXT: bit v0.8b, v1.8b, v2.8b129; CHECK-NEXT: ret130 %and = and <4 x i16> %C, %B131 %neg = xor <4 x i16> %C, <i16 -1, i16 -1, i16 -1, i16 -1>132 %and1 = and <4 x i16> %neg, %A133 %or = or <4 x i16> %and, %and1134 ret <4 x i16> %or135}136 137define <8 x i8> @test_bit_v8i8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C) {138; CHECK-LABEL: test_bit_v8i8:139; CHECK: // %bb.0:140; CHECK-NEXT: bit v0.8b, v1.8b, v2.8b141; CHECK-NEXT: ret142 %and = and <8 x i8> %C, %B143 %neg = xor <8 x i8> %C, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>144 %and1 = and <8 x i8> %neg, %A145 %or = or <8 x i8> %and, %and1146 ret <8 x i8> %or147}148 149; 128-bit vectors tests150 151define <2 x i64> @test_bit_v2i64(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C) {152; CHECK-LABEL: test_bit_v2i64:153; CHECK: // %bb.0:154; CHECK-NEXT: bit v0.16b, v1.16b, v2.16b155; CHECK-NEXT: ret156 %and = and <2 x i64> %C, %B157 %neg = xor <2 x i64> %C, <i64 -1, i64 -1>158 %and1 = and <2 x i64> %neg, %A159 %or = or <2 x i64> %and, %and1160 ret <2 x i64> %or161}162 163define <4 x i32> @test_bit_v4i32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {164; CHECK-LABEL: test_bit_v4i32:165; CHECK: // %bb.0:166; CHECK-NEXT: bit v0.16b, v1.16b, v2.16b167; CHECK-NEXT: ret168 %and = and <4 x i32> %C, %B169 %neg = xor <4 x i32> %C, <i32 -1, i32 -1, i32 -1, i32 -1>170 %and1 = and <4 x i32> %neg, %A171 %or = or <4 x i32> %and, %and1172 ret <4 x i32> %or173}174 175define <8 x i16> @test_bit_v8i16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) {176; CHECK-LABEL: test_bit_v8i16:177; CHECK: // %bb.0:178; CHECK-NEXT: bit v0.16b, v1.16b, v2.16b179; CHECK-NEXT: ret180 %and = and <8 x i16> %C, %B181 %neg = xor <8 x i16> %C, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>182 %and1 = and <8 x i16> %neg, %A183 %or = or <8 x i16> %and, %and1184 ret <8 x i16> %or185}186 187define <16 x i8> @test_bit_v16i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) {188; CHECK-LABEL: test_bit_v16i8:189; CHECK: // %bb.0:190; CHECK-NEXT: bit v0.16b, v1.16b, v2.16b191; CHECK-NEXT: ret192 %and = and <16 x i8> %C, %B193 %neg = xor <16 x i8> %C, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>194 %and1 = and <16 x i8> %neg, %A195 %or = or <16 x i8> %and, %and1196 ret <16 x i8> %or197}198 199define <4 x i32> @test_bit_sink_operand(<4 x i32> %src, <4 x i32> %dst, <4 x i32> %mask, i32 %scratch) {200; CHECK-SD-LABEL: test_bit_sink_operand:201; CHECK-SD: // %bb.0: // %entry202; CHECK-SD-NEXT: sub sp, sp, #32203; CHECK-SD-NEXT: .cfi_def_cfa_offset 32204; CHECK-SD-NEXT: add w8, w0, w0, lsr #31205; CHECK-SD-NEXT: mov w9, wzr206; CHECK-SD-NEXT: asr w8, w8, #1207; CHECK-SD-NEXT: .LBB11_1: // %do.body208; CHECK-SD-NEXT: // =>This Inner Loop Header: Depth=1209; CHECK-SD-NEXT: bit v1.16b, v0.16b, v2.16b210; CHECK-SD-NEXT: add x10, sp, #16211; CHECK-SD-NEXT: mov x11, sp212; CHECK-SD-NEXT: bfi x10, x9, #2, #2213; CHECK-SD-NEXT: bfi x11, x9, #2, #2214; CHECK-SD-NEXT: add w9, w9, #1215; CHECK-SD-NEXT: cmp w9, #5216; CHECK-SD-NEXT: str q1, [sp, #16]217; CHECK-SD-NEXT: str w0, [x10]218; CHECK-SD-NEXT: ldr q1, [sp, #16]219; CHECK-SD-NEXT: str q0, [sp]220; CHECK-SD-NEXT: str w8, [x11]221; CHECK-SD-NEXT: ldr q0, [sp]222; CHECK-SD-NEXT: b.ne .LBB11_1223; CHECK-SD-NEXT: // %bb.2: // %do.end224; CHECK-SD-NEXT: mov v0.16b, v1.16b225; CHECK-SD-NEXT: add sp, sp, #32226; CHECK-SD-NEXT: ret227;228; CHECK-GI-LABEL: test_bit_sink_operand:229; CHECK-GI: // %bb.0: // %entry230; CHECK-GI-NEXT: sub sp, sp, #32231; CHECK-GI-NEXT: .cfi_def_cfa_offset 32232; CHECK-GI-NEXT: asr w9, w0, #31233; CHECK-GI-NEXT: mov w8, wzr234; CHECK-GI-NEXT: add x10, sp, #16235; CHECK-GI-NEXT: mov x11, sp236; CHECK-GI-NEXT: add w9, w0, w9, lsr #31237; CHECK-GI-NEXT: asr w9, w9, #1238; CHECK-GI-NEXT: .LBB11_1: // %do.body239; CHECK-GI-NEXT: // =>This Inner Loop Header: Depth=1240; CHECK-GI-NEXT: bit v1.16b, v0.16b, v2.16b241; CHECK-GI-NEXT: mov w12, w8242; CHECK-GI-NEXT: add w8, w8, #1243; CHECK-GI-NEXT: and x12, x12, #0x3244; CHECK-GI-NEXT: cmp w8, #5245; CHECK-GI-NEXT: str q1, [sp, #16]246; CHECK-GI-NEXT: str w0, [x10, x12, lsl #2]247; CHECK-GI-NEXT: ldr q1, [sp, #16]248; CHECK-GI-NEXT: str q0, [sp]249; CHECK-GI-NEXT: str w9, [x11, x12, lsl #2]250; CHECK-GI-NEXT: ldr q0, [sp]251; CHECK-GI-NEXT: b.ne .LBB11_1252; CHECK-GI-NEXT: // %bb.2: // %do.end253; CHECK-GI-NEXT: mov v0.16b, v1.16b254; CHECK-GI-NEXT: add sp, sp, #32255; CHECK-GI-NEXT: ret256 257entry:258 %0 = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>259 %div = sdiv i32 %scratch, 2260 br label %do.body261 262do.body:263 %dst.addr.0 = phi <4 x i32> [ %dst, %entry ], [ %vecins, %do.body ]264 %src.addr.0 = phi <4 x i32> [ %src, %entry ], [ %vecins1, %do.body ]265 %i.0 = phi i32 [ 0, %entry ], [ %inc, %do.body ]266 %vbsl3.i = and <4 x i32> %src.addr.0, %mask267 %vbsl4.i = and <4 x i32> %dst.addr.0, %0268 %vbsl5.i = or <4 x i32> %vbsl3.i, %vbsl4.i269 %vecins = insertelement <4 x i32> %vbsl5.i, i32 %scratch, i32 %i.0270 %vecins1 = insertelement <4 x i32> %src.addr.0, i32 %div, i32 %i.0271 %inc = add nuw nsw i32 %i.0, 1272 %exitcond.not = icmp eq i32 %inc, 5273 br i1 %exitcond.not, label %do.end, label %do.body274 275do.end:276 ret <4 x i32> %vecins277}278