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1; RUN: llc < %s | FileCheck --check-prefix AS %s2; RUN: opt -S -interleaved-load-combine < %s | FileCheck %s3; RUN: opt -S -passes=interleaved-load-combine < %s | FileCheck %s4 5; ModuleID = 'aarch64_interleaved-ld-combine.bc'6target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"7target triple = "arm64--linux-gnu"8 9; This should be lowered into LD410define void @aarch64_ilc_const(ptr %ptr) {11entry:12 13;;; Check LLVM transformation14; CHECK-LABEL: @aarch64_ilc_const(15; CHECK-DAG: [[GEP:%.+]] = getelementptr inbounds <4 x float>, ptr %ptr, i64 216; CHECK-DAG: [[LOAD:%.+]] = load <16 x float>, ptr [[GEP]], align 1617; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>18; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> poison, <4 x i32> <i32 1, i32 5, i32 9, i32 13>19; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> poison, <4 x i32> <i32 2, i32 6, i32 10, i32 14>20; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> poison, <4 x i32> <i32 3, i32 7, i32 11, i32 15>21; CHECK: ret void22 23;;; Check if it gets lowerd24; AS-LABEL: aarch64_ilc_const25; AS: ld426; AS: ret27 28 %gep1 = getelementptr inbounds <4 x float>, ptr %ptr, i64 229 %gep2 = getelementptr inbounds <4 x float>, ptr %ptr, i64 330 %gep3 = getelementptr inbounds <4 x float>, ptr %ptr, i64 431 %gep4 = getelementptr inbounds <4 x float>, ptr %ptr, i64 532 %ld1 = load <4 x float>, ptr %gep1, align 1633 %ld2 = load <4 x float>, ptr %gep2, align 1634 %ld3 = load <4 x float>, ptr %gep3, align 1635 %ld4 = load <4 x float>, ptr %gep4, align 1636 %sv1 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 0, i32 1, i32 4, i32 5>37 %sv2 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>38 %sv3 = shufflevector <4 x float> %ld3, <4 x float> %ld4, <4 x i32> <i32 0, i32 1, i32 4, i32 5>39 %sv4 = shufflevector <4 x float> %ld3, <4 x float> %ld4, <4 x i32> <i32 2, i32 3, i32 6, i32 7>40 %m0_3 = shufflevector <4 x float> %sv1, <4 x float> %sv3, <4 x i32> <i32 0, i32 2, i32 4, i32 6>41 %m4_7 = shufflevector <4 x float> %sv1, <4 x float> %sv3, <4 x i32> <i32 1, i32 3, i32 5, i32 7>42 %m8_11 = shufflevector <4 x float> %sv2, <4 x float> %sv4, <4 x i32> <i32 0, i32 2, i32 4, i32 6>43 %m12_15 = shufflevector <4 x float> %sv2, <4 x float> %sv4, <4 x i32> <i32 1, i32 3, i32 5, i32 7>44 45 store <4 x float> %m0_3, ptr %gep1, align 1646 store <4 x float> %m4_7, ptr %gep2, align 1647 store <4 x float> %m8_11, ptr %gep3, align 1648 store <4 x float> %m12_15, ptr %gep4, align 1649 ret void50}51 52; This should be lowered into LD453define void @aarch64_ilc_idx(ptr %ptr, i64 %idx) {54entry:55 56;;; Check LLVM transformation57; CHECK-LABEL: @aarch64_ilc_idx(58; CHECK-DAG: [[ADD:%.+]] = add i64 %idx, 1659; CHECK-DAG: [[LSHR:%.+]] = lshr i64 [[ADD]], 260; CHECK-DAG: [[GEP:%.+]] = getelementptr inbounds <4 x float>, ptr %ptr, i64 [[LSHR]]61; CHECK-DAG: [[LOAD:%.+]] = load <16 x float>, ptr [[GEP]], align 1662; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>63; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> poison, <4 x i32> <i32 1, i32 5, i32 9, i32 13>64; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> poison, <4 x i32> <i32 2, i32 6, i32 10, i32 14>65; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> poison, <4 x i32> <i32 3, i32 7, i32 11, i32 15>66; CHECK: ret void67 68; AS-LABEL: aarch64_ilc_idx69; AS-DAG: lsl [[LSL:x[0-9]+]], x1, #270; AS-DAG: add [[ADD:x[0-9]+]], [[LSL]], #6471; AS-DAG: and [[AND:x[0-9]+]], [[ADD]], #0xfffffffffffffff072; AS-DAG: add [[ADR:x[0-9]+]], x0, [[AND]]73; AS-DAG: ld4 { v[[V0:[0-9]+]].4s, v[[V1:[0-9]+]].4s, v[[V2:[0-9]+]].4s, v[[V3:[0-9]+]].4s }, [[[ADR]]]74; AS-DAG: str q[[V0]]75; AS-DAG: str q[[V1]]76; AS-DAG: str q[[V2]]77; AS-DAG: str q[[V3]]78; AS: ret79 80 %a2 = add i64 %idx, 2081 %idx2 = lshr i64 %a2, 282 %a3 = add i64 %idx, 2483 %a1 = add i64 %idx, 1684 %idx1 = lshr i64 %a1, 285 %idx3 = lshr i64 %a3, 286 %a4 = add i64 %idx, 2887 %idx4 = lshr i64 %a4, 288 89 %gep2 = getelementptr inbounds <4 x float>, ptr %ptr, i64 %idx290 %gep4 = getelementptr inbounds <4 x float>, ptr %ptr, i64 %idx491 %gep1 = getelementptr inbounds <4 x float>, ptr %ptr, i64 %idx192 %gep3 = getelementptr inbounds <4 x float>, ptr %ptr, i64 %idx393 %ld1 = load <4 x float>, ptr %gep1, align 1694 %ld2 = load <4 x float>, ptr %gep2, align 1695 %ld3 = load <4 x float>, ptr %gep3, align 1696 %ld4 = load <4 x float>, ptr %gep4, align 1697 %sv1 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 0, i32 1, i32 4, i32 5>98 %sv2 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>99 %sv3 = shufflevector <4 x float> %ld3, <4 x float> %ld4, <4 x i32> <i32 0, i32 1, i32 4, i32 5>100 %sv4 = shufflevector <4 x float> %ld3, <4 x float> %ld4, <4 x i32> <i32 2, i32 3, i32 6, i32 7>101 %m0_3 = shufflevector <4 x float> %sv1, <4 x float> %sv3, <4 x i32> <i32 0, i32 2, i32 4, i32 6>102 %m4_7 = shufflevector <4 x float> %sv1, <4 x float> %sv3, <4 x i32> <i32 1, i32 3, i32 5, i32 7>103 %m8_11 = shufflevector <4 x float> %sv2, <4 x float> %sv4, <4 x i32> <i32 0, i32 2, i32 4, i32 6>104 %m12_15 = shufflevector <4 x float> %sv2, <4 x float> %sv4, <4 x i32> <i32 1, i32 3, i32 5, i32 7>105 106 store <4 x float> %m0_3, ptr %gep1, align 16107 store <4 x float> %m4_7, ptr %gep2, align 16108 store <4 x float> %m8_11, ptr %gep3, align 16109 store <4 x float> %m12_15, ptr %gep4, align 16110 ret void111}112 113; This should be lowered into LD4, a offset of has to be taken into account114%struct.ilc = type <{ float, [0 x <4 x float>] }>115define void @aarch64_ilc_struct(ptr %ptr, i64 %idx) {116entry:117 118;;; Check LLVM transformation119; CHECK-LABEL: @aarch64_ilc_struct(120; CHECK-DAG: [[LSHR:%.+]] = lshr i64 %idx, 2121; CHECK-DAG: [[GEP:%.+]] = getelementptr %struct.ilc, ptr %ptr, i32 0, i32 1, i64 [[LSHR]]122; CHECK-DAG: [[LOAD:%.+]] = load <16 x float>, ptr [[GEP]], align 4123; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>124; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> poison, <4 x i32> <i32 1, i32 5, i32 9, i32 13>125; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> poison, <4 x i32> <i32 2, i32 6, i32 10, i32 14>126; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> poison, <4 x i32> <i32 3, i32 7, i32 11, i32 15>127; CHECK: ret void128 129; AS-LABEL: aarch64_ilc_struct130; AS-DAG: lsl [[LSL:x[0-9]+]], x1, #2131; AS-DAG: add [[ADD:x[0-9]+]], x0, #4132; AS-DAG: and [[AND:x[0-9]+]], [[LSL]], #0xfffffffffffffff0133; AS-DAG: add [[ADR:x[0-9]+]], [[ADD]], [[AND]]134; AS-DAG: ld4 { v[[V0:[0-9]+]].4s, v[[V1:[0-9]+]].4s, v[[V2:[0-9]+]].4s, v[[V3:[0-9]+]].4s }, [[[ADR]]]135; AS-DAG: str q[[V0]]136; AS-DAG: str q[[V1]]137; AS-DAG: str q[[V2]]138; AS-DAG: str q[[V3]]139; AS: ret140 141 %a1 = add i64 %idx, 4142 %idx2 = lshr i64 %a1, 2143 %a2 = add i64 %idx, 8144 %idx3 = lshr i64 %a2, 2145 %a3 = add i64 %idx, 12146 %idx4 = lshr i64 %a3, 2147 148 %gep2 = getelementptr %struct.ilc, ptr %ptr, i32 0, i32 1, i64 %idx2149 %gep3 = getelementptr %struct.ilc, ptr %ptr, i32 0, i32 1, i64 %idx3150 %gep4 = getelementptr %struct.ilc, ptr %ptr, i32 0, i32 1, i64 %idx4151 %idx1 = lshr i64 %idx, 2152 %gep1 = getelementptr %struct.ilc, ptr %ptr, i32 0, i32 1, i64 %idx1153 %ld1 = load <4 x float>, ptr %gep1, align 4154 %ld2 = load <4 x float>, ptr %gep2, align 4155 %ld3 = load <4 x float>, ptr %gep3, align 4156 %ld4 = load <4 x float>, ptr %gep4, align 4157 %sv1 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 0, i32 1, i32 4, i32 5>158 %sv2 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>159 %sv3 = shufflevector <4 x float> %ld3, <4 x float> %ld4, <4 x i32> <i32 0, i32 1, i32 4, i32 5>160 %sv4 = shufflevector <4 x float> %ld3, <4 x float> %ld4, <4 x i32> <i32 2, i32 3, i32 6, i32 7>161 %m0_3 = shufflevector <4 x float> %sv1, <4 x float> %sv3, <4 x i32> <i32 0, i32 2, i32 4, i32 6>162 %m4_7 = shufflevector <4 x float> %sv1, <4 x float> %sv3, <4 x i32> <i32 1, i32 3, i32 5, i32 7>163 %m8_11 = shufflevector <4 x float> %sv2, <4 x float> %sv4, <4 x i32> <i32 0, i32 2, i32 4, i32 6>164 %m12_15 = shufflevector <4 x float> %sv2, <4 x float> %sv4, <4 x i32> <i32 1, i32 3, i32 5, i32 7>165 166 store <4 x float> %m0_3, ptr %gep1, align 16167 store <4 x float> %m4_7, ptr %gep2, align 16168 store <4 x float> %m8_11, ptr %gep3, align 16169 store <4 x float> %m12_15, ptr %gep4, align 16170 ret void171}172 173; This should be lowered into LD2174define void @aarch64_ilc_idx_ld2(ptr %ptr, i64 %idx) {175entry:176; CHECK-LABEL: @aarch64_ilc_idx_ld2(177; CHECK-DAG: [[LSHR:%.+]] = lshr i64 %idx, 2178; CHECK-DAG: [[GEP:%.+]] = getelementptr inbounds <4 x float>, ptr %ptr, i64 [[LSHR]]179; CHECK-DAG: [[LOAD:%.+]] = load <8 x float>, ptr [[GEP]], align 16180; CHECK: %{{.* }}= shufflevector <8 x float> [[LOAD]], <8 x float> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>181; CHECK: %{{.* }}= shufflevector <8 x float> [[LOAD]], <8 x float> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>182; CHECK-DAG: ret void183 184; AS-LABEL: aarch64_ilc_idx_ld2185; AS: ld2186; AS: ret187 188 %idx1 = lshr i64 %idx, 2189 %a1 = add i64 %idx, 4190 %idx2 = lshr i64 %a1, 2191 192 %gep1 = getelementptr inbounds <4 x float>, ptr %ptr, i64 %idx1193 %gep2 = getelementptr inbounds <4 x float>, ptr %ptr, i64 %idx2194 %ld1 = load <4 x float>, ptr %gep1, align 16195 %ld2 = load <4 x float>, ptr %gep2, align 16196 %m0_3 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>197 %m4_7 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>198 199 store <4 x float> %m0_3, ptr %gep1200 store <4 x float> %m4_7, ptr %gep2201 ret void202}203 204; This should be lowered into LD3205define void @aarch64_ilc_idx_ld3(ptr %ptr, i64 %idx) {206entry:207; CHECK-LABEL: @aarch64_ilc_idx_ld3(208; CHECK-DAG: [[LSHR:%.+]] = lshr i64 %idx, 2209; CHECK-DAG: [[GEP:%.+]] = getelementptr inbounds <4 x float>, ptr %ptr, i64 [[LSHR]]210; CHECK-DAG: [[LOAD:%.+]] = load <12 x float>, ptr [[GEP]], align 16211; CHECK: %{{.* }}= shufflevector <12 x float> [[LOAD]], <12 x float> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>212; CHECK: %{{.* }}= shufflevector <12 x float> [[LOAD]], <12 x float> poison, <4 x i32> <i32 1, i32 4, i32 7, i32 10>213; CHECK: %{{.* }}= shufflevector <12 x float> [[LOAD]], <12 x float> poison, <4 x i32> <i32 2, i32 5, i32 8, i32 11>214; CHECK-DAG: ret void215 216; AS-LABEL: aarch64_ilc_idx_ld3217; AS: ld3218; AS: ret219 220 %idx1 = lshr i64 %idx, 2221 %a1 = add i64 %idx, 4222 %idx2 = lshr i64 %a1, 2223 %a2 = add i64 %idx, 8224 %idx3 = lshr i64 %a2, 2225 226 %gep1 = getelementptr inbounds <4 x float>, ptr %ptr, i64 %idx1227 %gep2 = getelementptr inbounds <4 x float>, ptr %ptr, i64 %idx2228 %gep3 = getelementptr inbounds <4 x float>, ptr %ptr, i64 %idx3229 %ld1 = load <4 x float>, ptr %gep1, align 16230 %ld2 = load <4 x float>, ptr %gep2, align 16231 %ld3 = load <4 x float>, ptr %gep3, align 16232 233 %sv1 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 0, i32 3, i32 6, i32 undef>234 %sv2 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 1, i32 4, i32 7, i32 undef>235 %sv3 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 2, i32 5, i32 undef, i32 undef>236 %m0_3 = shufflevector <4 x float> %sv1, <4 x float> %ld3, <4 x i32> <i32 0, i32 1, i32 2, i32 5>237 %m4_7 = shufflevector <4 x float> %sv2, <4 x float> %ld3, <4 x i32> <i32 0, i32 1, i32 2, i32 6>238 %m8_11 = shufflevector <4 x float> %sv3, <4 x float> %ld3, <4 x i32> <i32 0, i32 1, i32 4, i32 7>239 240 store <4 x float> %m0_3, ptr %gep1, align 16241 store <4 x float> %m4_7, ptr %gep2, align 16242 store <4 x float> %m8_11, ptr %gep3, align 16243 ret void244}245; %sv3 = shufflevector <4 x float> %ld3, <4 x float> %ld4, <4 x i32> <i32 0, i32 undef, i32 4, i32 undef>246 247; This must not be lowered248define void @aarch64_ilc_i32_idx(ptr %ptr, i32 %idx) {249; CHECK-LABEL: @aarch64_ilc_i32_idx(250; CHECK: %idx1 = lshr i32 %idx, 2251; CHECK-NEXT: %a1 = add i32 %idx, 4252; CHECK-NEXT: %idx2 = lshr i32 %a1, 2253; CHECK-NEXT: %gep1 = getelementptr inbounds <4 x float>, ptr %ptr, i32 %idx1254; CHECK-NEXT: %gep2 = getelementptr inbounds <4 x float>, ptr %ptr, i32 %idx2255; CHECK-NEXT: %ld1 = load <4 x float>, ptr %gep1, align 16256; CHECK-NEXT: %ld2 = load <4 x float>, ptr %gep2, align 16257; CHECK-NEXT: %m0_3 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>258; CHECK-NEXT: %m4_7 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>259; CHECK-NEXT: store <4 x float> %m0_3, ptr %gep1, align 16260; CHECK-NEXT: store <4 x float> %m4_7, ptr %gep2, align 16261; CHECK-NEXT: ret void262 263; AS-LABEL: aarch64_ilc_i32_idx264; AS-DAG: @function265; AS-NOT: ld2266; AS-NOT: ld3267; AS-NOT: ld4268; AS-DAG: ret269 270entry:271 %idx1 = lshr i32 %idx, 2272 %a1 = add i32 %idx, 4273 %idx2 = lshr i32 %a1, 2274 275 %gep1 = getelementptr inbounds <4 x float>, ptr %ptr, i32 %idx1276 %gep2 = getelementptr inbounds <4 x float>, ptr %ptr, i32 %idx2277 %ld1 = load <4 x float>, ptr %gep1, align 16278 %ld2 = load <4 x float>, ptr %gep2, align 16279 %m0_3 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>280 %m4_7 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>281 282 store <4 x float> %m0_3, ptr %gep1, align 16283 store <4 x float> %m4_7, ptr %gep2, align 16284 ret void285}286 287; Volatile loads must not be lowered288define void @aarch64_ilc_volatile(ptr %ptr) {289; CHECK-LABEL: @aarch64_ilc_volatile(290; CHECK: %gep2 = getelementptr inbounds <4 x float>, ptr %ptr, i32 1291; CHECK-NEXT: %ld1 = load volatile <4 x float>, ptr %ptr, align 16292; CHECK-NEXT: %ld2 = load <4 x float>, ptr %gep2, align 16293; CHECK-NEXT: %m0_3 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>294; CHECK-NEXT: %m4_7 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>295; CHECK-NEXT: store <4 x float> %m0_3, ptr %ptr, align 16296; CHECK-NEXT: store <4 x float> %m4_7, ptr %gep2, align 16297; CHECK-NEXT: ret void298 299; AS-LABEL: aarch64_ilc_volatile300; AS-DAG: @function301; AS-NOT: ld2302; AS-NOT: ld3303; AS-NOT: ld4304; AS-DAG: ret305 306entry:307 %gep2 = getelementptr inbounds <4 x float>, ptr %ptr, i32 1308 %ld1 = load volatile <4 x float>, ptr %ptr, align 16309 %ld2 = load <4 x float>, ptr %gep2, align 16310 %m0_3 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>311 %m4_7 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>312 store <4 x float> %m0_3, ptr %ptr, align 16313 store <4 x float> %m4_7, ptr %gep2, align 16314 ret void315}316 317; This must not be lowered318define void @aarch64_ilc_depmem(ptr %ptr, i32 %idx) {319entry:320; CHECK-LABEL: @aarch64_ilc_depmem(321; CHECK: %gep2 = getelementptr inbounds <4 x float>, ptr %ptr, i32 1322; CHECK-NEXT: %ld1 = load <4 x float>, ptr %ptr, align 16323; CHECK-NEXT: store <4 x float> %ld1, ptr %gep2, align 16324; CHECK-NEXT: %ld2 = load <4 x float>, ptr %gep2, align 16325; CHECK-NEXT: %m0_3 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>326; CHECK-NEXT: %m4_7 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>327; CHECK-NEXT: store <4 x float> %m0_3, ptr %ptr, align 16328; CHECK-NEXT: store <4 x float> %m4_7, ptr %gep2, align 16329; CHECK-NEXT: ret void330 331; AS-LABEL: aarch64_ilc_depmem332; AS-DAG: @function333; AS-NOT: ld2334; AS-NOT: ld3335; AS-NOT: ld4336; AS-DAG: ret337 338 %gep2 = getelementptr inbounds <4 x float>, ptr %ptr, i32 1339 %ld1 = load <4 x float>, ptr %ptr, align 16340 store <4 x float> %ld1, ptr %gep2, align 16341 %ld2 = load <4 x float>, ptr %gep2, align 16342 %m0_3 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>343 %m4_7 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>344 345 store <4 x float> %m0_3, ptr %ptr, align 16346 store <4 x float> %m4_7, ptr %gep2, align 16347 ret void348}349 350; This cannot be converted - insertion position cannot be determined351define void @aarch64_no_insertion_pos(ptr %ptr) {352entry:353; CHECK-LABEL: @aarch64_no_insertion_pos(354; CHECK: %p1 = getelementptr inbounds float, ptr %ptr, i32 4355; CHECK-NEXT: %l0 = load <5 x float>, ptr %ptr356; CHECK-NEXT: %l1 = load <5 x float>, ptr %p1357; CHECK-NEXT: %s0 = shufflevector <5 x float> %l0, <5 x float> %l1, <4 x i32> <i32 1, i32 3, i32 6, i32 8>358; CHECK-NEXT: %s1 = shufflevector <5 x float> %l0, <5 x float> %l1, <4 x i32> <i32 2, i32 4, i32 7, i32 9>359; CHECK-NEXT: ret void360 361 %p1 = getelementptr inbounds float, ptr %ptr, i32 4362 %l0 = load <5 x float>, ptr %ptr363 %l1 = load <5 x float>, ptr %p1364 %s0 = shufflevector <5 x float> %l0, <5 x float> %l1, <4 x i32> <i32 1, i32 3, i32 6, i32 8>365 %s1 = shufflevector <5 x float> %l0, <5 x float> %l1, <4 x i32> <i32 2, i32 4, i32 7, i32 9>366 ret void367}368 369; This cannot be converted - the insertion position does not dominate all370; uses371define void @aarch64_insertpos_does_not_dominate(ptr %ptr) {372entry:373; CHECK-LABEL: @aarch64_insertpos_does_not_dominate(374; CHECK: %p1 = getelementptr inbounds float, ptr %ptr, i32 1375; CHECK-NEXT: %l1 = load <7 x float>, ptr %p1376; CHECK-NEXT: %s1 = shufflevector <7 x float> %l1, <7 x float> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>377; CHECK-NEXT: %l0 = load <7 x float>, ptr %ptr378; CHECK-NEXT: %s0 = shufflevector <7 x float> %l0, <7 x float> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>379; CHECK-NEXT: ret void380 %p1 = getelementptr inbounds float, ptr %ptr, i32 1381 %l1 = load <7 x float>, ptr %p1382 %s1 = shufflevector <7 x float> %l1, <7 x float> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>383 %l0 = load <7 x float>, ptr %ptr384 %s0 = shufflevector <7 x float> %l0, <7 x float> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>385 ret void386}387