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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-- -o - < %s | FileCheck %s3 4; Verify that we can fold csneg/csel into csinc instruction.5 6target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"7target triple = "aarch64-unknown-linux-gnu"8 9; int csinc1 (int a, int b) { return !a ? b+3 : b+1; }10define i32 @csinc1(i32 %a, i32 %b) {11; CHECK-LABEL: csinc1:12; CHECK: // %bb.0: // %entry13; CHECK-NEXT: cmp w0, #014; CHECK-NEXT: add w8, w1, #315; CHECK-NEXT: csinc w0, w8, w1, eq16; CHECK-NEXT: ret17entry:18 %tobool.not = icmp eq i32 %a, 019 %cond.v = select i1 %tobool.not, i32 3, i32 120 %cond = add nsw i32 %cond.v, %b21 ret i32 %cond22}23 24; int csinc2 (int a, int b) { return a ? b+3 : b+1; }25define i32 @csinc2(i32 %a, i32 %b) {26; CHECK-LABEL: csinc2:27; CHECK: // %bb.0: // %entry28; CHECK-NEXT: cmp w0, #029; CHECK-NEXT: add w8, w1, #330; CHECK-NEXT: csinc w0, w8, w1, ne31; CHECK-NEXT: ret32entry:33 %tobool.not = icmp eq i32 %a, 034 %cond.v = select i1 %tobool.not, i32 1, i32 335 %cond = add nsw i32 %cond.v, %b36 ret i32 %cond37}38 39; int csinc3 (int a, int b) { return !a ? b+1 : b-3; }40define i32 @csinc3(i32 %a, i32 %b) {41; CHECK-LABEL: csinc3:42; CHECK: // %bb.0: // %entry43; CHECK-NEXT: sub w8, w1, #344; CHECK-NEXT: cmp w0, #045; CHECK-NEXT: csinc w0, w8, w1, ne46; CHECK-NEXT: ret47entry:48 %tobool.not = icmp eq i32 %a, 049 %cond.v = select i1 %tobool.not, i32 1, i32 -350 %cond = add nsw i32 %cond.v, %b51 ret i32 %cond52}53 54; int csinc4 (int a, int b) { return a ? b+1 : b-3; }55define i32 @csinc4(i32 %a, i32 %b) {56; CHECK-LABEL: csinc4:57; CHECK: // %bb.0: // %entry58; CHECK-NEXT: sub w8, w1, #359; CHECK-NEXT: cmp w0, #060; CHECK-NEXT: csinc w0, w8, w1, eq61; CHECK-NEXT: ret62entry:63 %tobool.not = icmp eq i32 %a, 064 %cond.v = select i1 %tobool.not, i32 -3, i32 165 %cond = add nsw i32 %cond.v, %b66 ret i32 %cond67}68 69; int csinc5 (int a, int b) { return a ? b+1 : b-4095; }70define i32 @csinc5(i32 %a, i32 %b) {71; CHECK-LABEL: csinc5:72; CHECK: // %bb.0: // %entry73; CHECK-NEXT: sub w8, w1, #409574; CHECK-NEXT: cmp w0, #075; CHECK-NEXT: csinc w0, w8, w1, eq76; CHECK-NEXT: ret77entry:78 %tobool.not = icmp eq i32 %a, 079 %cond.v = select i1 %tobool.not, i32 -4095, i32 180 %cond = add nsw i32 %cond.v, %b81 ret i32 %cond82}83 84; int csinc6 (int a, int b) { return a ? b+1 : b-4096; }85define i32 @csinc6(i32 %a, i32 %b) {86; CHECK-LABEL: csinc6:87; CHECK: // %bb.0: // %entry88; CHECK-NEXT: sub w8, w1, #1, lsl #12 // =409689; CHECK-NEXT: cmp w0, #090; CHECK-NEXT: csinc w0, w8, w1, eq91; CHECK-NEXT: ret92entry:93 %tobool.not = icmp eq i32 %a, 094 %cond.v = select i1 %tobool.not, i32 -4096, i32 195 %cond = add nsw i32 %cond.v, %b96 ret i32 %cond97}98 99; prevent larger constants (the add laid after csinc)100; int csinc7 (int a, int b) { return a ? b+1 : b-4097; }101define i32 @csinc7(i32 %a, i32 %b) {102; CHECK-LABEL: csinc7:103; CHECK: // %bb.0: // %entry104; CHECK-NEXT: mov w8, #-4097 // =0xffffefff105; CHECK-NEXT: cmp w0, #0106; CHECK-NEXT: csinc w8, w8, wzr, eq107; CHECK-NEXT: add w0, w8, w1108; CHECK-NEXT: ret109entry:110 %tobool.not = icmp eq i32 %a, 0111 %cond.v = select i1 %tobool.not, i32 -4097, i32 1112 %cond = add nsw i32 %cond.v, %b113 ret i32 %cond114}115 116; int csinc8 (int a, int b) { return a ? b-1 : b+1; }117define i32 @csinc8(i32 %a, i32 %b) {118; CHECK-LABEL: csinc8:119; CHECK: // %bb.0: // %entry120; CHECK-NEXT: sub w8, w1, #1121; CHECK-NEXT: cmp w0, #0122; CHECK-NEXT: csinc w0, w8, w1, ne123; CHECK-NEXT: ret124entry:125 %tobool.not = icmp eq i32 %a, 0126 %cond.v = select i1 %tobool.not, i32 1, i32 -1127 %cond = add nsw i32 %cond.v, %b128 ret i32 %cond129}130 131; int csinc9 (int a, int b) { return a ? b+1 : b-1; }132define i32 @csinc9(i32 %a, i32 %b) {133; CHECK-LABEL: csinc9:134; CHECK: // %bb.0: // %entry135; CHECK-NEXT: sub w8, w1, #1136; CHECK-NEXT: cmp w0, #0137; CHECK-NEXT: csinc w0, w8, w1, eq138; CHECK-NEXT: ret139entry:140 %tobool.not = icmp eq i32 %a, 0141 %cond.v = select i1 %tobool.not, i32 -1, i32 1142 %cond = add nsw i32 %cond.v, %b143 ret i32 %cond144}145