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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5declare <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16>, <8 x i16>)6declare <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16>, <8 x i16>)7declare <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16>, <8 x i16>)8declare <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16>, <8 x i16>)9 10define <8 x i16> @haddu_zext(<8 x i8> %a0, <8 x i8> %a1) {11; CHECK-SD-LABEL: haddu_zext:12; CHECK-SD: // %bb.0:13; CHECK-SD-NEXT: uhadd v0.8b, v0.8b, v1.8b14; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #015; CHECK-SD-NEXT: ret16;17; CHECK-GI-LABEL: haddu_zext:18; CHECK-GI: // %bb.0:19; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #020; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #021; CHECK-GI-NEXT: mvni v2.8h, #254, lsl #822; CHECK-GI-NEXT: uhadd v0.8h, v0.8h, v1.8h23; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b24; CHECK-GI-NEXT: ret25 %x0 = zext <8 x i8> %a0 to <8 x i16>26 %x1 = zext <8 x i8> %a1 to <8 x i16>27 %hadd = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)28 %res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511,i16 511, i16 511, i16 511, i16 511>29 ret <8 x i16> %res30}31 32define <8 x i16> @rhaddu_zext(<8 x i8> %a0, <8 x i8> %a1) {33; CHECK-SD-LABEL: rhaddu_zext:34; CHECK-SD: // %bb.0:35; CHECK-SD-NEXT: urhadd v0.8b, v0.8b, v1.8b36; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #037; CHECK-SD-NEXT: ret38;39; CHECK-GI-LABEL: rhaddu_zext:40; CHECK-GI: // %bb.0:41; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #042; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #043; CHECK-GI-NEXT: mvni v2.8h, #254, lsl #844; CHECK-GI-NEXT: urhadd v0.8h, v0.8h, v1.8h45; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b46; CHECK-GI-NEXT: ret47 %x0 = zext <8 x i8> %a0 to <8 x i16>48 %x1 = zext <8 x i8> %a1 to <8 x i16>49 %hadd = call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)50 %res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511>51 ret <8 x i16> %res52}53 54define <8 x i16> @hadds_zext(<8 x i8> %a0, <8 x i8> %a1) {55; CHECK-SD-LABEL: hadds_zext:56; CHECK-SD: // %bb.0:57; CHECK-SD-NEXT: uhadd v0.8b, v0.8b, v1.8b58; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #059; CHECK-SD-NEXT: ret60;61; CHECK-GI-LABEL: hadds_zext:62; CHECK-GI: // %bb.0:63; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #064; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #065; CHECK-GI-NEXT: mvni v2.8h, #254, lsl #866; CHECK-GI-NEXT: shadd v0.8h, v0.8h, v1.8h67; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b68; CHECK-GI-NEXT: ret69 %x0 = zext <8 x i8> %a0 to <8 x i16>70 %x1 = zext <8 x i8> %a1 to <8 x i16>71 %hadd = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)72 %res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511>73 ret <8 x i16> %res74}75 76define <8 x i16> @shaddu_zext(<8 x i8> %a0, <8 x i8> %a1) {77; CHECK-SD-LABEL: shaddu_zext:78; CHECK-SD: // %bb.0:79; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #080; CHECK-SD-NEXT: ushll v1.8h, v1.8b, #081; CHECK-SD-NEXT: srhadd v0.8h, v0.8h, v1.8h82; CHECK-SD-NEXT: ret83;84; CHECK-GI-LABEL: shaddu_zext:85; CHECK-GI: // %bb.0:86; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #087; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #088; CHECK-GI-NEXT: mvni v2.8h, #254, lsl #889; CHECK-GI-NEXT: srhadd v0.8h, v0.8h, v1.8h90; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b91; CHECK-GI-NEXT: ret92 %x0 = zext <8 x i8> %a0 to <8 x i16>93 %x1 = zext <8 x i8> %a1 to <8 x i16>94 %hadd = call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)95 %res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511>96 ret <8 x i16> %res97}98 99; ; negative tests100 101define <8 x i16> @haddu_sext(<8 x i8> %a0, <8 x i8> %a1) {102; CHECK-SD-LABEL: haddu_sext:103; CHECK-SD: // %bb.0:104; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0105; CHECK-SD-NEXT: sshll v1.8h, v1.8b, #0106; CHECK-SD-NEXT: uhadd v0.8h, v0.8h, v1.8h107; CHECK-SD-NEXT: bic v0.8h, #254, lsl #8108; CHECK-SD-NEXT: ret109;110; CHECK-GI-LABEL: haddu_sext:111; CHECK-GI: // %bb.0:112; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0113; CHECK-GI-NEXT: sshll v1.8h, v1.8b, #0114; CHECK-GI-NEXT: mvni v2.8h, #254, lsl #8115; CHECK-GI-NEXT: uhadd v0.8h, v0.8h, v1.8h116; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b117; CHECK-GI-NEXT: ret118 %x0 = sext <8 x i8> %a0 to <8 x i16>119 %x1 = sext <8 x i8> %a1 to <8 x i16>120 %hadd = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)121 %res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511,i16 511, i16 511, i16 511, i16 511>122 ret <8 x i16> %res123}124 125define <8 x i16> @urhadd_sext(<8 x i8> %a0, <8 x i8> %a1) {126; CHECK-SD-LABEL: urhadd_sext:127; CHECK-SD: // %bb.0:128; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0129; CHECK-SD-NEXT: sshll v1.8h, v1.8b, #0130; CHECK-SD-NEXT: urhadd v0.8h, v0.8h, v1.8h131; CHECK-SD-NEXT: bic v0.8h, #254, lsl #8132; CHECK-SD-NEXT: ret133;134; CHECK-GI-LABEL: urhadd_sext:135; CHECK-GI: // %bb.0:136; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0137; CHECK-GI-NEXT: sshll v1.8h, v1.8b, #0138; CHECK-GI-NEXT: mvni v2.8h, #254, lsl #8139; CHECK-GI-NEXT: urhadd v0.8h, v0.8h, v1.8h140; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b141; CHECK-GI-NEXT: ret142 %x0 = sext <8 x i8> %a0 to <8 x i16>143 %x1 = sext <8 x i8> %a1 to <8 x i16>144 %hadd = call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)145 %res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511,i16 511, i16 511, i16 511, i16 511>146 ret <8 x i16> %res147}148 149define <8 x i16> @hadds_sext(<8 x i8> %a0, <8 x i8> %a1) {150; CHECK-SD-LABEL: hadds_sext:151; CHECK-SD: // %bb.0:152; CHECK-SD-NEXT: shadd v0.8b, v0.8b, v1.8b153; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0154; CHECK-SD-NEXT: bic v0.8h, #254, lsl #8155; CHECK-SD-NEXT: ret156;157; CHECK-GI-LABEL: hadds_sext:158; CHECK-GI: // %bb.0:159; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0160; CHECK-GI-NEXT: sshll v1.8h, v1.8b, #0161; CHECK-GI-NEXT: mvni v2.8h, #254, lsl #8162; CHECK-GI-NEXT: shadd v0.8h, v0.8h, v1.8h163; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b164; CHECK-GI-NEXT: ret165 %x0 = sext <8 x i8> %a0 to <8 x i16>166 %x1 = sext <8 x i8> %a1 to <8 x i16>167 %hadd = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)168 %res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511>169 ret <8 x i16> %res170}171 172define <8 x i16> @shaddu_sext(<8 x i8> %a0, <8 x i8> %a1) {173; CHECK-SD-LABEL: shaddu_sext:174; CHECK-SD: // %bb.0:175; CHECK-SD-NEXT: srhadd v0.8b, v0.8b, v1.8b176; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0177; CHECK-SD-NEXT: bic v0.8h, #254, lsl #8178; CHECK-SD-NEXT: ret179;180; CHECK-GI-LABEL: shaddu_sext:181; CHECK-GI: // %bb.0:182; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0183; CHECK-GI-NEXT: sshll v1.8h, v1.8b, #0184; CHECK-GI-NEXT: mvni v2.8h, #254, lsl #8185; CHECK-GI-NEXT: srhadd v0.8h, v0.8h, v1.8h186; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b187; CHECK-GI-NEXT: ret188 %x0 = sext <8 x i8> %a0 to <8 x i16>189 %x1 = sext <8 x i8> %a1 to <8 x i16>190 %hadd = call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)191 %res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511>192 ret <8 x i16> %res193}194;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:195; CHECK: {{.*}}196