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1# RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs -run-pass=aarch64-ldst-opt %s -o - | FileCheck %s2#3# The test below tests that when the AArch64 Load Store Optimization pass tries to4# convert load instructions into a ldp instruction, and when the destination5# registers are sub/super register of each other, then the convertion should not occur.6#7# For example, for the following pattern:8# ldr x10 [x9]9# ldr w10 [x9, 8],10# We cannot convert it to an ldp instruction.11#12# CHECK-NOT: LDP13# CHECK: $x10 = LDRSWui $x9, 014# CHECK: $w10 = LDRWui $x9, 115# CHECK: RET16---17name: test118tracksRegLiveness: true19body: |20 bb.0:21 liveins: $x922 $x10 = LDRSWui $x9, 0 :: (load (s32))23 $w10 = LDRWui $x9, 1 :: (load (s32))24 RET undef $lr, implicit undef $w025...26# CHECK-NOT: LDP27# CHECK: $w10 = LDRWui $x9, 028# CHECK: $x10 = LDRSWui $x9, 129# CHECK: RET30---31name: test232tracksRegLiveness: true33body: |34 bb.0:35 liveins: $x936 $w10 = LDRWui $x9, 0 :: (load (s32))37 $x10 = LDRSWui $x9, 1 :: (load (s32))38 RET undef $lr, implicit undef $w039...40