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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc -mtriple aarch64-none-linux-gnu -mattr=+neon,+i8mm < %s | FileCheck %s3; RUN: llc -mtriple aarch64-none-linux-gnu -mattr=+neon,+i8mm -global-isel < %s | FileCheck %s4 5define <4 x i32> @smmla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) {6; CHECK-LABEL: smmla.v4i32.v16i8:7; CHECK: // %bb.0: // %entry8; CHECK-NEXT: smmla v0.4s, v1.16b, v2.16b9; CHECK-NEXT: ret10entry:11 %vmmla1.i = tail call <4 x i32> @llvm.aarch64.neon.smmla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b)12 ret <4 x i32> %vmmla1.i13}14 15define <4 x i32> @ummla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) {16; CHECK-LABEL: ummla.v4i32.v16i8:17; CHECK: // %bb.0: // %entry18; CHECK-NEXT: ummla v0.4s, v1.16b, v2.16b19; CHECK-NEXT: ret20entry:21 %vmmla1.i = tail call <4 x i32> @llvm.aarch64.neon.ummla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b)22 ret <4 x i32> %vmmla1.i23}24 25define <4 x i32> @usmmla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) {26; CHECK-LABEL: usmmla.v4i32.v16i8:27; CHECK: // %bb.0: // %entry28; CHECK-NEXT: usmmla v0.4s, v1.16b, v2.16b29; CHECK-NEXT: ret30entry:31 %vusmmla1.i = tail call <4 x i32> @llvm.aarch64.neon.usmmla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) #332 ret <4 x i32> %vusmmla1.i33}34 35define <2 x i32> @usdot.v2i32.v8i8(<2 x i32> %r, <8 x i8> %a, <8 x i8> %b) {36; CHECK-LABEL: usdot.v2i32.v8i8:37; CHECK: // %bb.0: // %entry38; CHECK-NEXT: usdot v0.2s, v1.8b, v2.8b39; CHECK-NEXT: ret40entry:41 %vusdot1.i = tail call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %r, <8 x i8> %a, <8 x i8> %b)42 ret <2 x i32> %vusdot1.i43}44 45define <2 x i32> @usdot_lane.v2i32.v8i8(<2 x i32> %r, <8 x i8> %a, <8 x i8> %b) {46; CHECK-LABEL: usdot_lane.v2i32.v8i8:47; CHECK: // %bb.0: // %entry48; CHECK-NEXT: // kill: def $d2 killed $d2 def $q249; CHECK-NEXT: usdot v0.2s, v1.8b, v2.4b[0]50; CHECK-NEXT: ret51entry:52 %0 = bitcast <8 x i8> %b to <2 x i32>53 %shuffle = shufflevector <2 x i32> %0, <2 x i32> undef, <2 x i32> zeroinitializer54 %1 = bitcast <2 x i32> %shuffle to <8 x i8>55 %vusdot1.i = tail call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %r, <8 x i8> %a, <8 x i8> %1)56 ret <2 x i32> %vusdot1.i57}58 59define <2 x i32> @sudot_lane.v2i32.v8i8(<2 x i32> %r, <8 x i8> %a, <8 x i8> %b) {60; CHECK-LABEL: sudot_lane.v2i32.v8i8:61; CHECK: // %bb.0: // %entry62; CHECK-NEXT: // kill: def $d2 killed $d2 def $q263; CHECK-NEXT: sudot v0.2s, v1.8b, v2.4b[0]64; CHECK-NEXT: ret65entry:66 %0 = bitcast <8 x i8> %b to <2 x i32>67 %shuffle = shufflevector <2 x i32> %0, <2 x i32> undef, <2 x i32> zeroinitializer68 %1 = bitcast <2 x i32> %shuffle to <8 x i8>69 %vusdot1.i = tail call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %r, <8 x i8> %1, <8 x i8> %a)70 ret <2 x i32> %vusdot1.i71}72 73define <2 x i32> @usdot_lane.v2i32.v16i8(<2 x i32> %r, <8 x i8> %a, <16 x i8> %b) {74; CHECK-LABEL: usdot_lane.v2i32.v16i8:75; CHECK: // %bb.0: // %entry76; CHECK-NEXT: usdot v0.2s, v1.8b, v2.4b[0]77; CHECK-NEXT: ret78entry:79 %0 = bitcast <16 x i8> %b to <4 x i32>80 %shuffle = shufflevector <4 x i32> %0, <4 x i32> undef, <2 x i32> zeroinitializer81 %1 = bitcast <2 x i32> %shuffle to <8 x i8>82 %vusdot1.i = tail call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %r, <8 x i8> %a, <8 x i8> %1)83 ret <2 x i32> %vusdot1.i84}85 86define <2 x i32> @sudot_lane.v2i32.v16i8(<2 x i32> %r, <8 x i8> %a, <16 x i8> %b) {87; CHECK-LABEL: sudot_lane.v2i32.v16i8:88; CHECK: // %bb.0: // %entry89; CHECK-NEXT: sudot v0.2s, v1.8b, v2.4b[0]90; CHECK-NEXT: ret91entry:92 %0 = bitcast <16 x i8> %b to <4 x i32>93 %shuffle = shufflevector <4 x i32> %0, <4 x i32> undef, <2 x i32> zeroinitializer94 %1 = bitcast <2 x i32> %shuffle to <8 x i8>95 %vusdot1.i = tail call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %r, <8 x i8> %1, <8 x i8> %a) #396 ret <2 x i32> %vusdot1.i97}98 99define <4 x i32> @usdot.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) {100; CHECK-LABEL: usdot.v4i32.v16i8:101; CHECK: // %bb.0: // %entry102; CHECK-NEXT: usdot v0.4s, v1.16b, v2.16b103; CHECK-NEXT: ret104entry:105 %vusdot1.i = tail call <4 x i32> @llvm.aarch64.neon.usdot.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) #3106 ret <4 x i32> %vusdot1.i107}108 109define <4 x i32> @usdot_lane.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <8 x i8> %b) {110; CHECK-LABEL: usdot_lane.v4i32.v16i8:111; CHECK: // %bb.0: // %entry112; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2113; CHECK-NEXT: usdot v0.4s, v1.16b, v2.4b[0]114; CHECK-NEXT: ret115entry:116 %0 = bitcast <8 x i8> %b to <2 x i32>117 %shuffle = shufflevector <2 x i32> %0, <2 x i32> undef, <4 x i32> zeroinitializer118 %1 = bitcast <4 x i32> %shuffle to <16 x i8>119 %vusdot1.i = tail call <4 x i32> @llvm.aarch64.neon.usdot.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %1) #3120 ret <4 x i32> %vusdot1.i121}122 123define <4 x i32> @sudot_lane.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <8 x i8> %b) {124; CHECK-LABEL: sudot_lane.v4i32.v16i8:125; CHECK: // %bb.0: // %entry126; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2127; CHECK-NEXT: sudot v0.4s, v1.16b, v2.4b[0]128; CHECK-NEXT: ret129entry:130 %0 = bitcast <8 x i8> %b to <2 x i32>131 %shuffle = shufflevector <2 x i32> %0, <2 x i32> undef, <4 x i32> zeroinitializer132 %1 = bitcast <4 x i32> %shuffle to <16 x i8>133 %vusdot1.i = tail call <4 x i32> @llvm.aarch64.neon.usdot.v4i32.v16i8(<4 x i32> %r, <16 x i8> %1, <16 x i8> %a) #3134 ret <4 x i32> %vusdot1.i135}136 137define <4 x i32> @usdot_laneq.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) {138; CHECK-LABEL: usdot_laneq.v4i32.v16i8:139; CHECK: // %bb.0: // %entry140; CHECK-NEXT: usdot v0.4s, v1.16b, v2.4b[0]141; CHECK-NEXT: ret142entry:143 %0 = bitcast <16 x i8> %b to <4 x i32>144 %shuffle = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> zeroinitializer145 %1 = bitcast <4 x i32> %shuffle to <16 x i8>146 %vusdot1.i = tail call <4 x i32> @llvm.aarch64.neon.usdot.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %1) #3147 ret <4 x i32> %vusdot1.i148}149 150define <4 x i32> @sudot_laneq.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) {151; CHECK-LABEL: sudot_laneq.v4i32.v16i8:152; CHECK: // %bb.0: // %entry153; CHECK-NEXT: sudot v0.4s, v1.16b, v2.4b[0]154; CHECK-NEXT: ret155entry:156 %0 = bitcast <16 x i8> %b to <4 x i32>157 %shuffle = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> zeroinitializer158 %1 = bitcast <4 x i32> %shuffle to <16 x i8>159 %vusdot1.i = tail call <4 x i32> @llvm.aarch64.neon.usdot.v4i32.v16i8(<4 x i32> %r, <16 x i8> %1, <16 x i8> %a) #3160 ret <4 x i32> %vusdot1.i161}162 163declare <4 x i32> @llvm.aarch64.neon.smmla.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>) #2164declare <4 x i32> @llvm.aarch64.neon.ummla.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>) #2165declare <4 x i32> @llvm.aarch64.neon.usmmla.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>) #2166declare <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32>, <8 x i8>, <8 x i8>) #2167declare <4 x i32> @llvm.aarch64.neon.usdot.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>) #2168