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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"6 7declare i8 @llvm.vector.reduce.smin.v2i8(<2 x i8>)8declare i8 @llvm.vector.reduce.smin.v3i8(<3 x i8>)9declare i8 @llvm.vector.reduce.smin.v4i8(<4 x i8>)10declare i8 @llvm.vector.reduce.smin.v8i8(<8 x i8>)11declare i8 @llvm.vector.reduce.smin.v16i8(<16 x i8>)12declare i8 @llvm.vector.reduce.smin.v32i8(<32 x i8>)13declare i16 @llvm.vector.reduce.smin.v2i16(<2 x i16>)14declare i16 @llvm.vector.reduce.smin.v3i16(<3 x i16>)15declare i16 @llvm.vector.reduce.smin.v4i16(<4 x i16>)16declare i16 @llvm.vector.reduce.smin.v8i16(<8 x i16>)17declare i16 @llvm.vector.reduce.smin.v16i16(<16 x i16>)18declare i32 @llvm.vector.reduce.smin.v2i32(<2 x i32>)19declare i32 @llvm.vector.reduce.smin.v3i32(<3 x i32>)20declare i32 @llvm.vector.reduce.smin.v4i32(<4 x i32>)21declare i32 @llvm.vector.reduce.smin.v8i32(<8 x i32>)22declare i32 @llvm.vector.reduce.smin.v16i32(<16 x i32>)23declare i64 @llvm.vector.reduce.smin.v2i64(<2 x i64>)24declare i64 @llvm.vector.reduce.smin.v3i64(<3 x i64>)25declare i64 @llvm.vector.reduce.smin.v4i64(<4 x i64>)26declare i128 @llvm.vector.reduce.smin.v2i128(<2 x i128>)27declare i8 @llvm.vector.reduce.smax.v2i8(<2 x i8>)28declare i8 @llvm.vector.reduce.smax.v3i8(<3 x i8>)29declare i8 @llvm.vector.reduce.smax.v4i8(<4 x i8>)30declare i8 @llvm.vector.reduce.smax.v8i8(<8 x i8>)31declare i8 @llvm.vector.reduce.smax.v16i8(<16 x i8>)32declare i8 @llvm.vector.reduce.smax.v32i8(<32 x i8>)33declare i16 @llvm.vector.reduce.smax.v2i16(<2 x i16>)34declare i16 @llvm.vector.reduce.smax.v3i16(<3 x i16>)35declare i16 @llvm.vector.reduce.smax.v4i16(<4 x i16>)36declare i16 @llvm.vector.reduce.smax.v8i16(<8 x i16>)37declare i16 @llvm.vector.reduce.smax.v16i16(<16 x i16>)38declare i32 @llvm.vector.reduce.smax.v2i32(<2 x i32>)39declare i32 @llvm.vector.reduce.smax.v3i32(<3 x i32>)40declare i32 @llvm.vector.reduce.smax.v4i32(<4 x i32>)41declare i32 @llvm.vector.reduce.smax.v8i32(<8 x i32>)42declare i32 @llvm.vector.reduce.smax.v16i32(<16 x i32>)43declare i64 @llvm.vector.reduce.smax.v2i64(<2 x i64>)44declare i64 @llvm.vector.reduce.smax.v3i64(<3 x i64>)45declare i64 @llvm.vector.reduce.smax.v4i64(<4 x i64>)46declare i128 @llvm.vector.reduce.smax.v2i128(<2 x i128>)47declare i8 @llvm.vector.reduce.umin.v2i8(<2 x i8>)48declare i8 @llvm.vector.reduce.umin.v3i8(<3 x i8>)49declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)50declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)51declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)52declare i8 @llvm.vector.reduce.umin.v32i8(<32 x i8>)53declare i16 @llvm.vector.reduce.umin.v2i16(<2 x i16>)54declare i16 @llvm.vector.reduce.umin.v3i16(<3 x i16>)55declare i16 @llvm.vector.reduce.umin.v4i16(<4 x i16>)56declare i16 @llvm.vector.reduce.umin.v8i16(<8 x i16>)57declare i16 @llvm.vector.reduce.umin.v16i16(<16 x i16>)58declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>)59declare i32 @llvm.vector.reduce.umin.v3i32(<3 x i32>)60declare i32 @llvm.vector.reduce.umin.v4i32(<4 x i32>)61declare i32 @llvm.vector.reduce.umin.v8i32(<8 x i32>)62declare i32 @llvm.vector.reduce.umin.v16i32(<16 x i32>)63declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)64declare i64 @llvm.vector.reduce.umin.v3i64(<3 x i64>)65declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>)66declare i128 @llvm.vector.reduce.umin.v2i128(<2 x i128>)67declare i8 @llvm.vector.reduce.umax.v2i8(<2 x i8>)68declare i8 @llvm.vector.reduce.umax.v3i8(<3 x i8>)69declare i8 @llvm.vector.reduce.umax.v4i8(<4 x i8>)70declare i8 @llvm.vector.reduce.umax.v8i8(<8 x i8>)71declare i8 @llvm.vector.reduce.umax.v16i8(<16 x i8>)72declare i8 @llvm.vector.reduce.umax.v32i8(<32 x i8>)73declare i16 @llvm.vector.reduce.umax.v2i16(<2 x i16>)74declare i16 @llvm.vector.reduce.umax.v3i16(<3 x i16>)75declare i16 @llvm.vector.reduce.umax.v4i16(<4 x i16>)76declare i16 @llvm.vector.reduce.umax.v8i16(<8 x i16>)77declare i16 @llvm.vector.reduce.umax.v16i16(<16 x i16>)78declare i32 @llvm.vector.reduce.umax.v2i32(<2 x i32>)79declare i32 @llvm.vector.reduce.umax.v3i32(<3 x i32>)80declare i32 @llvm.vector.reduce.umax.v4i32(<4 x i32>)81declare i32 @llvm.vector.reduce.umax.v8i32(<8 x i32>)82declare i32 @llvm.vector.reduce.umax.v16i32(<16 x i32>)83declare i64 @llvm.vector.reduce.umax.v2i64(<2 x i64>)84declare i64 @llvm.vector.reduce.umax.v3i64(<3 x i64>)85declare i64 @llvm.vector.reduce.umax.v4i64(<4 x i64>)86declare i128 @llvm.vector.reduce.umax.v2i128(<2 x i128>)87 88declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>)89declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)90 91define i8 @smax_B(ptr nocapture readonly %arr) {92; CHECK-LABEL: smax_B:93; CHECK: // %bb.0:94; CHECK-NEXT: ldr q0, [x0]95; CHECK-NEXT: smaxv b0, v0.16b96; CHECK-NEXT: fmov w0, s097; CHECK-NEXT: ret98 %arr.load = load <16 x i8>, ptr %arr99 %r = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %arr.load)100 ret i8 %r101}102 103define i16 @smax_H(ptr nocapture readonly %arr) {104; CHECK-LABEL: smax_H:105; CHECK: // %bb.0:106; CHECK-NEXT: ldr q0, [x0]107; CHECK-NEXT: smaxv h0, v0.8h108; CHECK-NEXT: fmov w0, s0109; CHECK-NEXT: ret110 %arr.load = load <8 x i16>, ptr %arr111 %r = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %arr.load)112 ret i16 %r113}114 115define i32 @smax_S(ptr nocapture readonly %arr) {116; CHECK-LABEL: smax_S:117; CHECK: // %bb.0:118; CHECK-NEXT: ldr q0, [x0]119; CHECK-NEXT: smaxv s0, v0.4s120; CHECK-NEXT: fmov w0, s0121; CHECK-NEXT: ret122 %arr.load = load <4 x i32>, ptr %arr123 %r = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %arr.load)124 ret i32 %r125}126 127define i8 @umax_B(ptr nocapture readonly %arr) {128; CHECK-LABEL: umax_B:129; CHECK: // %bb.0:130; CHECK-NEXT: ldr q0, [x0]131; CHECK-NEXT: umaxv b0, v0.16b132; CHECK-NEXT: fmov w0, s0133; CHECK-NEXT: ret134 %arr.load = load <16 x i8>, ptr %arr135 %r = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %arr.load)136 ret i8 %r137}138 139define i16 @umax_H(ptr nocapture readonly %arr) {140; CHECK-LABEL: umax_H:141; CHECK: // %bb.0:142; CHECK-NEXT: ldr q0, [x0]143; CHECK-NEXT: umaxv h0, v0.8h144; CHECK-NEXT: fmov w0, s0145; CHECK-NEXT: ret146 %arr.load = load <8 x i16>, ptr %arr147 %r = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> %arr.load)148 ret i16 %r149}150 151define i32 @umax_S(ptr nocapture readonly %arr) {152; CHECK-LABEL: umax_S:153; CHECK: // %bb.0:154; CHECK-NEXT: ldr q0, [x0]155; CHECK-NEXT: umaxv s0, v0.4s156; CHECK-NEXT: fmov w0, s0157; CHECK-NEXT: ret158 %arr.load = load <4 x i32>, ptr %arr159 %r = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %arr.load)160 ret i32 %r161}162 163define i8 @smin_B(ptr nocapture readonly %arr) {164; CHECK-LABEL: smin_B:165; CHECK: // %bb.0:166; CHECK-NEXT: ldr q0, [x0]167; CHECK-NEXT: sminv b0, v0.16b168; CHECK-NEXT: fmov w0, s0169; CHECK-NEXT: ret170 %arr.load = load <16 x i8>, ptr %arr171 %r = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> %arr.load)172 ret i8 %r173}174 175define i16 @smin_H(ptr nocapture readonly %arr) {176; CHECK-LABEL: smin_H:177; CHECK: // %bb.0:178; CHECK-NEXT: ldr q0, [x0]179; CHECK-NEXT: sminv h0, v0.8h180; CHECK-NEXT: fmov w0, s0181; CHECK-NEXT: ret182 %arr.load = load <8 x i16>, ptr %arr183 %r = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %arr.load)184 ret i16 %r185}186 187define i32 @smin_S(ptr nocapture readonly %arr) {188; CHECK-LABEL: smin_S:189; CHECK: // %bb.0:190; CHECK-NEXT: ldr q0, [x0]191; CHECK-NEXT: sminv s0, v0.4s192; CHECK-NEXT: fmov w0, s0193; CHECK-NEXT: ret194 %arr.load = load <4 x i32>, ptr %arr195 %r = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %arr.load)196 ret i32 %r197}198 199define i8 @umin_B(ptr nocapture readonly %arr) {200; CHECK-LABEL: umin_B:201; CHECK: // %bb.0:202; CHECK-NEXT: ldr q0, [x0]203; CHECK-NEXT: uminv b0, v0.16b204; CHECK-NEXT: fmov w0, s0205; CHECK-NEXT: ret206 %arr.load = load <16 x i8>, ptr %arr207 %r = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %arr.load)208 ret i8 %r209}210 211define i16 @umin_H(ptr nocapture readonly %arr) {212; CHECK-LABEL: umin_H:213; CHECK: // %bb.0:214; CHECK-NEXT: ldr q0, [x0]215; CHECK-NEXT: uminv h0, v0.8h216; CHECK-NEXT: fmov w0, s0217; CHECK-NEXT: ret218 %arr.load = load <8 x i16>, ptr %arr219 %r = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> %arr.load)220 ret i16 %r221}222 223define i32 @umin_S(ptr nocapture readonly %arr) {224; CHECK-LABEL: umin_S:225; CHECK: // %bb.0:226; CHECK-NEXT: ldr q0, [x0]227; CHECK-NEXT: uminv s0, v0.4s228; CHECK-NEXT: fmov w0, s0229; CHECK-NEXT: ret230 %arr.load = load <4 x i32>, ptr %arr231 %r = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %arr.load)232 ret i32 %r233}234 235define float @fmaxnm_S(ptr nocapture readonly %arr) {236; CHECK-LABEL: fmaxnm_S:237; CHECK: // %bb.0:238; CHECK-NEXT: ldr q0, [x0]239; CHECK-NEXT: fmaxnmv s0, v0.4s240; CHECK-NEXT: ret241 %arr.load = load <4 x float>, ptr %arr242 %r = call nnan float @llvm.vector.reduce.fmax.v4f32(<4 x float> %arr.load)243 ret float %r244}245 246define float @fminnm_S(ptr nocapture readonly %arr) {247; CHECK-LABEL: fminnm_S:248; CHECK: // %bb.0:249; CHECK-NEXT: ldr q0, [x0]250; CHECK-NEXT: fminnmv s0, v0.4s251; CHECK-NEXT: ret252 %arr.load = load <4 x float>, ptr %arr253 %r = call nnan float @llvm.vector.reduce.fmin.v4f32(<4 x float> %arr.load)254 ret float %r255}256 257define i16 @oversized_umax_256(ptr nocapture readonly %arr) {258; CHECK-SD-LABEL: oversized_umax_256:259; CHECK-SD: // %bb.0:260; CHECK-SD-NEXT: ldp q1, q0, [x0]261; CHECK-SD-NEXT: umax v0.8h, v1.8h, v0.8h262; CHECK-SD-NEXT: umaxv h0, v0.8h263; CHECK-SD-NEXT: fmov w0, s0264; CHECK-SD-NEXT: ret265;266; CHECK-GI-LABEL: oversized_umax_256:267; CHECK-GI: // %bb.0:268; CHECK-GI-NEXT: ldp q0, q1, [x0]269; CHECK-GI-NEXT: umax v0.8h, v0.8h, v1.8h270; CHECK-GI-NEXT: umaxv h0, v0.8h271; CHECK-GI-NEXT: fmov w0, s0272; CHECK-GI-NEXT: ret273 %arr.load = load <16 x i16>, ptr %arr274 %r = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> %arr.load)275 ret i16 %r276}277 278define i32 @oversized_umax_512(ptr nocapture readonly %arr) {279; CHECK-SD-LABEL: oversized_umax_512:280; CHECK-SD: // %bb.0:281; CHECK-SD-NEXT: ldp q0, q1, [x0, #32]282; CHECK-SD-NEXT: ldp q2, q3, [x0]283; CHECK-SD-NEXT: umax v1.4s, v3.4s, v1.4s284; CHECK-SD-NEXT: umax v0.4s, v2.4s, v0.4s285; CHECK-SD-NEXT: umax v0.4s, v0.4s, v1.4s286; CHECK-SD-NEXT: umaxv s0, v0.4s287; CHECK-SD-NEXT: fmov w0, s0288; CHECK-SD-NEXT: ret289;290; CHECK-GI-LABEL: oversized_umax_512:291; CHECK-GI: // %bb.0:292; CHECK-GI-NEXT: ldp q0, q1, [x0]293; CHECK-GI-NEXT: ldp q2, q3, [x0, #32]294; CHECK-GI-NEXT: umax v0.4s, v0.4s, v1.4s295; CHECK-GI-NEXT: umax v1.4s, v2.4s, v3.4s296; CHECK-GI-NEXT: umax v0.4s, v0.4s, v1.4s297; CHECK-GI-NEXT: umaxv s0, v0.4s298; CHECK-GI-NEXT: fmov w0, s0299; CHECK-GI-NEXT: ret300 %arr.load = load <16 x i32>, ptr %arr301 %r = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> %arr.load)302 ret i32 %r303}304 305define i16 @oversized_umin_256(ptr nocapture readonly %arr) {306; CHECK-SD-LABEL: oversized_umin_256:307; CHECK-SD: // %bb.0:308; CHECK-SD-NEXT: ldp q1, q0, [x0]309; CHECK-SD-NEXT: umin v0.8h, v1.8h, v0.8h310; CHECK-SD-NEXT: uminv h0, v0.8h311; CHECK-SD-NEXT: fmov w0, s0312; CHECK-SD-NEXT: ret313;314; CHECK-GI-LABEL: oversized_umin_256:315; CHECK-GI: // %bb.0:316; CHECK-GI-NEXT: ldp q0, q1, [x0]317; CHECK-GI-NEXT: umin v0.8h, v0.8h, v1.8h318; CHECK-GI-NEXT: uminv h0, v0.8h319; CHECK-GI-NEXT: fmov w0, s0320; CHECK-GI-NEXT: ret321 %arr.load = load <16 x i16>, ptr %arr322 %r = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> %arr.load)323 ret i16 %r324}325 326define i32 @oversized_umin_512(ptr nocapture readonly %arr) {327; CHECK-SD-LABEL: oversized_umin_512:328; CHECK-SD: // %bb.0:329; CHECK-SD-NEXT: ldp q0, q1, [x0, #32]330; CHECK-SD-NEXT: ldp q2, q3, [x0]331; CHECK-SD-NEXT: umin v1.4s, v3.4s, v1.4s332; CHECK-SD-NEXT: umin v0.4s, v2.4s, v0.4s333; CHECK-SD-NEXT: umin v0.4s, v0.4s, v1.4s334; CHECK-SD-NEXT: uminv s0, v0.4s335; CHECK-SD-NEXT: fmov w0, s0336; CHECK-SD-NEXT: ret337;338; CHECK-GI-LABEL: oversized_umin_512:339; CHECK-GI: // %bb.0:340; CHECK-GI-NEXT: ldp q0, q1, [x0]341; CHECK-GI-NEXT: ldp q2, q3, [x0, #32]342; CHECK-GI-NEXT: umin v0.4s, v0.4s, v1.4s343; CHECK-GI-NEXT: umin v1.4s, v2.4s, v3.4s344; CHECK-GI-NEXT: umin v0.4s, v0.4s, v1.4s345; CHECK-GI-NEXT: uminv s0, v0.4s346; CHECK-GI-NEXT: fmov w0, s0347; CHECK-GI-NEXT: ret348 %arr.load = load <16 x i32>, ptr %arr349 %r = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> %arr.load)350 ret i32 %r351}352 353define i16 @oversized_smax_256(ptr nocapture readonly %arr) {354; CHECK-SD-LABEL: oversized_smax_256:355; CHECK-SD: // %bb.0:356; CHECK-SD-NEXT: ldp q1, q0, [x0]357; CHECK-SD-NEXT: smax v0.8h, v1.8h, v0.8h358; CHECK-SD-NEXT: smaxv h0, v0.8h359; CHECK-SD-NEXT: fmov w0, s0360; CHECK-SD-NEXT: ret361;362; CHECK-GI-LABEL: oversized_smax_256:363; CHECK-GI: // %bb.0:364; CHECK-GI-NEXT: ldp q0, q1, [x0]365; CHECK-GI-NEXT: smax v0.8h, v0.8h, v1.8h366; CHECK-GI-NEXT: smaxv h0, v0.8h367; CHECK-GI-NEXT: fmov w0, s0368; CHECK-GI-NEXT: ret369 %arr.load = load <16 x i16>, ptr %arr370 %r = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> %arr.load)371 ret i16 %r372}373 374define i32 @oversized_smax_512(ptr nocapture readonly %arr) {375; CHECK-SD-LABEL: oversized_smax_512:376; CHECK-SD: // %bb.0:377; CHECK-SD-NEXT: ldp q0, q1, [x0, #32]378; CHECK-SD-NEXT: ldp q2, q3, [x0]379; CHECK-SD-NEXT: smax v1.4s, v3.4s, v1.4s380; CHECK-SD-NEXT: smax v0.4s, v2.4s, v0.4s381; CHECK-SD-NEXT: smax v0.4s, v0.4s, v1.4s382; CHECK-SD-NEXT: smaxv s0, v0.4s383; CHECK-SD-NEXT: fmov w0, s0384; CHECK-SD-NEXT: ret385;386; CHECK-GI-LABEL: oversized_smax_512:387; CHECK-GI: // %bb.0:388; CHECK-GI-NEXT: ldp q0, q1, [x0]389; CHECK-GI-NEXT: ldp q2, q3, [x0, #32]390; CHECK-GI-NEXT: smax v0.4s, v0.4s, v1.4s391; CHECK-GI-NEXT: smax v1.4s, v2.4s, v3.4s392; CHECK-GI-NEXT: smax v0.4s, v0.4s, v1.4s393; CHECK-GI-NEXT: smaxv s0, v0.4s394; CHECK-GI-NEXT: fmov w0, s0395; CHECK-GI-NEXT: ret396 %arr.load = load <16 x i32>, ptr %arr397 %r = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> %arr.load)398 ret i32 %r399}400 401define i16 @oversized_smin_256(ptr nocapture readonly %arr) {402; CHECK-SD-LABEL: oversized_smin_256:403; CHECK-SD: // %bb.0:404; CHECK-SD-NEXT: ldp q1, q0, [x0]405; CHECK-SD-NEXT: smin v0.8h, v1.8h, v0.8h406; CHECK-SD-NEXT: sminv h0, v0.8h407; CHECK-SD-NEXT: fmov w0, s0408; CHECK-SD-NEXT: ret409;410; CHECK-GI-LABEL: oversized_smin_256:411; CHECK-GI: // %bb.0:412; CHECK-GI-NEXT: ldp q0, q1, [x0]413; CHECK-GI-NEXT: smin v0.8h, v0.8h, v1.8h414; CHECK-GI-NEXT: sminv h0, v0.8h415; CHECK-GI-NEXT: fmov w0, s0416; CHECK-GI-NEXT: ret417 %arr.load = load <16 x i16>, ptr %arr418 %r = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> %arr.load)419 ret i16 %r420}421 422 423define i32 @oversized_smin_512(ptr nocapture readonly %arr) {424; CHECK-SD-LABEL: oversized_smin_512:425; CHECK-SD: // %bb.0:426; CHECK-SD-NEXT: ldp q0, q1, [x0, #32]427; CHECK-SD-NEXT: ldp q2, q3, [x0]428; CHECK-SD-NEXT: smin v1.4s, v3.4s, v1.4s429; CHECK-SD-NEXT: smin v0.4s, v2.4s, v0.4s430; CHECK-SD-NEXT: smin v0.4s, v0.4s, v1.4s431; CHECK-SD-NEXT: sminv s0, v0.4s432; CHECK-SD-NEXT: fmov w0, s0433; CHECK-SD-NEXT: ret434;435; CHECK-GI-LABEL: oversized_smin_512:436; CHECK-GI: // %bb.0:437; CHECK-GI-NEXT: ldp q0, q1, [x0]438; CHECK-GI-NEXT: ldp q2, q3, [x0, #32]439; CHECK-GI-NEXT: smin v0.4s, v0.4s, v1.4s440; CHECK-GI-NEXT: smin v1.4s, v2.4s, v3.4s441; CHECK-GI-NEXT: smin v0.4s, v0.4s, v1.4s442; CHECK-GI-NEXT: sminv s0, v0.4s443; CHECK-GI-NEXT: fmov w0, s0444; CHECK-GI-NEXT: ret445 %arr.load = load <16 x i32>, ptr %arr446 %r = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> %arr.load)447 ret i32 %r448}449 450define i8 @sminv_v2i8(<2 x i8> %a) {451; CHECK-SD-LABEL: sminv_v2i8:452; CHECK-SD: // %bb.0: // %entry453; CHECK-SD-NEXT: shl v0.2s, v0.2s, #24454; CHECK-SD-NEXT: sshr v0.2s, v0.2s, #24455; CHECK-SD-NEXT: sminp v0.2s, v0.2s, v0.2s456; CHECK-SD-NEXT: fmov w0, s0457; CHECK-SD-NEXT: ret458;459; CHECK-GI-LABEL: sminv_v2i8:460; CHECK-GI: // %bb.0: // %entry461; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0462; CHECK-GI-NEXT: mov s1, v0.s[1]463; CHECK-GI-NEXT: fmov w8, s0464; CHECK-GI-NEXT: sxtb w8, w8465; CHECK-GI-NEXT: fmov w9, s1466; CHECK-GI-NEXT: cmp w8, w9, sxtb467; CHECK-GI-NEXT: fcsel s0, s0, s1, lt468; CHECK-GI-NEXT: fmov w0, s0469; CHECK-GI-NEXT: ret470entry:471 %arg1 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> %a)472 ret i8 %arg1473}474 475define i8 @sminv_v3i8(<3 x i8> %a) {476; CHECK-SD-LABEL: sminv_v3i8:477; CHECK-SD: // %bb.0: // %entry478; CHECK-SD-NEXT: movi v0.4h, #127479; CHECK-SD-NEXT: mov v0.h[0], w0480; CHECK-SD-NEXT: mov v0.h[1], w1481; CHECK-SD-NEXT: mov v0.h[2], w2482; CHECK-SD-NEXT: shl v0.4h, v0.4h, #8483; CHECK-SD-NEXT: sshr v0.4h, v0.4h, #8484; CHECK-SD-NEXT: sminv h0, v0.4h485; CHECK-SD-NEXT: fmov w0, s0486; CHECK-SD-NEXT: ret487;488; CHECK-GI-LABEL: sminv_v3i8:489; CHECK-GI: // %bb.0: // %entry490; CHECK-GI-NEXT: sxtb w8, w0491; CHECK-GI-NEXT: cmp w8, w1, sxtb492; CHECK-GI-NEXT: csel w8, w0, w1, lt493; CHECK-GI-NEXT: sxtb w9, w8494; CHECK-GI-NEXT: cmp w9, w2, sxtb495; CHECK-GI-NEXT: csel w0, w8, w2, lt496; CHECK-GI-NEXT: ret497entry:498 %arg1 = call i8 @llvm.vector.reduce.smin.v3i8(<3 x i8> %a)499 ret i8 %arg1500}501 502define i8 @sminv_v4i8(<4 x i8> %a) {503; CHECK-SD-LABEL: sminv_v4i8:504; CHECK-SD: // %bb.0: // %entry505; CHECK-SD-NEXT: shl v0.4h, v0.4h, #8506; CHECK-SD-NEXT: sshr v0.4h, v0.4h, #8507; CHECK-SD-NEXT: sminv h0, v0.4h508; CHECK-SD-NEXT: fmov w0, s0509; CHECK-SD-NEXT: ret510;511; CHECK-GI-LABEL: sminv_v4i8:512; CHECK-GI: // %bb.0: // %entry513; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0514; CHECK-GI-NEXT: umov w8, v0.h[0]515; CHECK-GI-NEXT: umov w9, v0.h[1]516; CHECK-GI-NEXT: umov w10, v0.h[2]517; CHECK-GI-NEXT: umov w12, v0.h[3]518; CHECK-GI-NEXT: sxtb w11, w8519; CHECK-GI-NEXT: cmp w11, w9, sxtb520; CHECK-GI-NEXT: sxtb w11, w10521; CHECK-GI-NEXT: csel w8, w8, w9, lt522; CHECK-GI-NEXT: cmp w11, w12, sxtb523; CHECK-GI-NEXT: sxtb w9, w8524; CHECK-GI-NEXT: csel w10, w10, w12, lt525; CHECK-GI-NEXT: cmp w9, w10, sxtb526; CHECK-GI-NEXT: csel w0, w8, w10, lt527; CHECK-GI-NEXT: ret528entry:529 %arg1 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> %a)530 ret i8 %arg1531}532 533define i8 @sminv_v8i8(<8 x i8> %a) {534; CHECK-LABEL: sminv_v8i8:535; CHECK: // %bb.0: // %entry536; CHECK-NEXT: sminv b0, v0.8b537; CHECK-NEXT: fmov w0, s0538; CHECK-NEXT: ret539entry:540 %arg1 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> %a)541 ret i8 %arg1542}543 544define i8 @sminv_v16i8(<16 x i8> %a) {545; CHECK-LABEL: sminv_v16i8:546; CHECK: // %bb.0: // %entry547; CHECK-NEXT: sminv b0, v0.16b548; CHECK-NEXT: fmov w0, s0549; CHECK-NEXT: ret550entry:551 %arg1 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> %a)552 ret i8 %arg1553}554 555define i8 @sminv_v32i8(<32 x i8> %a) {556; CHECK-LABEL: sminv_v32i8:557; CHECK: // %bb.0: // %entry558; CHECK-NEXT: smin v0.16b, v0.16b, v1.16b559; CHECK-NEXT: sminv b0, v0.16b560; CHECK-NEXT: fmov w0, s0561; CHECK-NEXT: ret562entry:563 %arg1 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> %a)564 ret i8 %arg1565}566 567define i16 @sminv_v2i16(<2 x i16> %a) {568; CHECK-SD-LABEL: sminv_v2i16:569; CHECK-SD: // %bb.0: // %entry570; CHECK-SD-NEXT: shl v0.2s, v0.2s, #16571; CHECK-SD-NEXT: sshr v0.2s, v0.2s, #16572; CHECK-SD-NEXT: sminp v0.2s, v0.2s, v0.2s573; CHECK-SD-NEXT: fmov w0, s0574; CHECK-SD-NEXT: ret575;576; CHECK-GI-LABEL: sminv_v2i16:577; CHECK-GI: // %bb.0: // %entry578; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0579; CHECK-GI-NEXT: mov s1, v0.s[1]580; CHECK-GI-NEXT: fmov w8, s0581; CHECK-GI-NEXT: sxth w8, w8582; CHECK-GI-NEXT: fmov w9, s1583; CHECK-GI-NEXT: cmp w8, w9, sxth584; CHECK-GI-NEXT: fcsel s0, s0, s1, lt585; CHECK-GI-NEXT: fmov w0, s0586; CHECK-GI-NEXT: ret587entry:588 %arg1 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> %a)589 ret i16 %arg1590}591 592define i16 @sminv_v3i16(<3 x i16> %a) {593; CHECK-LABEL: sminv_v3i16:594; CHECK: // %bb.0: // %entry595; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0596; CHECK-NEXT: mov w8, #32767 // =0x7fff597; CHECK-NEXT: mov v0.h[3], w8598; CHECK-NEXT: sminv h0, v0.4h599; CHECK-NEXT: fmov w0, s0600; CHECK-NEXT: ret601entry:602 %arg1 = call i16 @llvm.vector.reduce.smin.v3i16(<3 x i16> %a)603 ret i16 %arg1604}605 606define i16 @sminv_v4i16(<4 x i16> %a) {607; CHECK-LABEL: sminv_v4i16:608; CHECK: // %bb.0: // %entry609; CHECK-NEXT: sminv h0, v0.4h610; CHECK-NEXT: fmov w0, s0611; CHECK-NEXT: ret612entry:613 %arg1 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> %a)614 ret i16 %arg1615}616 617define i16 @sminv_v8i16(<8 x i16> %a) {618; CHECK-LABEL: sminv_v8i16:619; CHECK: // %bb.0: // %entry620; CHECK-NEXT: sminv h0, v0.8h621; CHECK-NEXT: fmov w0, s0622; CHECK-NEXT: ret623entry:624 %arg1 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %a)625 ret i16 %arg1626}627 628define i16 @sminv_v16i16(<16 x i16> %a) {629; CHECK-LABEL: sminv_v16i16:630; CHECK: // %bb.0: // %entry631; CHECK-NEXT: smin v0.8h, v0.8h, v1.8h632; CHECK-NEXT: sminv h0, v0.8h633; CHECK-NEXT: fmov w0, s0634; CHECK-NEXT: ret635entry:636 %arg1 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> %a)637 ret i16 %arg1638}639 640define i32 @sminv_v2i32(<2 x i32> %a) {641; CHECK-LABEL: sminv_v2i32:642; CHECK: // %bb.0: // %entry643; CHECK-NEXT: sminp v0.2s, v0.2s, v0.2s644; CHECK-NEXT: fmov w0, s0645; CHECK-NEXT: ret646entry:647 %arg1 = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> %a)648 ret i32 %arg1649}650 651define i32 @sminv_v3i32(<3 x i32> %a) {652; CHECK-LABEL: sminv_v3i32:653; CHECK: // %bb.0: // %entry654; CHECK-NEXT: mov w8, #2147483647 // =0x7fffffff655; CHECK-NEXT: mov v0.s[3], w8656; CHECK-NEXT: sminv s0, v0.4s657; CHECK-NEXT: fmov w0, s0658; CHECK-NEXT: ret659entry:660 %arg1 = call i32 @llvm.vector.reduce.smin.v3i32(<3 x i32> %a)661 ret i32 %arg1662}663 664define i32 @sminv_v4i32(<4 x i32> %a) {665; CHECK-LABEL: sminv_v4i32:666; CHECK: // %bb.0: // %entry667; CHECK-NEXT: sminv s0, v0.4s668; CHECK-NEXT: fmov w0, s0669; CHECK-NEXT: ret670entry:671 %arg1 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %a)672 ret i32 %arg1673}674 675define i32 @sminv_v8i32(<8 x i32> %a) {676; CHECK-LABEL: sminv_v8i32:677; CHECK: // %bb.0: // %entry678; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s679; CHECK-NEXT: sminv s0, v0.4s680; CHECK-NEXT: fmov w0, s0681; CHECK-NEXT: ret682entry:683 %arg1 = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> %a)684 ret i32 %arg1685}686 687define i64 @sminv_v2i64(<2 x i64> %a) {688; CHECK-SD-LABEL: sminv_v2i64:689; CHECK-SD: // %bb.0: // %entry690; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8691; CHECK-SD-NEXT: cmgt d2, d1, d0692; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b693; CHECK-SD-NEXT: fmov x0, d0694; CHECK-SD-NEXT: ret695;696; CHECK-GI-LABEL: sminv_v2i64:697; CHECK-GI: // %bb.0: // %entry698; CHECK-GI-NEXT: mov d1, v0.d[1]699; CHECK-GI-NEXT: fmov x8, d0700; CHECK-GI-NEXT: fmov x9, d1701; CHECK-GI-NEXT: cmp x8, x9702; CHECK-GI-NEXT: fcsel d0, d0, d1, lt703; CHECK-GI-NEXT: fmov x0, d0704; CHECK-GI-NEXT: ret705entry:706 %arg1 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> %a)707 ret i64 %arg1708}709 710define i64 @sminv_v3i64(<3 x i64> %a) {711; CHECK-SD-LABEL: sminv_v3i64:712; CHECK-SD: // %bb.0: // %entry713; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2714; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0715; CHECK-SD-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff716; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1717; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]718; CHECK-SD-NEXT: mov v2.d[1], x8719; CHECK-SD-NEXT: cmgt v1.2d, v2.2d, v0.2d720; CHECK-SD-NEXT: bif v0.16b, v2.16b, v1.16b721; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8722; CHECK-SD-NEXT: cmgt d2, d1, d0723; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b724; CHECK-SD-NEXT: fmov x0, d0725; CHECK-SD-NEXT: ret726;727; CHECK-GI-LABEL: sminv_v3i64:728; CHECK-GI: // %bb.0: // %entry729; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0730; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2731; CHECK-GI-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff732; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1733; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]734; CHECK-GI-NEXT: mov v2.d[1], x8735; CHECK-GI-NEXT: cmgt v1.2d, v2.2d, v0.2d736; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b737; CHECK-GI-NEXT: mov d1, v0.d[1]738; CHECK-GI-NEXT: fmov x8, d0739; CHECK-GI-NEXT: fmov x9, d1740; CHECK-GI-NEXT: cmp x8, x9741; CHECK-GI-NEXT: fcsel d0, d0, d1, lt742; CHECK-GI-NEXT: fmov x0, d0743; CHECK-GI-NEXT: ret744entry:745 %arg1 = call i64 @llvm.vector.reduce.smin.v3i64(<3 x i64> %a)746 ret i64 %arg1747}748 749define i64 @sminv_v4i64(<4 x i64> %a) {750; CHECK-SD-LABEL: sminv_v4i64:751; CHECK-SD: // %bb.0: // %entry752; CHECK-SD-NEXT: cmgt v2.2d, v1.2d, v0.2d753; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b754; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8755; CHECK-SD-NEXT: cmgt d2, d1, d0756; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b757; CHECK-SD-NEXT: fmov x0, d0758; CHECK-SD-NEXT: ret759;760; CHECK-GI-LABEL: sminv_v4i64:761; CHECK-GI: // %bb.0: // %entry762; CHECK-GI-NEXT: cmgt v2.2d, v1.2d, v0.2d763; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b764; CHECK-GI-NEXT: mov d1, v0.d[1]765; CHECK-GI-NEXT: fmov x8, d0766; CHECK-GI-NEXT: fmov x9, d1767; CHECK-GI-NEXT: cmp x8, x9768; CHECK-GI-NEXT: fcsel d0, d0, d1, lt769; CHECK-GI-NEXT: fmov x0, d0770; CHECK-GI-NEXT: ret771entry:772 %arg1 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> %a)773 ret i64 %arg1774}775 776define i128 @sminv_v2i128(<2 x i128> %a) {777; CHECK-SD-LABEL: sminv_v2i128:778; CHECK-SD: // %bb.0: // %entry779; CHECK-SD-NEXT: cmp x0, x2780; CHECK-SD-NEXT: sbcs xzr, x1, x3781; CHECK-SD-NEXT: csel x0, x0, x2, lt782; CHECK-SD-NEXT: csel x1, x1, x3, lt783; CHECK-SD-NEXT: ret784;785; CHECK-GI-LABEL: sminv_v2i128:786; CHECK-GI: // %bb.0: // %entry787; CHECK-GI-NEXT: cmp x0, x2788; CHECK-GI-NEXT: cset w8, lo789; CHECK-GI-NEXT: cmp x1, x3790; CHECK-GI-NEXT: cset w9, lt791; CHECK-GI-NEXT: csel w8, w8, w9, eq792; CHECK-GI-NEXT: tst w8, #0x1793; CHECK-GI-NEXT: csel x0, x0, x2, ne794; CHECK-GI-NEXT: csel x1, x1, x3, ne795; CHECK-GI-NEXT: ret796entry:797 %arg1 = call i128 @llvm.vector.reduce.smin.v2i128(<2 x i128> %a)798 ret i128 %arg1799}800 801define i8 @smaxv_v2i8(<2 x i8> %a) {802; CHECK-SD-LABEL: smaxv_v2i8:803; CHECK-SD: // %bb.0: // %entry804; CHECK-SD-NEXT: shl v0.2s, v0.2s, #24805; CHECK-SD-NEXT: sshr v0.2s, v0.2s, #24806; CHECK-SD-NEXT: smaxp v0.2s, v0.2s, v0.2s807; CHECK-SD-NEXT: fmov w0, s0808; CHECK-SD-NEXT: ret809;810; CHECK-GI-LABEL: smaxv_v2i8:811; CHECK-GI: // %bb.0: // %entry812; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0813; CHECK-GI-NEXT: mov s1, v0.s[1]814; CHECK-GI-NEXT: fmov w8, s0815; CHECK-GI-NEXT: sxtb w8, w8816; CHECK-GI-NEXT: fmov w9, s1817; CHECK-GI-NEXT: cmp w8, w9, sxtb818; CHECK-GI-NEXT: fcsel s0, s0, s1, gt819; CHECK-GI-NEXT: fmov w0, s0820; CHECK-GI-NEXT: ret821entry:822 %arg1 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> %a)823 ret i8 %arg1824}825 826define i8 @smaxv_v3i8(<3 x i8> %a) {827; CHECK-SD-LABEL: smaxv_v3i8:828; CHECK-SD: // %bb.0: // %entry829; CHECK-SD-NEXT: movi v0.4h, #128830; CHECK-SD-NEXT: mov v0.h[0], w0831; CHECK-SD-NEXT: mov v0.h[1], w1832; CHECK-SD-NEXT: mov v0.h[2], w2833; CHECK-SD-NEXT: shl v0.4h, v0.4h, #8834; CHECK-SD-NEXT: sshr v0.4h, v0.4h, #8835; CHECK-SD-NEXT: smaxv h0, v0.4h836; CHECK-SD-NEXT: fmov w0, s0837; CHECK-SD-NEXT: ret838;839; CHECK-GI-LABEL: smaxv_v3i8:840; CHECK-GI: // %bb.0: // %entry841; CHECK-GI-NEXT: sxtb w8, w0842; CHECK-GI-NEXT: cmp w8, w1, sxtb843; CHECK-GI-NEXT: csel w8, w0, w1, gt844; CHECK-GI-NEXT: sxtb w9, w8845; CHECK-GI-NEXT: cmp w9, w2, sxtb846; CHECK-GI-NEXT: csel w0, w8, w2, gt847; CHECK-GI-NEXT: ret848entry:849 %arg1 = call i8 @llvm.vector.reduce.smax.v3i8(<3 x i8> %a)850 ret i8 %arg1851}852 853define i8 @smaxv_v4i8(<4 x i8> %a) {854; CHECK-SD-LABEL: smaxv_v4i8:855; CHECK-SD: // %bb.0: // %entry856; CHECK-SD-NEXT: shl v0.4h, v0.4h, #8857; CHECK-SD-NEXT: sshr v0.4h, v0.4h, #8858; CHECK-SD-NEXT: smaxv h0, v0.4h859; CHECK-SD-NEXT: fmov w0, s0860; CHECK-SD-NEXT: ret861;862; CHECK-GI-LABEL: smaxv_v4i8:863; CHECK-GI: // %bb.0: // %entry864; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0865; CHECK-GI-NEXT: umov w8, v0.h[0]866; CHECK-GI-NEXT: umov w9, v0.h[1]867; CHECK-GI-NEXT: umov w10, v0.h[2]868; CHECK-GI-NEXT: umov w12, v0.h[3]869; CHECK-GI-NEXT: sxtb w11, w8870; CHECK-GI-NEXT: cmp w11, w9, sxtb871; CHECK-GI-NEXT: sxtb w11, w10872; CHECK-GI-NEXT: csel w8, w8, w9, gt873; CHECK-GI-NEXT: cmp w11, w12, sxtb874; CHECK-GI-NEXT: sxtb w9, w8875; CHECK-GI-NEXT: csel w10, w10, w12, gt876; CHECK-GI-NEXT: cmp w9, w10, sxtb877; CHECK-GI-NEXT: csel w0, w8, w10, gt878; CHECK-GI-NEXT: ret879entry:880 %arg1 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> %a)881 ret i8 %arg1882}883 884define i8 @smaxv_v8i8(<8 x i8> %a) {885; CHECK-LABEL: smaxv_v8i8:886; CHECK: // %bb.0: // %entry887; CHECK-NEXT: smaxv b0, v0.8b888; CHECK-NEXT: fmov w0, s0889; CHECK-NEXT: ret890entry:891 %arg1 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> %a)892 ret i8 %arg1893}894 895define i8 @smaxv_v16i8(<16 x i8> %a) {896; CHECK-LABEL: smaxv_v16i8:897; CHECK: // %bb.0: // %entry898; CHECK-NEXT: smaxv b0, v0.16b899; CHECK-NEXT: fmov w0, s0900; CHECK-NEXT: ret901entry:902 %arg1 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %a)903 ret i8 %arg1904}905 906define i8 @smaxv_v32i8(<32 x i8> %a) {907; CHECK-LABEL: smaxv_v32i8:908; CHECK: // %bb.0: // %entry909; CHECK-NEXT: smax v0.16b, v0.16b, v1.16b910; CHECK-NEXT: smaxv b0, v0.16b911; CHECK-NEXT: fmov w0, s0912; CHECK-NEXT: ret913entry:914 %arg1 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> %a)915 ret i8 %arg1916}917 918define i16 @smaxv_v2i16(<2 x i16> %a) {919; CHECK-SD-LABEL: smaxv_v2i16:920; CHECK-SD: // %bb.0: // %entry921; CHECK-SD-NEXT: shl v0.2s, v0.2s, #16922; CHECK-SD-NEXT: sshr v0.2s, v0.2s, #16923; CHECK-SD-NEXT: smaxp v0.2s, v0.2s, v0.2s924; CHECK-SD-NEXT: fmov w0, s0925; CHECK-SD-NEXT: ret926;927; CHECK-GI-LABEL: smaxv_v2i16:928; CHECK-GI: // %bb.0: // %entry929; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0930; CHECK-GI-NEXT: mov s1, v0.s[1]931; CHECK-GI-NEXT: fmov w8, s0932; CHECK-GI-NEXT: sxth w8, w8933; CHECK-GI-NEXT: fmov w9, s1934; CHECK-GI-NEXT: cmp w8, w9, sxth935; CHECK-GI-NEXT: fcsel s0, s0, s1, gt936; CHECK-GI-NEXT: fmov w0, s0937; CHECK-GI-NEXT: ret938entry:939 %arg1 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> %a)940 ret i16 %arg1941}942 943define i16 @smaxv_v3i16(<3 x i16> %a) {944; CHECK-SD-LABEL: smaxv_v3i16:945; CHECK-SD: // %bb.0: // %entry946; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0947; CHECK-SD-NEXT: mov w8, #-32768 // =0xffff8000948; CHECK-SD-NEXT: mov v0.h[3], w8949; CHECK-SD-NEXT: smaxv h0, v0.4h950; CHECK-SD-NEXT: fmov w0, s0951; CHECK-SD-NEXT: ret952;953; CHECK-GI-LABEL: smaxv_v3i16:954; CHECK-GI: // %bb.0: // %entry955; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0956; CHECK-GI-NEXT: mov w8, #32768 // =0x8000957; CHECK-GI-NEXT: mov v0.h[3], w8958; CHECK-GI-NEXT: smaxv h0, v0.4h959; CHECK-GI-NEXT: fmov w0, s0960; CHECK-GI-NEXT: ret961entry:962 %arg1 = call i16 @llvm.vector.reduce.smax.v3i16(<3 x i16> %a)963 ret i16 %arg1964}965 966define i16 @smaxv_v4i16(<4 x i16> %a) {967; CHECK-LABEL: smaxv_v4i16:968; CHECK: // %bb.0: // %entry969; CHECK-NEXT: smaxv h0, v0.4h970; CHECK-NEXT: fmov w0, s0971; CHECK-NEXT: ret972entry:973 %arg1 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> %a)974 ret i16 %arg1975}976 977define i16 @smaxv_v8i16(<8 x i16> %a) {978; CHECK-LABEL: smaxv_v8i16:979; CHECK: // %bb.0: // %entry980; CHECK-NEXT: smaxv h0, v0.8h981; CHECK-NEXT: fmov w0, s0982; CHECK-NEXT: ret983entry:984 %arg1 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %a)985 ret i16 %arg1986}987 988define i16 @smaxv_v16i16(<16 x i16> %a) {989; CHECK-LABEL: smaxv_v16i16:990; CHECK: // %bb.0: // %entry991; CHECK-NEXT: smax v0.8h, v0.8h, v1.8h992; CHECK-NEXT: smaxv h0, v0.8h993; CHECK-NEXT: fmov w0, s0994; CHECK-NEXT: ret995entry:996 %arg1 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> %a)997 ret i16 %arg1998}999 1000define i32 @smaxv_v2i32(<2 x i32> %a) {1001; CHECK-LABEL: smaxv_v2i32:1002; CHECK: // %bb.0: // %entry1003; CHECK-NEXT: smaxp v0.2s, v0.2s, v0.2s1004; CHECK-NEXT: fmov w0, s01005; CHECK-NEXT: ret1006entry:1007 %arg1 = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> %a)1008 ret i32 %arg11009}1010 1011define i32 @smaxv_v3i32(<3 x i32> %a) {1012; CHECK-LABEL: smaxv_v3i32:1013; CHECK: // %bb.0: // %entry1014; CHECK-NEXT: mov w8, #-2147483648 // =0x800000001015; CHECK-NEXT: mov v0.s[3], w81016; CHECK-NEXT: smaxv s0, v0.4s1017; CHECK-NEXT: fmov w0, s01018; CHECK-NEXT: ret1019entry:1020 %arg1 = call i32 @llvm.vector.reduce.smax.v3i32(<3 x i32> %a)1021 ret i32 %arg11022}1023 1024define i32 @smaxv_v4i32(<4 x i32> %a) {1025; CHECK-LABEL: smaxv_v4i32:1026; CHECK: // %bb.0: // %entry1027; CHECK-NEXT: smaxv s0, v0.4s1028; CHECK-NEXT: fmov w0, s01029; CHECK-NEXT: ret1030entry:1031 %arg1 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %a)1032 ret i32 %arg11033}1034 1035define i32 @smaxv_v8i32(<8 x i32> %a) {1036; CHECK-LABEL: smaxv_v8i32:1037; CHECK: // %bb.0: // %entry1038; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s1039; CHECK-NEXT: smaxv s0, v0.4s1040; CHECK-NEXT: fmov w0, s01041; CHECK-NEXT: ret1042entry:1043 %arg1 = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> %a)1044 ret i32 %arg11045}1046 1047define i64 @smaxv_v2i64(<2 x i64> %a) {1048; CHECK-SD-LABEL: smaxv_v2i64:1049; CHECK-SD: // %bb.0: // %entry1050; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #81051; CHECK-SD-NEXT: cmgt d2, d0, d11052; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b1053; CHECK-SD-NEXT: fmov x0, d01054; CHECK-SD-NEXT: ret1055;1056; CHECK-GI-LABEL: smaxv_v2i64:1057; CHECK-GI: // %bb.0: // %entry1058; CHECK-GI-NEXT: mov d1, v0.d[1]1059; CHECK-GI-NEXT: fmov x8, d01060; CHECK-GI-NEXT: fmov x9, d11061; CHECK-GI-NEXT: cmp x8, x91062; CHECK-GI-NEXT: fcsel d0, d0, d1, gt1063; CHECK-GI-NEXT: fmov x0, d01064; CHECK-GI-NEXT: ret1065entry:1066 %arg1 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> %a)1067 ret i64 %arg11068}1069 1070define i64 @smaxv_v3i64(<3 x i64> %a) {1071; CHECK-SD-LABEL: smaxv_v3i64:1072; CHECK-SD: // %bb.0: // %entry1073; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q21074; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01075; CHECK-SD-NEXT: mov x8, #-9223372036854775808 // =0x80000000000000001076; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q11077; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]1078; CHECK-SD-NEXT: mov v2.d[1], x81079; CHECK-SD-NEXT: cmgt v1.2d, v0.2d, v2.2d1080; CHECK-SD-NEXT: bif v0.16b, v2.16b, v1.16b1081; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #81082; CHECK-SD-NEXT: cmgt d2, d0, d11083; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b1084; CHECK-SD-NEXT: fmov x0, d01085; CHECK-SD-NEXT: ret1086;1087; CHECK-GI-LABEL: smaxv_v3i64:1088; CHECK-GI: // %bb.0: // %entry1089; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01090; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q21091; CHECK-GI-NEXT: mov x8, #-9223372036854775808 // =0x80000000000000001092; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q11093; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]1094; CHECK-GI-NEXT: mov v2.d[1], x81095; CHECK-GI-NEXT: cmgt v1.2d, v0.2d, v2.2d1096; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b1097; CHECK-GI-NEXT: mov d1, v0.d[1]1098; CHECK-GI-NEXT: fmov x8, d01099; CHECK-GI-NEXT: fmov x9, d11100; CHECK-GI-NEXT: cmp x8, x91101; CHECK-GI-NEXT: fcsel d0, d0, d1, gt1102; CHECK-GI-NEXT: fmov x0, d01103; CHECK-GI-NEXT: ret1104entry:1105 %arg1 = call i64 @llvm.vector.reduce.smax.v3i64(<3 x i64> %a)1106 ret i64 %arg11107}1108 1109define i64 @smaxv_v4i64(<4 x i64> %a) {1110; CHECK-SD-LABEL: smaxv_v4i64:1111; CHECK-SD: // %bb.0: // %entry1112; CHECK-SD-NEXT: cmgt v2.2d, v0.2d, v1.2d1113; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b1114; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #81115; CHECK-SD-NEXT: cmgt d2, d0, d11116; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b1117; CHECK-SD-NEXT: fmov x0, d01118; CHECK-SD-NEXT: ret1119;1120; CHECK-GI-LABEL: smaxv_v4i64:1121; CHECK-GI: // %bb.0: // %entry1122; CHECK-GI-NEXT: cmgt v2.2d, v0.2d, v1.2d1123; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b1124; CHECK-GI-NEXT: mov d1, v0.d[1]1125; CHECK-GI-NEXT: fmov x8, d01126; CHECK-GI-NEXT: fmov x9, d11127; CHECK-GI-NEXT: cmp x8, x91128; CHECK-GI-NEXT: fcsel d0, d0, d1, gt1129; CHECK-GI-NEXT: fmov x0, d01130; CHECK-GI-NEXT: ret1131entry:1132 %arg1 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> %a)1133 ret i64 %arg11134}1135 1136define i128 @smaxv_v2i128(<2 x i128> %a) {1137; CHECK-SD-LABEL: smaxv_v2i128:1138; CHECK-SD: // %bb.0: // %entry1139; CHECK-SD-NEXT: cmp x2, x01140; CHECK-SD-NEXT: sbcs xzr, x3, x11141; CHECK-SD-NEXT: csel x0, x0, x2, lt1142; CHECK-SD-NEXT: csel x1, x1, x3, lt1143; CHECK-SD-NEXT: ret1144;1145; CHECK-GI-LABEL: smaxv_v2i128:1146; CHECK-GI: // %bb.0: // %entry1147; CHECK-GI-NEXT: cmp x0, x21148; CHECK-GI-NEXT: cset w8, hi1149; CHECK-GI-NEXT: cmp x1, x31150; CHECK-GI-NEXT: cset w9, gt1151; CHECK-GI-NEXT: csel w8, w8, w9, eq1152; CHECK-GI-NEXT: tst w8, #0x11153; CHECK-GI-NEXT: csel x0, x0, x2, ne1154; CHECK-GI-NEXT: csel x1, x1, x3, ne1155; CHECK-GI-NEXT: ret1156entry:1157 %arg1 = call i128 @llvm.vector.reduce.smax.v2i128(<2 x i128> %a)1158 ret i128 %arg11159}1160 1161define i8 @uminv_v2i8(<2 x i8> %a) {1162; CHECK-SD-LABEL: uminv_v2i8:1163; CHECK-SD: // %bb.0: // %entry1164; CHECK-SD-NEXT: movi d1, #0x0000ff000000ff1165; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b1166; CHECK-SD-NEXT: uminp v0.2s, v0.2s, v0.2s1167; CHECK-SD-NEXT: fmov w0, s01168; CHECK-SD-NEXT: ret1169;1170; CHECK-GI-LABEL: uminv_v2i8:1171; CHECK-GI: // %bb.0: // %entry1172; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01173; CHECK-GI-NEXT: mov s1, v0.s[1]1174; CHECK-GI-NEXT: fmov w8, s01175; CHECK-GI-NEXT: and w8, w8, #0xff1176; CHECK-GI-NEXT: fmov w9, s11177; CHECK-GI-NEXT: cmp w8, w9, uxtb1178; CHECK-GI-NEXT: fcsel s0, s0, s1, lo1179; CHECK-GI-NEXT: fmov w0, s01180; CHECK-GI-NEXT: ret1181entry:1182 %arg1 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> %a)1183 ret i8 %arg11184}1185 1186define i8 @uminv_v3i8(<3 x i8> %a) {1187; CHECK-SD-LABEL: uminv_v3i8:1188; CHECK-SD: // %bb.0: // %entry1189; CHECK-SD-NEXT: movi d0, #0xff00ff00ff00ff1190; CHECK-SD-NEXT: mov v0.h[0], w01191; CHECK-SD-NEXT: mov v0.h[1], w11192; CHECK-SD-NEXT: mov v0.h[2], w21193; CHECK-SD-NEXT: bic v0.4h, #255, lsl #81194; CHECK-SD-NEXT: uminv h0, v0.4h1195; CHECK-SD-NEXT: fmov w0, s01196; CHECK-SD-NEXT: ret1197;1198; CHECK-GI-LABEL: uminv_v3i8:1199; CHECK-GI: // %bb.0: // %entry1200; CHECK-GI-NEXT: and w8, w0, #0xff1201; CHECK-GI-NEXT: cmp w8, w1, uxtb1202; CHECK-GI-NEXT: csel w8, w0, w1, lo1203; CHECK-GI-NEXT: and w9, w8, #0xff1204; CHECK-GI-NEXT: cmp w9, w2, uxtb1205; CHECK-GI-NEXT: csel w0, w8, w2, lo1206; CHECK-GI-NEXT: ret1207entry:1208 %arg1 = call i8 @llvm.vector.reduce.umin.v3i8(<3 x i8> %a)1209 ret i8 %arg11210}1211 1212define i8 @uminv_v4i8(<4 x i8> %a) {1213; CHECK-SD-LABEL: uminv_v4i8:1214; CHECK-SD: // %bb.0: // %entry1215; CHECK-SD-NEXT: bic v0.4h, #255, lsl #81216; CHECK-SD-NEXT: uminv h0, v0.4h1217; CHECK-SD-NEXT: fmov w0, s01218; CHECK-SD-NEXT: ret1219;1220; CHECK-GI-LABEL: uminv_v4i8:1221; CHECK-GI: // %bb.0: // %entry1222; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01223; CHECK-GI-NEXT: umov w8, v0.h[0]1224; CHECK-GI-NEXT: umov w9, v0.h[1]1225; CHECK-GI-NEXT: umov w10, v0.h[2]1226; CHECK-GI-NEXT: umov w11, v0.h[3]1227; CHECK-GI-NEXT: and w12, w8, #0xff1228; CHECK-GI-NEXT: cmp w12, w9, uxtb1229; CHECK-GI-NEXT: and w12, w10, #0xff1230; CHECK-GI-NEXT: csel w8, w8, w9, lo1231; CHECK-GI-NEXT: cmp w12, w11, uxtb1232; CHECK-GI-NEXT: csel w9, w10, w11, lo1233; CHECK-GI-NEXT: and w10, w8, #0xff1234; CHECK-GI-NEXT: cmp w10, w9, uxtb1235; CHECK-GI-NEXT: csel w0, w8, w9, lo1236; CHECK-GI-NEXT: ret1237entry:1238 %arg1 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> %a)1239 ret i8 %arg11240}1241 1242define i8 @uminv_v8i8(<8 x i8> %a) {1243; CHECK-LABEL: uminv_v8i8:1244; CHECK: // %bb.0: // %entry1245; CHECK-NEXT: uminv b0, v0.8b1246; CHECK-NEXT: fmov w0, s01247; CHECK-NEXT: ret1248entry:1249 %arg1 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> %a)1250 ret i8 %arg11251}1252 1253define i8 @uminv_v16i8(<16 x i8> %a) {1254; CHECK-LABEL: uminv_v16i8:1255; CHECK: // %bb.0: // %entry1256; CHECK-NEXT: uminv b0, v0.16b1257; CHECK-NEXT: fmov w0, s01258; CHECK-NEXT: ret1259entry:1260 %arg1 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %a)1261 ret i8 %arg11262}1263 1264define i8 @uminv_v32i8(<32 x i8> %a) {1265; CHECK-LABEL: uminv_v32i8:1266; CHECK: // %bb.0: // %entry1267; CHECK-NEXT: umin v0.16b, v0.16b, v1.16b1268; CHECK-NEXT: uminv b0, v0.16b1269; CHECK-NEXT: fmov w0, s01270; CHECK-NEXT: ret1271entry:1272 %arg1 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> %a)1273 ret i8 %arg11274}1275 1276define i16 @uminv_v2i16(<2 x i16> %a) {1277; CHECK-SD-LABEL: uminv_v2i16:1278; CHECK-SD: // %bb.0: // %entry1279; CHECK-SD-NEXT: movi d1, #0x00ffff0000ffff1280; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b1281; CHECK-SD-NEXT: uminp v0.2s, v0.2s, v0.2s1282; CHECK-SD-NEXT: fmov w0, s01283; CHECK-SD-NEXT: ret1284;1285; CHECK-GI-LABEL: uminv_v2i16:1286; CHECK-GI: // %bb.0: // %entry1287; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01288; CHECK-GI-NEXT: mov s1, v0.s[1]1289; CHECK-GI-NEXT: fmov w8, s01290; CHECK-GI-NEXT: and w8, w8, #0xffff1291; CHECK-GI-NEXT: fmov w9, s11292; CHECK-GI-NEXT: cmp w8, w9, uxth1293; CHECK-GI-NEXT: fcsel s0, s0, s1, lo1294; CHECK-GI-NEXT: fmov w0, s01295; CHECK-GI-NEXT: ret1296entry:1297 %arg1 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> %a)1298 ret i16 %arg11299}1300 1301define i16 @uminv_v3i16(<3 x i16> %a) {1302; CHECK-SD-LABEL: uminv_v3i16:1303; CHECK-SD: // %bb.0: // %entry1304; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01305; CHECK-SD-NEXT: mov w8, #-1 // =0xffffffff1306; CHECK-SD-NEXT: mov v0.h[3], w81307; CHECK-SD-NEXT: uminv h0, v0.4h1308; CHECK-SD-NEXT: fmov w0, s01309; CHECK-SD-NEXT: ret1310;1311; CHECK-GI-LABEL: uminv_v3i16:1312; CHECK-GI: // %bb.0: // %entry1313; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01314; CHECK-GI-NEXT: mov w8, #65535 // =0xffff1315; CHECK-GI-NEXT: mov v0.h[3], w81316; CHECK-GI-NEXT: uminv h0, v0.4h1317; CHECK-GI-NEXT: fmov w0, s01318; CHECK-GI-NEXT: ret1319entry:1320 %arg1 = call i16 @llvm.vector.reduce.umin.v3i16(<3 x i16> %a)1321 ret i16 %arg11322}1323 1324define i16 @uminv_v4i16(<4 x i16> %a) {1325; CHECK-LABEL: uminv_v4i16:1326; CHECK: // %bb.0: // %entry1327; CHECK-NEXT: uminv h0, v0.4h1328; CHECK-NEXT: fmov w0, s01329; CHECK-NEXT: ret1330entry:1331 %arg1 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> %a)1332 ret i16 %arg11333}1334 1335define i16 @uminv_v8i16(<8 x i16> %a) {1336; CHECK-LABEL: uminv_v8i16:1337; CHECK: // %bb.0: // %entry1338; CHECK-NEXT: uminv h0, v0.8h1339; CHECK-NEXT: fmov w0, s01340; CHECK-NEXT: ret1341entry:1342 %arg1 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> %a)1343 ret i16 %arg11344}1345 1346define i16 @uminv_v16i16(<16 x i16> %a) {1347; CHECK-LABEL: uminv_v16i16:1348; CHECK: // %bb.0: // %entry1349; CHECK-NEXT: umin v0.8h, v0.8h, v1.8h1350; CHECK-NEXT: uminv h0, v0.8h1351; CHECK-NEXT: fmov w0, s01352; CHECK-NEXT: ret1353entry:1354 %arg1 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> %a)1355 ret i16 %arg11356}1357 1358define i32 @uminv_v2i32(<2 x i32> %a) {1359; CHECK-LABEL: uminv_v2i32:1360; CHECK: // %bb.0: // %entry1361; CHECK-NEXT: uminp v0.2s, v0.2s, v0.2s1362; CHECK-NEXT: fmov w0, s01363; CHECK-NEXT: ret1364entry:1365 %arg1 = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> %a)1366 ret i32 %arg11367}1368 1369define i32 @uminv_v3i32(<3 x i32> %a) {1370; CHECK-LABEL: uminv_v3i32:1371; CHECK: // %bb.0: // %entry1372; CHECK-NEXT: mov w8, #-1 // =0xffffffff1373; CHECK-NEXT: mov v0.s[3], w81374; CHECK-NEXT: uminv s0, v0.4s1375; CHECK-NEXT: fmov w0, s01376; CHECK-NEXT: ret1377entry:1378 %arg1 = call i32 @llvm.vector.reduce.umin.v3i32(<3 x i32> %a)1379 ret i32 %arg11380}1381 1382define i32 @uminv_v4i32(<4 x i32> %a) {1383; CHECK-LABEL: uminv_v4i32:1384; CHECK: // %bb.0: // %entry1385; CHECK-NEXT: uminv s0, v0.4s1386; CHECK-NEXT: fmov w0, s01387; CHECK-NEXT: ret1388entry:1389 %arg1 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %a)1390 ret i32 %arg11391}1392 1393define i32 @uminv_v8i32(<8 x i32> %a) {1394; CHECK-LABEL: uminv_v8i32:1395; CHECK: // %bb.0: // %entry1396; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s1397; CHECK-NEXT: uminv s0, v0.4s1398; CHECK-NEXT: fmov w0, s01399; CHECK-NEXT: ret1400entry:1401 %arg1 = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> %a)1402 ret i32 %arg11403}1404 1405define i64 @uminv_v2i64(<2 x i64> %a) {1406; CHECK-SD-LABEL: uminv_v2i64:1407; CHECK-SD: // %bb.0: // %entry1408; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #81409; CHECK-SD-NEXT: cmhi d2, d1, d01410; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b1411; CHECK-SD-NEXT: fmov x0, d01412; CHECK-SD-NEXT: ret1413;1414; CHECK-GI-LABEL: uminv_v2i64:1415; CHECK-GI: // %bb.0: // %entry1416; CHECK-GI-NEXT: mov d1, v0.d[1]1417; CHECK-GI-NEXT: fmov x8, d01418; CHECK-GI-NEXT: fmov x9, d11419; CHECK-GI-NEXT: cmp x8, x91420; CHECK-GI-NEXT: fcsel d0, d0, d1, lo1421; CHECK-GI-NEXT: fmov x0, d01422; CHECK-GI-NEXT: ret1423entry:1424 %arg1 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> %a)1425 ret i64 %arg11426}1427 1428define i64 @uminv_v3i64(<3 x i64> %a) {1429; CHECK-SD-LABEL: uminv_v3i64:1430; CHECK-SD: // %bb.0: // %entry1431; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q21432; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01433; CHECK-SD-NEXT: mov x8, #-1 // =0xffffffffffffffff1434; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q11435; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]1436; CHECK-SD-NEXT: mov v2.d[1], x81437; CHECK-SD-NEXT: cmhi v1.2d, v2.2d, v0.2d1438; CHECK-SD-NEXT: bif v0.16b, v2.16b, v1.16b1439; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #81440; CHECK-SD-NEXT: cmhi d2, d1, d01441; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b1442; CHECK-SD-NEXT: fmov x0, d01443; CHECK-SD-NEXT: ret1444;1445; CHECK-GI-LABEL: uminv_v3i64:1446; CHECK-GI: // %bb.0: // %entry1447; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01448; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q21449; CHECK-GI-NEXT: mov x8, #-1 // =0xffffffffffffffff1450; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q11451; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]1452; CHECK-GI-NEXT: mov v2.d[1], x81453; CHECK-GI-NEXT: cmhi v1.2d, v2.2d, v0.2d1454; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b1455; CHECK-GI-NEXT: mov d1, v0.d[1]1456; CHECK-GI-NEXT: fmov x8, d01457; CHECK-GI-NEXT: fmov x9, d11458; CHECK-GI-NEXT: cmp x8, x91459; CHECK-GI-NEXT: fcsel d0, d0, d1, lo1460; CHECK-GI-NEXT: fmov x0, d01461; CHECK-GI-NEXT: ret1462entry:1463 %arg1 = call i64 @llvm.vector.reduce.umin.v3i64(<3 x i64> %a)1464 ret i64 %arg11465}1466 1467define i64 @uminv_v4i64(<4 x i64> %a) {1468; CHECK-SD-LABEL: uminv_v4i64:1469; CHECK-SD: // %bb.0: // %entry1470; CHECK-SD-NEXT: cmhi v2.2d, v1.2d, v0.2d1471; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b1472; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #81473; CHECK-SD-NEXT: cmhi d2, d1, d01474; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b1475; CHECK-SD-NEXT: fmov x0, d01476; CHECK-SD-NEXT: ret1477;1478; CHECK-GI-LABEL: uminv_v4i64:1479; CHECK-GI: // %bb.0: // %entry1480; CHECK-GI-NEXT: cmhi v2.2d, v1.2d, v0.2d1481; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b1482; CHECK-GI-NEXT: mov d1, v0.d[1]1483; CHECK-GI-NEXT: fmov x8, d01484; CHECK-GI-NEXT: fmov x9, d11485; CHECK-GI-NEXT: cmp x8, x91486; CHECK-GI-NEXT: fcsel d0, d0, d1, lo1487; CHECK-GI-NEXT: fmov x0, d01488; CHECK-GI-NEXT: ret1489entry:1490 %arg1 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> %a)1491 ret i64 %arg11492}1493 1494define i128 @uminv_v2i128(<2 x i128> %a) {1495; CHECK-SD-LABEL: uminv_v2i128:1496; CHECK-SD: // %bb.0: // %entry1497; CHECK-SD-NEXT: cmp x0, x21498; CHECK-SD-NEXT: sbcs xzr, x1, x31499; CHECK-SD-NEXT: csel x0, x0, x2, lo1500; CHECK-SD-NEXT: csel x1, x1, x3, lo1501; CHECK-SD-NEXT: ret1502;1503; CHECK-GI-LABEL: uminv_v2i128:1504; CHECK-GI: // %bb.0: // %entry1505; CHECK-GI-NEXT: cmp x0, x21506; CHECK-GI-NEXT: cset w8, lo1507; CHECK-GI-NEXT: cmp x1, x31508; CHECK-GI-NEXT: cset w9, lo1509; CHECK-GI-NEXT: csel w8, w8, w9, eq1510; CHECK-GI-NEXT: tst w8, #0x11511; CHECK-GI-NEXT: csel x0, x0, x2, ne1512; CHECK-GI-NEXT: csel x1, x1, x3, ne1513; CHECK-GI-NEXT: ret1514entry:1515 %arg1 = call i128 @llvm.vector.reduce.umin.v2i128(<2 x i128> %a)1516 ret i128 %arg11517}1518 1519define i8 @umaxv_v2i8(<2 x i8> %a) {1520; CHECK-SD-LABEL: umaxv_v2i8:1521; CHECK-SD: // %bb.0: // %entry1522; CHECK-SD-NEXT: movi d1, #0x0000ff000000ff1523; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b1524; CHECK-SD-NEXT: umaxp v0.2s, v0.2s, v0.2s1525; CHECK-SD-NEXT: fmov w0, s01526; CHECK-SD-NEXT: ret1527;1528; CHECK-GI-LABEL: umaxv_v2i8:1529; CHECK-GI: // %bb.0: // %entry1530; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01531; CHECK-GI-NEXT: mov s1, v0.s[1]1532; CHECK-GI-NEXT: fmov w8, s01533; CHECK-GI-NEXT: and w8, w8, #0xff1534; CHECK-GI-NEXT: fmov w9, s11535; CHECK-GI-NEXT: cmp w8, w9, uxtb1536; CHECK-GI-NEXT: fcsel s0, s0, s1, hi1537; CHECK-GI-NEXT: fmov w0, s01538; CHECK-GI-NEXT: ret1539entry:1540 %arg1 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> %a)1541 ret i8 %arg11542}1543 1544define i8 @umaxv_v3i8(<3 x i8> %a) {1545; CHECK-SD-LABEL: umaxv_v3i8:1546; CHECK-SD: // %bb.0: // %entry1547; CHECK-SD-NEXT: movi v0.2d, #00000000000000001548; CHECK-SD-NEXT: mov v0.h[0], w01549; CHECK-SD-NEXT: mov v0.h[1], w11550; CHECK-SD-NEXT: mov v0.h[2], w21551; CHECK-SD-NEXT: bic v0.4h, #255, lsl #81552; CHECK-SD-NEXT: umaxv h0, v0.4h1553; CHECK-SD-NEXT: fmov w0, s01554; CHECK-SD-NEXT: ret1555;1556; CHECK-GI-LABEL: umaxv_v3i8:1557; CHECK-GI: // %bb.0: // %entry1558; CHECK-GI-NEXT: and w8, w0, #0xff1559; CHECK-GI-NEXT: cmp w8, w1, uxtb1560; CHECK-GI-NEXT: csel w8, w0, w1, hi1561; CHECK-GI-NEXT: and w9, w8, #0xff1562; CHECK-GI-NEXT: cmp w9, w2, uxtb1563; CHECK-GI-NEXT: csel w0, w8, w2, hi1564; CHECK-GI-NEXT: ret1565entry:1566 %arg1 = call i8 @llvm.vector.reduce.umax.v3i8(<3 x i8> %a)1567 ret i8 %arg11568}1569 1570define i8 @umaxv_v4i8(<4 x i8> %a) {1571; CHECK-SD-LABEL: umaxv_v4i8:1572; CHECK-SD: // %bb.0: // %entry1573; CHECK-SD-NEXT: bic v0.4h, #255, lsl #81574; CHECK-SD-NEXT: umaxv h0, v0.4h1575; CHECK-SD-NEXT: fmov w0, s01576; CHECK-SD-NEXT: ret1577;1578; CHECK-GI-LABEL: umaxv_v4i8:1579; CHECK-GI: // %bb.0: // %entry1580; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01581; CHECK-GI-NEXT: umov w8, v0.h[0]1582; CHECK-GI-NEXT: umov w9, v0.h[1]1583; CHECK-GI-NEXT: umov w10, v0.h[2]1584; CHECK-GI-NEXT: umov w11, v0.h[3]1585; CHECK-GI-NEXT: and w12, w8, #0xff1586; CHECK-GI-NEXT: cmp w12, w9, uxtb1587; CHECK-GI-NEXT: and w12, w10, #0xff1588; CHECK-GI-NEXT: csel w8, w8, w9, hi1589; CHECK-GI-NEXT: cmp w12, w11, uxtb1590; CHECK-GI-NEXT: csel w9, w10, w11, hi1591; CHECK-GI-NEXT: and w10, w8, #0xff1592; CHECK-GI-NEXT: cmp w10, w9, uxtb1593; CHECK-GI-NEXT: csel w0, w8, w9, hi1594; CHECK-GI-NEXT: ret1595entry:1596 %arg1 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> %a)1597 ret i8 %arg11598}1599 1600define i8 @umaxv_v8i8(<8 x i8> %a) {1601; CHECK-LABEL: umaxv_v8i8:1602; CHECK: // %bb.0: // %entry1603; CHECK-NEXT: umaxv b0, v0.8b1604; CHECK-NEXT: fmov w0, s01605; CHECK-NEXT: ret1606entry:1607 %arg1 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> %a)1608 ret i8 %arg11609}1610 1611define i8 @umaxv_v16i8(<16 x i8> %a) {1612; CHECK-LABEL: umaxv_v16i8:1613; CHECK: // %bb.0: // %entry1614; CHECK-NEXT: umaxv b0, v0.16b1615; CHECK-NEXT: fmov w0, s01616; CHECK-NEXT: ret1617entry:1618 %arg1 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %a)1619 ret i8 %arg11620}1621 1622define i8 @umaxv_v32i8(<32 x i8> %a) {1623; CHECK-LABEL: umaxv_v32i8:1624; CHECK: // %bb.0: // %entry1625; CHECK-NEXT: umax v0.16b, v0.16b, v1.16b1626; CHECK-NEXT: umaxv b0, v0.16b1627; CHECK-NEXT: fmov w0, s01628; CHECK-NEXT: ret1629entry:1630 %arg1 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> %a)1631 ret i8 %arg11632}1633 1634define i16 @umaxv_v2i16(<2 x i16> %a) {1635; CHECK-SD-LABEL: umaxv_v2i16:1636; CHECK-SD: // %bb.0: // %entry1637; CHECK-SD-NEXT: movi d1, #0x00ffff0000ffff1638; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b1639; CHECK-SD-NEXT: umaxp v0.2s, v0.2s, v0.2s1640; CHECK-SD-NEXT: fmov w0, s01641; CHECK-SD-NEXT: ret1642;1643; CHECK-GI-LABEL: umaxv_v2i16:1644; CHECK-GI: // %bb.0: // %entry1645; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01646; CHECK-GI-NEXT: mov s1, v0.s[1]1647; CHECK-GI-NEXT: fmov w8, s01648; CHECK-GI-NEXT: and w8, w8, #0xffff1649; CHECK-GI-NEXT: fmov w9, s11650; CHECK-GI-NEXT: cmp w8, w9, uxth1651; CHECK-GI-NEXT: fcsel s0, s0, s1, hi1652; CHECK-GI-NEXT: fmov w0, s01653; CHECK-GI-NEXT: ret1654entry:1655 %arg1 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> %a)1656 ret i16 %arg11657}1658 1659define i16 @umaxv_v3i16(<3 x i16> %a) {1660; CHECK-SD-LABEL: umaxv_v3i16:1661; CHECK-SD: // %bb.0: // %entry1662; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01663; CHECK-SD-NEXT: mov v0.h[3], wzr1664; CHECK-SD-NEXT: umaxv h0, v0.4h1665; CHECK-SD-NEXT: fmov w0, s01666; CHECK-SD-NEXT: ret1667;1668; CHECK-GI-LABEL: umaxv_v3i16:1669; CHECK-GI: // %bb.0: // %entry1670; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01671; CHECK-GI-NEXT: mov w8, #0 // =0x01672; CHECK-GI-NEXT: mov v0.h[3], w81673; CHECK-GI-NEXT: umaxv h0, v0.4h1674; CHECK-GI-NEXT: fmov w0, s01675; CHECK-GI-NEXT: ret1676entry:1677 %arg1 = call i16 @llvm.vector.reduce.umax.v3i16(<3 x i16> %a)1678 ret i16 %arg11679}1680 1681define i16 @umaxv_v4i16(<4 x i16> %a) {1682; CHECK-LABEL: umaxv_v4i16:1683; CHECK: // %bb.0: // %entry1684; CHECK-NEXT: umaxv h0, v0.4h1685; CHECK-NEXT: fmov w0, s01686; CHECK-NEXT: ret1687entry:1688 %arg1 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> %a)1689 ret i16 %arg11690}1691 1692define i16 @umaxv_v8i16(<8 x i16> %a) {1693; CHECK-LABEL: umaxv_v8i16:1694; CHECK: // %bb.0: // %entry1695; CHECK-NEXT: umaxv h0, v0.8h1696; CHECK-NEXT: fmov w0, s01697; CHECK-NEXT: ret1698entry:1699 %arg1 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> %a)1700 ret i16 %arg11701}1702 1703define i16 @umaxv_v16i16(<16 x i16> %a) {1704; CHECK-LABEL: umaxv_v16i16:1705; CHECK: // %bb.0: // %entry1706; CHECK-NEXT: umax v0.8h, v0.8h, v1.8h1707; CHECK-NEXT: umaxv h0, v0.8h1708; CHECK-NEXT: fmov w0, s01709; CHECK-NEXT: ret1710entry:1711 %arg1 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> %a)1712 ret i16 %arg11713}1714 1715define i32 @umaxv_v2i32(<2 x i32> %a) {1716; CHECK-LABEL: umaxv_v2i32:1717; CHECK: // %bb.0: // %entry1718; CHECK-NEXT: umaxp v0.2s, v0.2s, v0.2s1719; CHECK-NEXT: fmov w0, s01720; CHECK-NEXT: ret1721entry:1722 %arg1 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> %a)1723 ret i32 %arg11724}1725 1726define i32 @umaxv_v3i32(<3 x i32> %a) {1727; CHECK-LABEL: umaxv_v3i32:1728; CHECK: // %bb.0: // %entry1729; CHECK-NEXT: mov v0.s[3], wzr1730; CHECK-NEXT: umaxv s0, v0.4s1731; CHECK-NEXT: fmov w0, s01732; CHECK-NEXT: ret1733entry:1734 %arg1 = call i32 @llvm.vector.reduce.umax.v3i32(<3 x i32> %a)1735 ret i32 %arg11736}1737 1738define i32 @umaxv_v4i32(<4 x i32> %a) {1739; CHECK-LABEL: umaxv_v4i32:1740; CHECK: // %bb.0: // %entry1741; CHECK-NEXT: umaxv s0, v0.4s1742; CHECK-NEXT: fmov w0, s01743; CHECK-NEXT: ret1744entry:1745 %arg1 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %a)1746 ret i32 %arg11747}1748 1749define i32 @umaxv_v8i32(<8 x i32> %a) {1750; CHECK-LABEL: umaxv_v8i32:1751; CHECK: // %bb.0: // %entry1752; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s1753; CHECK-NEXT: umaxv s0, v0.4s1754; CHECK-NEXT: fmov w0, s01755; CHECK-NEXT: ret1756entry:1757 %arg1 = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> %a)1758 ret i32 %arg11759}1760 1761define i64 @umaxv_v2i64(<2 x i64> %a) {1762; CHECK-SD-LABEL: umaxv_v2i64:1763; CHECK-SD: // %bb.0: // %entry1764; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #81765; CHECK-SD-NEXT: cmhi d2, d0, d11766; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b1767; CHECK-SD-NEXT: fmov x0, d01768; CHECK-SD-NEXT: ret1769;1770; CHECK-GI-LABEL: umaxv_v2i64:1771; CHECK-GI: // %bb.0: // %entry1772; CHECK-GI-NEXT: mov d1, v0.d[1]1773; CHECK-GI-NEXT: fmov x8, d01774; CHECK-GI-NEXT: fmov x9, d11775; CHECK-GI-NEXT: cmp x8, x91776; CHECK-GI-NEXT: fcsel d0, d0, d1, hi1777; CHECK-GI-NEXT: fmov x0, d01778; CHECK-GI-NEXT: ret1779entry:1780 %arg1 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> %a)1781 ret i64 %arg11782}1783 1784define i64 @umaxv_v3i64(<3 x i64> %a) {1785; CHECK-SD-LABEL: umaxv_v3i64:1786; CHECK-SD: // %bb.0: // %entry1787; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q21788; CHECK-SD-NEXT: mov v3.16b, v2.16b1789; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01790; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q11791; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]1792; CHECK-SD-NEXT: mov v3.d[1], xzr1793; CHECK-SD-NEXT: cmhi v3.2d, v0.2d, v3.2d1794; CHECK-SD-NEXT: ext v4.16b, v3.16b, v3.16b, #81795; CHECK-SD-NEXT: bif v0.16b, v2.16b, v3.16b1796; CHECK-SD-NEXT: and v1.8b, v1.8b, v4.8b1797; CHECK-SD-NEXT: cmhi d2, d0, d11798; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b1799; CHECK-SD-NEXT: fmov x0, d01800; CHECK-SD-NEXT: ret1801;1802; CHECK-GI-LABEL: umaxv_v3i64:1803; CHECK-GI: // %bb.0: // %entry1804; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01805; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q21806; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q11807; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]1808; CHECK-GI-NEXT: mov v2.d[1], xzr1809; CHECK-GI-NEXT: cmhi v1.2d, v0.2d, v2.2d1810; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b1811; CHECK-GI-NEXT: mov d1, v0.d[1]1812; CHECK-GI-NEXT: fmov x8, d01813; CHECK-GI-NEXT: fmov x9, d11814; CHECK-GI-NEXT: cmp x8, x91815; CHECK-GI-NEXT: fcsel d0, d0, d1, hi1816; CHECK-GI-NEXT: fmov x0, d01817; CHECK-GI-NEXT: ret1818entry:1819 %arg1 = call i64 @llvm.vector.reduce.umax.v3i64(<3 x i64> %a)1820 ret i64 %arg11821}1822 1823define i64 @umaxv_v4i64(<4 x i64> %a) {1824; CHECK-SD-LABEL: umaxv_v4i64:1825; CHECK-SD: // %bb.0: // %entry1826; CHECK-SD-NEXT: cmhi v2.2d, v0.2d, v1.2d1827; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b1828; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #81829; CHECK-SD-NEXT: cmhi d2, d0, d11830; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b1831; CHECK-SD-NEXT: fmov x0, d01832; CHECK-SD-NEXT: ret1833;1834; CHECK-GI-LABEL: umaxv_v4i64:1835; CHECK-GI: // %bb.0: // %entry1836; CHECK-GI-NEXT: cmhi v2.2d, v0.2d, v1.2d1837; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b1838; CHECK-GI-NEXT: mov d1, v0.d[1]1839; CHECK-GI-NEXT: fmov x8, d01840; CHECK-GI-NEXT: fmov x9, d11841; CHECK-GI-NEXT: cmp x8, x91842; CHECK-GI-NEXT: fcsel d0, d0, d1, hi1843; CHECK-GI-NEXT: fmov x0, d01844; CHECK-GI-NEXT: ret1845entry:1846 %arg1 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> %a)1847 ret i64 %arg11848}1849 1850define i128 @umaxv_v2i128(<2 x i128> %a) {1851; CHECK-SD-LABEL: umaxv_v2i128:1852; CHECK-SD: // %bb.0: // %entry1853; CHECK-SD-NEXT: cmp x2, x01854; CHECK-SD-NEXT: sbcs xzr, x3, x11855; CHECK-SD-NEXT: csel x0, x0, x2, lo1856; CHECK-SD-NEXT: csel x1, x1, x3, lo1857; CHECK-SD-NEXT: ret1858;1859; CHECK-GI-LABEL: umaxv_v2i128:1860; CHECK-GI: // %bb.0: // %entry1861; CHECK-GI-NEXT: cmp x0, x21862; CHECK-GI-NEXT: cset w8, hi1863; CHECK-GI-NEXT: cmp x1, x31864; CHECK-GI-NEXT: cset w9, hi1865; CHECK-GI-NEXT: csel w8, w8, w9, eq1866; CHECK-GI-NEXT: tst w8, #0x11867; CHECK-GI-NEXT: csel x0, x0, x2, ne1868; CHECK-GI-NEXT: csel x1, x1, x3, ne1869; CHECK-GI-NEXT: ret1870entry:1871 %arg1 = call i128 @llvm.vector.reduce.umax.v2i128(<2 x i128> %a)1872 ret i128 %arg11873}1874