523 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc -mtriple=aarch64 -aarch64-enable-sink-fold=true -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64 -aarch64-enable-sink-fold=true -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5; CHECK-GI: warning: Instruction selection used fallback path for mulv_v3i326 7declare i8 @llvm.vector.reduce.mul.v2i8(<2 x i8>)8declare i8 @llvm.vector.reduce.mul.v3i8(<3 x i8>)9declare i8 @llvm.vector.reduce.mul.v4i8(<4 x i8>)10declare i8 @llvm.vector.reduce.mul.v8i8(<8 x i8>)11declare i8 @llvm.vector.reduce.mul.v16i8(<16 x i8>)12declare i8 @llvm.vector.reduce.mul.v32i8(<32 x i8>)13declare i16 @llvm.vector.reduce.mul.v2i16(<2 x i16>)14declare i16 @llvm.vector.reduce.mul.v3i16(<3 x i16>)15declare i16 @llvm.vector.reduce.mul.v4i16(<4 x i16>)16declare i16 @llvm.vector.reduce.mul.v8i16(<8 x i16>)17declare i16 @llvm.vector.reduce.mul.v16i16(<16 x i16>)18declare i32 @llvm.vector.reduce.mul.v2i32(<2 x i32>)19declare i32 @llvm.vector.reduce.mul.v3i32(<3 x i32>)20declare i32 @llvm.vector.reduce.mul.v4i32(<4 x i32>)21declare i32 @llvm.vector.reduce.mul.v8i32(<8 x i32>)22declare i64 @llvm.vector.reduce.mul.v2i64(<2 x i64>)23declare i64 @llvm.vector.reduce.mul.v3i64(<3 x i64>)24declare i64 @llvm.vector.reduce.mul.v4i64(<4 x i64>)25declare i128 @llvm.vector.reduce.mul.v2i128(<2 x i128>)26 27define i8 @mulv_v2i8(<2 x i8> %a) {28; CHECK-LABEL: mulv_v2i8:29; CHECK: // %bb.0: // %entry30; CHECK-NEXT: // kill: def $d0 killed $d0 def $q031; CHECK-NEXT: mov w8, v0.s[1]32; CHECK-NEXT: fmov w9, s033; CHECK-NEXT: mul w0, w9, w834; CHECK-NEXT: ret35entry:36 %arg1 = call i8 @llvm.vector.reduce.mul.v2i8(<2 x i8> %a)37 ret i8 %arg138}39 40define i8 @mulv_v3i8(<3 x i8> %a) {41; CHECK-LABEL: mulv_v3i8:42; CHECK: // %bb.0: // %entry43; CHECK-NEXT: mul w8, w0, w144; CHECK-NEXT: mul w0, w8, w245; CHECK-NEXT: ret46entry:47 %arg1 = call i8 @llvm.vector.reduce.mul.v3i8(<3 x i8> %a)48 ret i8 %arg149}50 51define i8 @mulv_v4i8(<4 x i8> %a) {52; CHECK-SD-LABEL: mulv_v4i8:53; CHECK-SD: // %bb.0: // %entry54; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q055; CHECK-SD-NEXT: umov w8, v0.h[1]56; CHECK-SD-NEXT: umov w9, v0.h[0]57; CHECK-SD-NEXT: umov w10, v0.h[2]58; CHECK-SD-NEXT: mul w8, w9, w859; CHECK-SD-NEXT: umov w9, v0.h[3]60; CHECK-SD-NEXT: mul w8, w8, w1061; CHECK-SD-NEXT: mul w0, w8, w962; CHECK-SD-NEXT: ret63;64; CHECK-GI-LABEL: mulv_v4i8:65; CHECK-GI: // %bb.0: // %entry66; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q067; CHECK-GI-NEXT: umov w8, v0.h[0]68; CHECK-GI-NEXT: umov w9, v0.h[1]69; CHECK-GI-NEXT: umov w10, v0.h[2]70; CHECK-GI-NEXT: umov w11, v0.h[3]71; CHECK-GI-NEXT: mul w8, w8, w972; CHECK-GI-NEXT: mul w9, w10, w1173; CHECK-GI-NEXT: mul w0, w8, w974; CHECK-GI-NEXT: ret75entry:76 %arg1 = call i8 @llvm.vector.reduce.mul.v4i8(<4 x i8> %a)77 ret i8 %arg178}79 80define i8 @mulv_v8i8(<8 x i8> %a) {81; CHECK-SD-LABEL: mulv_v8i8:82; CHECK-SD: // %bb.0: // %entry83; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q084; CHECK-SD-NEXT: umov w8, v0.b[1]85; CHECK-SD-NEXT: umov w9, v0.b[0]86; CHECK-SD-NEXT: umov w10, v0.b[2]87; CHECK-SD-NEXT: mul w8, w9, w888; CHECK-SD-NEXT: umov w9, v0.b[3]89; CHECK-SD-NEXT: mul w8, w8, w1090; CHECK-SD-NEXT: umov w10, v0.b[4]91; CHECK-SD-NEXT: mul w8, w8, w992; CHECK-SD-NEXT: umov w9, v0.b[5]93; CHECK-SD-NEXT: mul w8, w8, w1094; CHECK-SD-NEXT: umov w10, v0.b[6]95; CHECK-SD-NEXT: mul w8, w8, w996; CHECK-SD-NEXT: umov w9, v0.b[7]97; CHECK-SD-NEXT: mul w8, w8, w1098; CHECK-SD-NEXT: mul w0, w8, w999; CHECK-SD-NEXT: ret100;101; CHECK-GI-LABEL: mulv_v8i8:102; CHECK-GI: // %bb.0: // %entry103; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0104; CHECK-GI-NEXT: umov w8, v0.b[0]105; CHECK-GI-NEXT: umov w9, v0.b[1]106; CHECK-GI-NEXT: umov w10, v0.b[2]107; CHECK-GI-NEXT: umov w11, v0.b[3]108; CHECK-GI-NEXT: umov w12, v0.b[4]109; CHECK-GI-NEXT: umov w13, v0.b[5]110; CHECK-GI-NEXT: umov w14, v0.b[6]111; CHECK-GI-NEXT: umov w15, v0.b[7]112; CHECK-GI-NEXT: mul w8, w8, w9113; CHECK-GI-NEXT: mul w9, w10, w11114; CHECK-GI-NEXT: mul w10, w12, w13115; CHECK-GI-NEXT: mul w11, w14, w15116; CHECK-GI-NEXT: mul w8, w8, w9117; CHECK-GI-NEXT: mul w9, w10, w11118; CHECK-GI-NEXT: mul w0, w8, w9119; CHECK-GI-NEXT: ret120entry:121 %arg1 = call i8 @llvm.vector.reduce.mul.v8i8(<8 x i8> %a)122 ret i8 %arg1123}124 125define i8 @mulv_v16i8(<16 x i8> %a) {126; CHECK-SD-LABEL: mulv_v16i8:127; CHECK-SD: // %bb.0: // %entry128; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8129; CHECK-SD-NEXT: mul v0.8b, v0.8b, v1.8b130; CHECK-SD-NEXT: umov w8, v0.b[1]131; CHECK-SD-NEXT: umov w9, v0.b[0]132; CHECK-SD-NEXT: umov w10, v0.b[2]133; CHECK-SD-NEXT: mul w8, w9, w8134; CHECK-SD-NEXT: umov w9, v0.b[3]135; CHECK-SD-NEXT: mul w8, w8, w10136; CHECK-SD-NEXT: umov w10, v0.b[4]137; CHECK-SD-NEXT: mul w8, w8, w9138; CHECK-SD-NEXT: umov w9, v0.b[5]139; CHECK-SD-NEXT: mul w8, w8, w10140; CHECK-SD-NEXT: umov w10, v0.b[6]141; CHECK-SD-NEXT: mul w8, w8, w9142; CHECK-SD-NEXT: umov w9, v0.b[7]143; CHECK-SD-NEXT: mul w8, w8, w10144; CHECK-SD-NEXT: mul w0, w8, w9145; CHECK-SD-NEXT: ret146;147; CHECK-GI-LABEL: mulv_v16i8:148; CHECK-GI: // %bb.0: // %entry149; CHECK-GI-NEXT: mov d1, v0.d[1]150; CHECK-GI-NEXT: mul v0.8b, v0.8b, v1.8b151; CHECK-GI-NEXT: umov w8, v0.b[0]152; CHECK-GI-NEXT: umov w9, v0.b[1]153; CHECK-GI-NEXT: umov w10, v0.b[2]154; CHECK-GI-NEXT: umov w11, v0.b[3]155; CHECK-GI-NEXT: umov w12, v0.b[4]156; CHECK-GI-NEXT: umov w13, v0.b[5]157; CHECK-GI-NEXT: umov w14, v0.b[6]158; CHECK-GI-NEXT: umov w15, v0.b[7]159; CHECK-GI-NEXT: mul w8, w8, w9160; CHECK-GI-NEXT: mul w9, w10, w11161; CHECK-GI-NEXT: mul w10, w12, w13162; CHECK-GI-NEXT: mul w11, w14, w15163; CHECK-GI-NEXT: mul w8, w8, w9164; CHECK-GI-NEXT: mul w9, w10, w11165; CHECK-GI-NEXT: mul w0, w8, w9166; CHECK-GI-NEXT: ret167entry:168 %arg1 = call i8 @llvm.vector.reduce.mul.v16i8(<16 x i8> %a)169 ret i8 %arg1170}171 172define i8 @mulv_v32i8(<32 x i8> %a) {173; CHECK-SD-LABEL: mulv_v32i8:174; CHECK-SD: // %bb.0: // %entry175; CHECK-SD-NEXT: mul v0.16b, v0.16b, v1.16b176; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8177; CHECK-SD-NEXT: mul v0.8b, v0.8b, v1.8b178; CHECK-SD-NEXT: umov w8, v0.b[1]179; CHECK-SD-NEXT: umov w9, v0.b[0]180; CHECK-SD-NEXT: umov w10, v0.b[2]181; CHECK-SD-NEXT: mul w8, w9, w8182; CHECK-SD-NEXT: umov w9, v0.b[3]183; CHECK-SD-NEXT: mul w8, w8, w10184; CHECK-SD-NEXT: umov w10, v0.b[4]185; CHECK-SD-NEXT: mul w8, w8, w9186; CHECK-SD-NEXT: umov w9, v0.b[5]187; CHECK-SD-NEXT: mul w8, w8, w10188; CHECK-SD-NEXT: umov w10, v0.b[6]189; CHECK-SD-NEXT: mul w8, w8, w9190; CHECK-SD-NEXT: umov w9, v0.b[7]191; CHECK-SD-NEXT: mul w8, w8, w10192; CHECK-SD-NEXT: mul w0, w8, w9193; CHECK-SD-NEXT: ret194;195; CHECK-GI-LABEL: mulv_v32i8:196; CHECK-GI: // %bb.0: // %entry197; CHECK-GI-NEXT: mov d2, v0.d[1]198; CHECK-GI-NEXT: mov d3, v1.d[1]199; CHECK-GI-NEXT: mul v0.8b, v0.8b, v2.8b200; CHECK-GI-NEXT: mul v1.8b, v1.8b, v3.8b201; CHECK-GI-NEXT: mul v0.8b, v0.8b, v1.8b202; CHECK-GI-NEXT: umov w8, v0.b[0]203; CHECK-GI-NEXT: umov w9, v0.b[1]204; CHECK-GI-NEXT: umov w10, v0.b[2]205; CHECK-GI-NEXT: umov w11, v0.b[3]206; CHECK-GI-NEXT: umov w12, v0.b[4]207; CHECK-GI-NEXT: umov w13, v0.b[5]208; CHECK-GI-NEXT: umov w14, v0.b[6]209; CHECK-GI-NEXT: umov w15, v0.b[7]210; CHECK-GI-NEXT: mul w8, w8, w9211; CHECK-GI-NEXT: mul w9, w10, w11212; CHECK-GI-NEXT: mul w10, w12, w13213; CHECK-GI-NEXT: mul w11, w14, w15214; CHECK-GI-NEXT: mul w8, w8, w9215; CHECK-GI-NEXT: mul w9, w10, w11216; CHECK-GI-NEXT: mul w0, w8, w9217; CHECK-GI-NEXT: ret218entry:219 %arg1 = call i8 @llvm.vector.reduce.mul.v32i8(<32 x i8> %a)220 ret i8 %arg1221}222 223define i16 @mulv_v2i16(<2 x i16> %a) {224; CHECK-LABEL: mulv_v2i16:225; CHECK: // %bb.0: // %entry226; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0227; CHECK-NEXT: mov w8, v0.s[1]228; CHECK-NEXT: fmov w9, s0229; CHECK-NEXT: mul w0, w9, w8230; CHECK-NEXT: ret231entry:232 %arg1 = call i16 @llvm.vector.reduce.mul.v2i16(<2 x i16> %a)233 ret i16 %arg1234}235 236define i16 @mulv_v3i16(<3 x i16> %a) {237; CHECK-SD-LABEL: mulv_v3i16:238; CHECK-SD: // %bb.0: // %entry239; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0240; CHECK-SD-NEXT: umov w8, v0.h[1]241; CHECK-SD-NEXT: umov w9, v0.h[0]242; CHECK-SD-NEXT: umov w10, v0.h[2]243; CHECK-SD-NEXT: mul w8, w9, w8244; CHECK-SD-NEXT: mul w0, w8, w10245; CHECK-SD-NEXT: ret246;247; CHECK-GI-LABEL: mulv_v3i16:248; CHECK-GI: // %bb.0: // %entry249; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0250; CHECK-GI-NEXT: umov w8, v0.h[0]251; CHECK-GI-NEXT: umov w9, v0.h[1]252; CHECK-GI-NEXT: umov w10, v0.h[2]253; CHECK-GI-NEXT: mul w8, w8, w9254; CHECK-GI-NEXT: mul w0, w8, w10255; CHECK-GI-NEXT: ret256entry:257 %arg1 = call i16 @llvm.vector.reduce.mul.v3i16(<3 x i16> %a)258 ret i16 %arg1259}260 261define i16 @mulv_v4i16(<4 x i16> %a) {262; CHECK-SD-LABEL: mulv_v4i16:263; CHECK-SD: // %bb.0: // %entry264; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0265; CHECK-SD-NEXT: umov w8, v0.h[1]266; CHECK-SD-NEXT: umov w9, v0.h[0]267; CHECK-SD-NEXT: umov w10, v0.h[2]268; CHECK-SD-NEXT: mul w8, w9, w8269; CHECK-SD-NEXT: umov w9, v0.h[3]270; CHECK-SD-NEXT: mul w8, w8, w10271; CHECK-SD-NEXT: mul w0, w8, w9272; CHECK-SD-NEXT: ret273;274; CHECK-GI-LABEL: mulv_v4i16:275; CHECK-GI: // %bb.0: // %entry276; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0277; CHECK-GI-NEXT: umov w8, v0.h[0]278; CHECK-GI-NEXT: umov w9, v0.h[1]279; CHECK-GI-NEXT: umov w10, v0.h[2]280; CHECK-GI-NEXT: umov w11, v0.h[3]281; CHECK-GI-NEXT: mul w8, w8, w9282; CHECK-GI-NEXT: mul w9, w10, w11283; CHECK-GI-NEXT: mul w0, w8, w9284; CHECK-GI-NEXT: ret285entry:286 %arg1 = call i16 @llvm.vector.reduce.mul.v4i16(<4 x i16> %a)287 ret i16 %arg1288}289 290define i16 @mulv_v8i16(<8 x i16> %a) {291; CHECK-SD-LABEL: mulv_v8i16:292; CHECK-SD: // %bb.0: // %entry293; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8294; CHECK-SD-NEXT: mul v0.4h, v0.4h, v1.4h295; CHECK-SD-NEXT: umov w8, v0.h[1]296; CHECK-SD-NEXT: umov w9, v0.h[0]297; CHECK-SD-NEXT: umov w10, v0.h[2]298; CHECK-SD-NEXT: mul w8, w9, w8299; CHECK-SD-NEXT: umov w9, v0.h[3]300; CHECK-SD-NEXT: mul w8, w8, w10301; CHECK-SD-NEXT: mul w0, w8, w9302; CHECK-SD-NEXT: ret303;304; CHECK-GI-LABEL: mulv_v8i16:305; CHECK-GI: // %bb.0: // %entry306; CHECK-GI-NEXT: mov d1, v0.d[1]307; CHECK-GI-NEXT: mul v0.4h, v0.4h, v1.4h308; CHECK-GI-NEXT: umov w8, v0.h[0]309; CHECK-GI-NEXT: umov w9, v0.h[1]310; CHECK-GI-NEXT: umov w10, v0.h[2]311; CHECK-GI-NEXT: umov w11, v0.h[3]312; CHECK-GI-NEXT: mul w8, w8, w9313; CHECK-GI-NEXT: mul w9, w10, w11314; CHECK-GI-NEXT: mul w0, w8, w9315; CHECK-GI-NEXT: ret316entry:317 %arg1 = call i16 @llvm.vector.reduce.mul.v8i16(<8 x i16> %a)318 ret i16 %arg1319}320 321define i16 @mulv_v16i16(<16 x i16> %a) {322; CHECK-SD-LABEL: mulv_v16i16:323; CHECK-SD: // %bb.0: // %entry324; CHECK-SD-NEXT: mul v0.8h, v0.8h, v1.8h325; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8326; CHECK-SD-NEXT: mul v0.4h, v0.4h, v1.4h327; CHECK-SD-NEXT: umov w8, v0.h[1]328; CHECK-SD-NEXT: umov w9, v0.h[0]329; CHECK-SD-NEXT: umov w10, v0.h[2]330; CHECK-SD-NEXT: mul w8, w9, w8331; CHECK-SD-NEXT: umov w9, v0.h[3]332; CHECK-SD-NEXT: mul w8, w8, w10333; CHECK-SD-NEXT: mul w0, w8, w9334; CHECK-SD-NEXT: ret335;336; CHECK-GI-LABEL: mulv_v16i16:337; CHECK-GI: // %bb.0: // %entry338; CHECK-GI-NEXT: mov d2, v0.d[1]339; CHECK-GI-NEXT: mov d3, v1.d[1]340; CHECK-GI-NEXT: mul v0.4h, v0.4h, v2.4h341; CHECK-GI-NEXT: mul v1.4h, v1.4h, v3.4h342; CHECK-GI-NEXT: mul v0.4h, v0.4h, v1.4h343; CHECK-GI-NEXT: umov w8, v0.h[0]344; CHECK-GI-NEXT: umov w9, v0.h[1]345; CHECK-GI-NEXT: umov w10, v0.h[2]346; CHECK-GI-NEXT: umov w11, v0.h[3]347; CHECK-GI-NEXT: mul w8, w8, w9348; CHECK-GI-NEXT: mul w9, w10, w11349; CHECK-GI-NEXT: mul w0, w8, w9350; CHECK-GI-NEXT: ret351entry:352 %arg1 = call i16 @llvm.vector.reduce.mul.v16i16(<16 x i16> %a)353 ret i16 %arg1354}355 356define i32 @mulv_v2i32(<2 x i32> %a) {357; CHECK-LABEL: mulv_v2i32:358; CHECK: // %bb.0: // %entry359; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0360; CHECK-NEXT: mov w8, v0.s[1]361; CHECK-NEXT: fmov w9, s0362; CHECK-NEXT: mul w0, w9, w8363; CHECK-NEXT: ret364entry:365 %arg1 = call i32 @llvm.vector.reduce.mul.v2i32(<2 x i32> %a)366 ret i32 %arg1367}368 369define i32 @mulv_v3i32(<3 x i32> %a) {370; CHECK-LABEL: mulv_v3i32:371; CHECK: // %bb.0: // %entry372; CHECK-NEXT: mov v1.16b, v0.16b373; CHECK-NEXT: mov w8, #1 // =0x1374; CHECK-NEXT: mov v1.s[3], w8375; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #8376; CHECK-NEXT: mul v0.2s, v0.2s, v1.2s377; CHECK-NEXT: mov w8, v0.s[1]378; CHECK-NEXT: fmov w9, s0379; CHECK-NEXT: mul w0, w9, w8380; CHECK-NEXT: ret381entry:382 %arg1 = call i32 @llvm.vector.reduce.mul.v3i32(<3 x i32> %a)383 ret i32 %arg1384}385 386define i32 @mulv_v4i32(<4 x i32> %a) {387; CHECK-SD-LABEL: mulv_v4i32:388; CHECK-SD: // %bb.0: // %entry389; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8390; CHECK-SD-NEXT: mul v0.2s, v0.2s, v1.2s391; CHECK-SD-NEXT: mov w8, v0.s[1]392; CHECK-SD-NEXT: fmov w9, s0393; CHECK-SD-NEXT: mul w0, w9, w8394; CHECK-SD-NEXT: ret395;396; CHECK-GI-LABEL: mulv_v4i32:397; CHECK-GI: // %bb.0: // %entry398; CHECK-GI-NEXT: mov d1, v0.d[1]399; CHECK-GI-NEXT: mul v0.2s, v0.2s, v1.2s400; CHECK-GI-NEXT: mov w8, v0.s[1]401; CHECK-GI-NEXT: fmov w9, s0402; CHECK-GI-NEXT: mul w0, w9, w8403; CHECK-GI-NEXT: ret404entry:405 %arg1 = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> %a)406 ret i32 %arg1407}408 409define i32 @mulv_v8i32(<8 x i32> %a) {410; CHECK-SD-LABEL: mulv_v8i32:411; CHECK-SD: // %bb.0: // %entry412; CHECK-SD-NEXT: mul v0.4s, v0.4s, v1.4s413; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8414; CHECK-SD-NEXT: mul v0.2s, v0.2s, v1.2s415; CHECK-SD-NEXT: mov w8, v0.s[1]416; CHECK-SD-NEXT: fmov w9, s0417; CHECK-SD-NEXT: mul w0, w9, w8418; CHECK-SD-NEXT: ret419;420; CHECK-GI-LABEL: mulv_v8i32:421; CHECK-GI: // %bb.0: // %entry422; CHECK-GI-NEXT: mov d2, v0.d[1]423; CHECK-GI-NEXT: mov d3, v1.d[1]424; CHECK-GI-NEXT: mul v0.2s, v0.2s, v2.2s425; CHECK-GI-NEXT: mul v1.2s, v1.2s, v3.2s426; CHECK-GI-NEXT: mul v0.2s, v0.2s, v1.2s427; CHECK-GI-NEXT: mov w8, v0.s[1]428; CHECK-GI-NEXT: fmov w9, s0429; CHECK-GI-NEXT: mul w0, w9, w8430; CHECK-GI-NEXT: ret431entry:432 %arg1 = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> %a)433 ret i32 %arg1434}435 436define i64 @mulv_v2i64(<2 x i64> %a) {437; CHECK-LABEL: mulv_v2i64:438; CHECK: // %bb.0: // %entry439; CHECK-NEXT: mov x8, v0.d[1]440; CHECK-NEXT: fmov x9, d0441; CHECK-NEXT: mul x0, x9, x8442; CHECK-NEXT: ret443entry:444 %arg1 = call i64 @llvm.vector.reduce.mul.v2i64(<2 x i64> %a)445 ret i64 %arg1446}447 448define i64 @mulv_v3i64(<3 x i64> %a) {449; CHECK-SD-LABEL: mulv_v3i64:450; CHECK-SD: // %bb.0: // %entry451; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2452; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0453; CHECK-SD-NEXT: fmov x8, d2454; CHECK-SD-NEXT: fmov x9, d0455; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1456; CHECK-SD-NEXT: mul x8, x9, x8457; CHECK-SD-NEXT: fmov x9, d1458; CHECK-SD-NEXT: mul x0, x9, x8459; CHECK-SD-NEXT: ret460;461; CHECK-GI-LABEL: mulv_v3i64:462; CHECK-GI: // %bb.0: // %entry463; CHECK-GI-NEXT: fmov x8, d0464; CHECK-GI-NEXT: fmov x9, d1465; CHECK-GI-NEXT: mul x8, x8, x9466; CHECK-GI-NEXT: fmov x9, d2467; CHECK-GI-NEXT: mul x0, x8, x9468; CHECK-GI-NEXT: ret469entry:470 %arg1 = call i64 @llvm.vector.reduce.mul.v3i64(<3 x i64> %a)471 ret i64 %arg1472}473 474define i64 @mulv_v4i64(<4 x i64> %a) {475; CHECK-SD-LABEL: mulv_v4i64:476; CHECK-SD: // %bb.0: // %entry477; CHECK-SD-NEXT: mov x8, v1.d[1]478; CHECK-SD-NEXT: mov x9, v0.d[1]479; CHECK-SD-NEXT: fmov x10, d0480; CHECK-SD-NEXT: mul x8, x9, x8481; CHECK-SD-NEXT: fmov x9, d1482; CHECK-SD-NEXT: mul x9, x10, x9483; CHECK-SD-NEXT: mul x0, x9, x8484; CHECK-SD-NEXT: ret485;486; CHECK-GI-LABEL: mulv_v4i64:487; CHECK-GI: // %bb.0: // %entry488; CHECK-GI-NEXT: mov x8, v0.d[1]489; CHECK-GI-NEXT: fmov x10, d0490; CHECK-GI-NEXT: mov x9, v1.d[1]491; CHECK-GI-NEXT: mul x8, x10, x8492; CHECK-GI-NEXT: fmov x10, d1493; CHECK-GI-NEXT: mul x9, x10, x9494; CHECK-GI-NEXT: mul x0, x8, x9495; CHECK-GI-NEXT: ret496entry:497 %arg1 = call i64 @llvm.vector.reduce.mul.v4i64(<4 x i64> %a)498 ret i64 %arg1499}500 501define i128 @mulv_v2i128(<2 x i128> %a) {502; CHECK-SD-LABEL: mulv_v2i128:503; CHECK-SD: // %bb.0: // %entry504; CHECK-SD-NEXT: umulh x8, x0, x2505; CHECK-SD-NEXT: madd x8, x0, x3, x8506; CHECK-SD-NEXT: mul x0, x0, x2507; CHECK-SD-NEXT: madd x1, x1, x2, x8508; CHECK-SD-NEXT: ret509;510; CHECK-GI-LABEL: mulv_v2i128:511; CHECK-GI: // %bb.0: // %entry512; CHECK-GI-NEXT: mul x9, x0, x3513; CHECK-GI-NEXT: mul x8, x0, x2514; CHECK-GI-NEXT: umulh x10, x0, x2515; CHECK-GI-NEXT: madd x9, x1, x2, x9516; CHECK-GI-NEXT: mov x0, x8517; CHECK-GI-NEXT: add x1, x9, x10518; CHECK-GI-NEXT: ret519entry:520 %arg1 = call i128 @llvm.vector.reduce.mul.v2i128(<2 x i128> %a)521 ret i128 %arg1522}523