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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=arm64-apple-ios -o - %s | FileCheck %s3 4declare i32 @llvm.aarch64.neon.uaddlv.i32.v8i8(<8 x i8>) #05declare i32 @llvm.aarch64.neon.uaddlv.i32.v16i8(<16 x i8>) #06declare i32 @llvm.aarch64.neon.uaddlv.i32.v4i16(<4 x i16>) #07declare i32 @llvm.aarch64.neon.uaddlv.i32.v8i16(<8 x i16>) #08declare i64 @llvm.aarch64.neon.uaddlv.i64.v4i32(<4 x i32>) #09 10define void @insert_vec_v2i32_uaddlv_from_v8i16(ptr %0) {11; CHECK-LABEL: insert_vec_v2i32_uaddlv_from_v8i16:12; CHECK: ; %bb.0: ; %entry13; CHECK-NEXT: movi.2d v0, #000000000000000014; CHECK-NEXT: movi.2d v1, #000000000000000015; CHECK-NEXT: uaddlv.8h s0, v016; CHECK-NEXT: mov.s v1[0], v0[0]17; CHECK-NEXT: ucvtf.2s v0, v118; CHECK-NEXT: str d0, [x0]19; CHECK-NEXT: ret20 21entry:22 %vaddlv = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v8i16(<8 x i16> zeroinitializer)23 %1 = insertelement <2 x i32> zeroinitializer, i32 %vaddlv, i64 024 %2 = uitofp <2 x i32> %1 to <2 x float>25 store <2 x float> %2, ptr %0, align 826 ret void27}28 29define void @insert_vec_v4i32_uaddlv_from_v8i16(ptr %0) {30; CHECK-LABEL: insert_vec_v4i32_uaddlv_from_v8i16:31; CHECK: ; %bb.0: ; %entry32; CHECK-NEXT: movi.2d v0, #000000000000000033; CHECK-NEXT: uaddlv.8h s1, v034; CHECK-NEXT: mov.s v0[0], v1[0]35; CHECK-NEXT: ucvtf.4s v0, v036; CHECK-NEXT: str q0, [x0]37; CHECK-NEXT: ret38 39entry:40 %vaddlv = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v8i16(<8 x i16> zeroinitializer)41 %1 = insertelement <4 x i32> zeroinitializer, i32 %vaddlv, i64 042 %2 = uitofp <4 x i32> %1 to <4 x float>43 store <4 x float> %2, ptr %0, align 844 ret void45}46 47define void @insert_vec_v16i32_uaddlv_from_v8i16(ptr %0) {48; CHECK-LABEL: insert_vec_v16i32_uaddlv_from_v8i16:49; CHECK: ; %bb.0: ; %entry50; CHECK-NEXT: movi.2d v0, #000000000000000051; CHECK-NEXT: movi.2d v2, #000000000000000052; CHECK-NEXT: uaddlv.8h s1, v053; CHECK-NEXT: stp q0, q0, [x0, #32]54; CHECK-NEXT: mov.s v2[0], v1[0]55; CHECK-NEXT: ucvtf.4s v1, v256; CHECK-NEXT: stp q1, q0, [x0]57; CHECK-NEXT: ret58 59entry:60 %vaddlv = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v8i16(<8 x i16> zeroinitializer)61 %1 = insertelement <16 x i32> zeroinitializer, i32 %vaddlv, i64 062 %2 = uitofp <16 x i32> %1 to <16 x float>63 store <16 x float> %2, ptr %0, align 864 ret void65}66 67define void @insert_vec_v23i32_uaddlv_from_v8i16(ptr %0) {68; CHECK-LABEL: insert_vec_v23i32_uaddlv_from_v8i16:69; CHECK: ; %bb.0: ; %entry70; CHECK-NEXT: movi.2d v0, #000000000000000071; CHECK-NEXT: movi.2d v2, #000000000000000072; CHECK-NEXT: str wzr, [x0, #88]73; CHECK-NEXT: str xzr, [x0, #80]74; CHECK-NEXT: uaddlv.8h s1, v075; CHECK-NEXT: stp q0, q0, [x0, #16]76; CHECK-NEXT: stp q0, q0, [x0, #48]77; CHECK-NEXT: mov.s v2[0], v1[0]78; CHECK-NEXT: ucvtf.4s v1, v279; CHECK-NEXT: str q1, [x0]80; CHECK-NEXT: ret81 82entry:83 %vaddlv = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v8i16(<8 x i16> zeroinitializer)84 %1 = insertelement <23 x i32> zeroinitializer, i32 %vaddlv, i64 085 %2 = uitofp <23 x i32> %1 to <23 x float>86 store <23 x float> %2, ptr %0, align 887 ret void88}89 90define void @insert_vec_v2i32_uaddlv_from_v16i8(ptr %0) {91; CHECK-LABEL: insert_vec_v2i32_uaddlv_from_v16i8:92; CHECK: ; %bb.0: ; %entry93; CHECK-NEXT: movi.2d v0, #000000000000000094; CHECK-NEXT: movi.2d v1, #000000000000000095; CHECK-NEXT: uaddlv.16b h0, v096; CHECK-NEXT: mov.s v1[0], v0[0]97; CHECK-NEXT: ucvtf.2s v0, v198; CHECK-NEXT: str d0, [x0]99; CHECK-NEXT: ret100 101entry:102 %vaddlv = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v16i8(<16 x i8> zeroinitializer)103 %1 = insertelement <2 x i32> zeroinitializer, i32 %vaddlv, i64 0104 %2 = uitofp <2 x i32> %1 to <2 x float>105 store <2 x float> %2, ptr %0, align 8106 ret void107}108 109define void @insert_vec_v2i32_uaddlv_from_v8i8(ptr %0) {110; CHECK-LABEL: insert_vec_v2i32_uaddlv_from_v8i8:111; CHECK: ; %bb.0: ; %entry112; CHECK-NEXT: movi.2d v0, #0000000000000000113; CHECK-NEXT: uaddlv.8b h1, v0114; CHECK-NEXT: mov.s v0[0], v1[0]115; CHECK-NEXT: ucvtf.2s v0, v0116; CHECK-NEXT: str d0, [x0]117; CHECK-NEXT: ret118 119entry:120 %vaddlv = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v8i8(<8 x i8> zeroinitializer)121 %1 = insertelement <2 x i32> zeroinitializer, i32 %vaddlv, i64 0122 %2 = uitofp <2 x i32> %1 to <2 x float>123 store <2 x float> %2, ptr %0, align 8124 ret void125}126 127define void @insert_vec_v2i32_uaddlv_from_v4i16(ptr %0) {128; CHECK-LABEL: insert_vec_v2i32_uaddlv_from_v4i16:129; CHECK: ; %bb.0: ; %entry130; CHECK-NEXT: movi.2d v0, #0000000000000000131; CHECK-NEXT: uaddlv.4h s1, v0132; CHECK-NEXT: mov.s v0[0], v1[0]133; CHECK-NEXT: ucvtf.2s v0, v0134; CHECK-NEXT: str d0, [x0]135; CHECK-NEXT: ret136 137entry:138 %vaddlv = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v4i16(<4 x i16> zeroinitializer)139 %1 = insertelement <2 x i32> zeroinitializer, i32 %vaddlv, i64 0140 %2 = uitofp <2 x i32> %1 to <2 x float>141 store <2 x float> %2, ptr %0, align 8142 ret void143}144 145define void @insert_vec_v6i64_uaddlv_from_v4i32(ptr %0) {146; CHECK-LABEL: insert_vec_v6i64_uaddlv_from_v4i32:147; CHECK: ; %bb.0: ; %entry148; CHECK-NEXT: movi.2d v0, #0000000000000000149; CHECK-NEXT: str xzr, [x0, #16]150; CHECK-NEXT: uaddlv.4s d1, v0151; CHECK-NEXT: fmov x8, d1152; CHECK-NEXT: ucvtf s1, x8153; CHECK-NEXT: mov.s v0[0], v1[0]154; CHECK-NEXT: str q0, [x0]155; CHECK-NEXT: ret156 157entry:158 %vaddlv = tail call i64 @llvm.aarch64.neon.uaddlv.i64.v4i32(<4 x i32> zeroinitializer)159 %1 = insertelement <6 x i64> zeroinitializer, i64 %vaddlv, i64 0160 %2 = uitofp <6 x i64> %1 to <6 x float>161 store <6 x float> %2, ptr %0, align 8162 ret void163}164 165define void @insert_vec_v2i64_uaddlv_from_v4i32(ptr %0) {166; CHECK-LABEL: insert_vec_v2i64_uaddlv_from_v4i32:167; CHECK: ; %bb.0: ; %entry168; CHECK-NEXT: movi.2d v0, #0000000000000000169; CHECK-NEXT: uaddlv.4s d0, v0170; CHECK-NEXT: fmov x8, d0171; CHECK-NEXT: movi d0, #0000000000000000172; CHECK-NEXT: ucvtf s1, x8173; CHECK-NEXT: mov.s v0[0], v1[0]174; CHECK-NEXT: str d0, [x0]175; CHECK-NEXT: ret176 177entry:178 %vaddlv = tail call i64 @llvm.aarch64.neon.uaddlv.i64.v4i32(<4 x i32> zeroinitializer)179 %1 = insertelement <2 x i64> zeroinitializer, i64 %vaddlv, i64 0180 %2 = uitofp <2 x i64> %1 to <2 x float>181 store <2 x float> %2, ptr %0, align 8182 ret void183}184 185define void @insert_vec_v5i64_uaddlv_from_v4i32(ptr %0) {186; CHECK-LABEL: insert_vec_v5i64_uaddlv_from_v4i32:187; CHECK: ; %bb.0: ; %entry188; CHECK-NEXT: movi.2d v0, #0000000000000000189; CHECK-NEXT: str wzr, [x0, #16]190; CHECK-NEXT: uaddlv.4s d1, v0191; CHECK-NEXT: fmov x8, d1192; CHECK-NEXT: ucvtf s1, x8193; CHECK-NEXT: mov.s v0[0], v1[0]194; CHECK-NEXT: str q0, [x0]195; CHECK-NEXT: ret196 197entry:198 %vaddlv = tail call i64 @llvm.aarch64.neon.uaddlv.i64.v4i32(<4 x i32> zeroinitializer)199 %1 = insertelement <5 x i64> zeroinitializer, i64 %vaddlv, i64 0200 %2 = uitofp <5 x i64> %1 to <5 x float>201 store <5 x float> %2, ptr %0, align 8202 ret void203}204 205define void @insert_vec_v8i16_uaddlv_from_v8i16(ptr %0) {206; CHECK-LABEL: insert_vec_v8i16_uaddlv_from_v8i16:207; CHECK: ; %bb.0: ; %entry208; CHECK-NEXT: movi.2d v0, #0000000000000000209; CHECK-NEXT: movi.2d v1, #0000000000000000210; CHECK-NEXT: stp xzr, xzr, [x0, #16]211; CHECK-NEXT: uaddlv.8h s0, v0212; CHECK-NEXT: mov.h v1[0], v0[0]213; CHECK-NEXT: ushll.4s v1, v1, #0214; CHECK-NEXT: ucvtf.4s v1, v1215; CHECK-NEXT: str q1, [x0]216; CHECK-NEXT: ret217 218entry:219 %vaddlv = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v8i16(<8 x i16> zeroinitializer)220 %1 = trunc i32 %vaddlv to i16221 %2 = insertelement <8 x i16> zeroinitializer, i16 %1, i64 0222 %3 = uitofp <8 x i16> %2 to <8 x float>223 store <8 x float> %3, ptr %0, align 8224 ret void225}226 227define void @insert_vec_v3i16_uaddlv_from_v8i16(ptr %0) {228; CHECK-LABEL: insert_vec_v3i16_uaddlv_from_v8i16:229; CHECK: ; %bb.0: ; %entry230; CHECK-NEXT: movi.2d v0, #0000000000000000231; CHECK-NEXT: movi.2d v1, #0000000000000000232; CHECK-NEXT: add x8, x0, #8233; CHECK-NEXT: uaddlv.8h s0, v0234; CHECK-NEXT: mov.h v1[0], v0[0]235; CHECK-NEXT: ushll.4s v1, v1, #0236; CHECK-NEXT: ucvtf.4s v1, v1237; CHECK-NEXT: st1.s { v1 }[2], [x8]238; CHECK-NEXT: str d1, [x0]239; CHECK-NEXT: ret240 241entry:242 %vaddlv = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v8i16(<8 x i16> zeroinitializer)243 %1 = trunc i32 %vaddlv to i16244 %2 = insertelement <3 x i16> zeroinitializer, i16 %1, i64 0245 %3 = uitofp <3 x i16> %2 to <3 x float>246 store <3 x float> %3, ptr %0, align 8247 ret void248}249 250define void @insert_vec_v16i64_uaddlv_from_v4i16(ptr %0) {251; CHECK-LABEL: insert_vec_v16i64_uaddlv_from_v4i16:252; CHECK: ; %bb.0: ; %entry253; CHECK-NEXT: movi.2d v0, #0000000000000000254; CHECK-NEXT: movi.2d v2, #0000000000000000255; CHECK-NEXT: uaddlv.4h s1, v0256; CHECK-NEXT: stp q0, q0, [x0, #32]257; CHECK-NEXT: mov.s v2[0], v1[0]258; CHECK-NEXT: fmov x8, d2259; CHECK-NEXT: mov.d x9, v2[1]260; CHECK-NEXT: movi.2d v2, #0000000000000000261; CHECK-NEXT: ucvtf s1, x8262; CHECK-NEXT: ucvtf s3, x9263; CHECK-NEXT: mov.s v2[0], v1[0]264; CHECK-NEXT: mov.s v2[1], v3[0]265; CHECK-NEXT: stp q2, q0, [x0]266; CHECK-NEXT: ret267 268entry:269 %vaddlv = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v4i16(<4 x i16> zeroinitializer)270 %1 = zext i32 %vaddlv to i64271 %2 = insertelement <16 x i64> zeroinitializer, i64 %1, i64 0272 %3 = uitofp <16 x i64> %2 to <16 x float>273 store <16 x float> %3, ptr %0, align 8274 ret void275}276 277define void @insert_vec_v16i8_uaddlv_from_v8i8(ptr %0) {278; CHECK-LABEL: insert_vec_v16i8_uaddlv_from_v8i8:279; CHECK: ; %bb.0: ; %entry280; CHECK-NEXT: movi.2d v0, #0000000000000000281; CHECK-NEXT: movi.2d v2, #0000000000000000282; CHECK-NEXT: uaddlv.8b h1, v0283; CHECK-NEXT: stp q0, q0, [x0, #32]284; CHECK-NEXT: mov.h v2[0], v1[0]285; CHECK-NEXT: bic.4h v2, #255, lsl #8286; CHECK-NEXT: ushll.4s v2, v2, #0287; CHECK-NEXT: ucvtf.4s v2, v2288; CHECK-NEXT: stp q2, q0, [x0]289; CHECK-NEXT: ret290 291entry:292 %vaddlv = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v8i8(<8 x i8> zeroinitializer)293 %1 = trunc i32 %vaddlv to i8294 %2 = insertelement <16 x i8> zeroinitializer, i8 %1, i64 0295 %3 = uitofp <16 x i8> %2 to <16 x float>296 store <16 x float> %3, ptr %0, align 8297 ret void298}299 300define void @insert_vec_v8i8_uaddlv_from_v8i8(ptr %0) {301; CHECK-LABEL: insert_vec_v8i8_uaddlv_from_v8i8:302; CHECK: ; %bb.0: ; %entry303; CHECK-NEXT: movi.2d v0, #0000000000000000304; CHECK-NEXT: stp xzr, xzr, [x0, #16]305; CHECK-NEXT: uaddlv.8b h1, v0306; CHECK-NEXT: mov.h v0[0], v1[0]307; CHECK-NEXT: bic.4h v0, #7, lsl #8308; CHECK-NEXT: ushll.4s v0, v0, #0309; CHECK-NEXT: ucvtf.4s v0, v0310; CHECK-NEXT: str q0, [x0]311; CHECK-NEXT: ret312 313entry:314 %vaddlv = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v8i8(<8 x i8> zeroinitializer)315 %1 = trunc i32 %vaddlv to i8316 %2 = insertelement <8 x i8> zeroinitializer, i8 %1, i64 0317 %3 = uitofp <8 x i8> %2 to <8 x float>318 store <8 x float> %3, ptr %0, align 8319 ret void320}321 322define void @insert_vec_v12i16_uaddlv_from_v4i16(ptr %0) {323; CHECK-LABEL: insert_vec_v12i16_uaddlv_from_v4i16:324; CHECK: ; %bb.0: ; %entry325; CHECK-NEXT: movi.2d v0, #0000000000000000326; CHECK-NEXT: stp xzr, xzr, [x0, #16]327; CHECK-NEXT: stp xzr, xzr, [x0, #32]328; CHECK-NEXT: uaddlv.4h s1, v0329; CHECK-NEXT: mov.h v0[0], v1[0]330; CHECK-NEXT: ushll.4s v0, v0, #0331; CHECK-NEXT: ucvtf.4s v0, v0332; CHECK-NEXT: str q0, [x0]333; CHECK-NEXT: ret334 335entry:336 %vaddlv = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v4i16(<4 x i16> zeroinitializer)337 %1 = trunc i32 %vaddlv to i16338 %2 = insertelement <12 x i16> zeroinitializer, i16 %1, i64 0339 %3 = uitofp <12 x i16> %2 to <12 x float>340 store <12 x float> %3, ptr %0, align 8341 ret void342}343 344define void @insert_vec_v8i32_uaddlv_from_v4i32(ptr %0) {345; CHECK-LABEL: insert_vec_v8i32_uaddlv_from_v4i32:346; CHECK: ; %bb.0: ; %entry347; CHECK-NEXT: movi.2d v0, #0000000000000000348; CHECK-NEXT: stp xzr, xzr, [x0, #16]349; CHECK-NEXT: uaddlv.4s d1, v0350; CHECK-NEXT: mov.s v0[0], v1[0]351; CHECK-NEXT: ucvtf.4s v0, v0352; CHECK-NEXT: str q0, [x0]353; CHECK-NEXT: ret354 355entry:356 %vaddlv = tail call i64 @llvm.aarch64.neon.uaddlv.i64.v4i32(<4 x i32> zeroinitializer)357 %1 = trunc i64 %vaddlv to i32358 %2 = insertelement <8 x i32> zeroinitializer, i32 %1, i64 0359 %3 = uitofp <8 x i32> %2 to <8 x float>360 store <8 x float> %3, ptr %0, align 8361 ret void362}363 364define void @insert_vec_v16i32_uaddlv_from_v4i32(ptr %0) {365; CHECK-LABEL: insert_vec_v16i32_uaddlv_from_v4i32:366; CHECK: ; %bb.0: ; %entry367; CHECK-NEXT: movi.2d v0, #0000000000000000368; CHECK-NEXT: movi.2d v2, #0000000000000000369; CHECK-NEXT: uaddlv.4s d1, v0370; CHECK-NEXT: stp q0, q0, [x0, #32]371; CHECK-NEXT: mov.s v2[0], v1[0]372; CHECK-NEXT: ucvtf.4s v1, v2373; CHECK-NEXT: stp q1, q0, [x0]374; CHECK-NEXT: ret375 376entry:377 %vaddlv = tail call i64 @llvm.aarch64.neon.uaddlv.i64.v4i32(<4 x i32> zeroinitializer)378 %1 = trunc i64 %vaddlv to i32379 %2 = insertelement <16 x i32> zeroinitializer, i32 %1, i64 0380 %3 = uitofp <16 x i32> %2 to <16 x float>381 store <16 x float> %3, ptr %0, align 8382 ret void383}384 385define void @insert_vec_v4i16_uaddlv_from_v4i32(ptr %0) {386; CHECK-LABEL: insert_vec_v4i16_uaddlv_from_v4i32:387; CHECK: ; %bb.0: ; %entry388; CHECK-NEXT: movi.2d v0, #0000000000000000389; CHECK-NEXT: movi.2d v1, #0000000000000000390; CHECK-NEXT: uaddlv.4s d0, v0391; CHECK-NEXT: mov.h v1[0], v0[0]392; CHECK-NEXT: ushll.4s v1, v1, #0393; CHECK-NEXT: ucvtf.4s v1, v1394; CHECK-NEXT: str q1, [x0]395; CHECK-NEXT: ret396 397entry:398 %vaddlv = tail call i64 @llvm.aarch64.neon.uaddlv.i64.v4i32(<4 x i32> zeroinitializer)399 %1 = trunc i64 %vaddlv to i16400 %2 = insertelement <4 x i16> zeroinitializer, i16 %1, i64 0401 %3 = uitofp <4 x i16> %2 to <4 x float>402 store <4 x float> %3, ptr %0, align 8403 ret void404}405 406define void @insert_vec_v16i16_uaddlv_from_v4i32(ptr %0) {407; CHECK-LABEL: insert_vec_v16i16_uaddlv_from_v4i32:408; CHECK: ; %bb.0: ; %entry409; CHECK-NEXT: movi.2d v0, #0000000000000000410; CHECK-NEXT: movi.2d v1, #0000000000000000411; CHECK-NEXT: movi.2d v2, #0000000000000000412; CHECK-NEXT: uaddlv.4s d0, v0413; CHECK-NEXT: stp q2, q2, [x0, #32]414; CHECK-NEXT: mov.h v1[0], v0[0]415; CHECK-NEXT: ushll.4s v1, v1, #0416; CHECK-NEXT: ucvtf.4s v1, v1417; CHECK-NEXT: stp q1, q2, [x0]418; CHECK-NEXT: ret419 420entry:421 %vaddlv = tail call i64 @llvm.aarch64.neon.uaddlv.i64.v4i32(<4 x i32> zeroinitializer)422 %1 = trunc i64 %vaddlv to i16423 %2 = insertelement <16 x i16> zeroinitializer, i16 %1, i64 0424 %3 = uitofp <16 x i16> %2 to <16 x float>425 store <16 x float> %3, ptr %0, align 8426 ret void427}428 429define void @insert_vec_v8i8_uaddlv_from_v4i32(ptr %0) {430; CHECK-LABEL: insert_vec_v8i8_uaddlv_from_v4i32:431; CHECK: ; %bb.0: ; %entry432; CHECK-NEXT: movi.2d v0, #0000000000000000433; CHECK-NEXT: movi.2d v1, #0000000000000000434; CHECK-NEXT: stp xzr, xzr, [x0, #16]435; CHECK-NEXT: uaddlv.4s d0, v0436; CHECK-NEXT: mov.h v1[0], v0[0]437; CHECK-NEXT: bic.4h v1, #255, lsl #8438; CHECK-NEXT: ushll.4s v1, v1, #0439; CHECK-NEXT: ucvtf.4s v1, v1440; CHECK-NEXT: str q1, [x0]441; CHECK-NEXT: ret442 443entry:444 %vaddlv = tail call i64 @llvm.aarch64.neon.uaddlv.i64.v4i32(<4 x i32> zeroinitializer)445 %1 = trunc i64 %vaddlv to i8446 %2 = insertelement <8 x i8> zeroinitializer, i8 %1, i64 0447 %3 = uitofp <8 x i8> %2 to <8 x float>448 store <8 x float> %3, ptr %0, align 8449 ret void450}451 452define void @insert_vec_v16i8_uaddlv_from_v4i32(ptr %0) {453; CHECK-LABEL: insert_vec_v16i8_uaddlv_from_v4i32:454; CHECK: ; %bb.0: ; %entry455; CHECK-NEXT: movi.2d v0, #0000000000000000456; CHECK-NEXT: movi.2d v1, #0000000000000000457; CHECK-NEXT: movi.2d v2, #0000000000000000458; CHECK-NEXT: uaddlv.4s d0, v0459; CHECK-NEXT: stp q2, q2, [x0, #32]460; CHECK-NEXT: mov.h v1[0], v0[0]461; CHECK-NEXT: bic.4h v1, #255, lsl #8462; CHECK-NEXT: ushll.4s v1, v1, #0463; CHECK-NEXT: ucvtf.4s v1, v1464; CHECK-NEXT: stp q1, q2, [x0]465; CHECK-NEXT: ret466 467entry:468 %vaddlv = tail call i64 @llvm.aarch64.neon.uaddlv.i64.v4i32(<4 x i32> zeroinitializer)469 %1 = trunc i64 %vaddlv to i8470 %2 = insertelement <16 x i8> zeroinitializer, i8 %1, i64 0471 %3 = uitofp <16 x i8> %2 to <16 x float>472 store <16 x float> %3, ptr %0, align 8473 ret void474}475 476define void @insert_vec_v2i32_uaddlv_from_v8i16_nz_index(ptr %0) {477; CHECK-LABEL: insert_vec_v2i32_uaddlv_from_v8i16_nz_index:478; CHECK: ; %bb.0: ; %entry479; CHECK-NEXT: movi.2d v0, #0000000000000000480; CHECK-NEXT: uaddlv.8h s1, v0481; CHECK-NEXT: mov.s v0[2], v1[0]482; CHECK-NEXT: ucvtf.4s v0, v0483; CHECK-NEXT: str q0, [x0]484; CHECK-NEXT: ret485 486entry:487 %vaddlv = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v8i16(<8 x i16> zeroinitializer)488 %1 = insertelement <4 x i32> zeroinitializer, i32 %vaddlv, i64 2489 %2 = uitofp <4 x i32> %1 to <4 x float>490 store <4 x float> %2, ptr %0, align 8491 ret void492}493 494define void @store_saddlv_v8i8(ptr %H, <8 x i8> %sum_h, i32 %idx) {495; CHECK-LABEL: store_saddlv_v8i8:496; CHECK: ; %bb.0: ; %entry497; CHECK-NEXT: saddlv.8b h0, v0498; CHECK-NEXT: ; kill: def $w1 killed $w1 def $x1499; CHECK-NEXT: sbfiz x8, x1, #3, #32500; CHECK-NEXT: str s0, [x0, x8]501; CHECK-NEXT: ret502entry:503 %vaddlvq_s32.i = tail call i32 @llvm.aarch64.neon.saddlv.i32.v8i8(<8 x i8> %sum_h)504 %idxprom = sext i32 %idx to i64505 %arrayidx = getelementptr inbounds i64, ptr %H, i64 %idxprom506 store i32 %vaddlvq_s32.i, ptr %arrayidx, align 8507 ret void508}509 510define void @store_saddlv_v16i8(ptr %H, <16 x i8> %sum_h, i32 %idx) {511; CHECK-LABEL: store_saddlv_v16i8:512; CHECK: ; %bb.0: ; %entry513; CHECK-NEXT: saddlv.16b h0, v0514; CHECK-NEXT: ; kill: def $w1 killed $w1 def $x1515; CHECK-NEXT: sbfiz x8, x1, #3, #32516; CHECK-NEXT: str s0, [x0, x8]517; CHECK-NEXT: ret518entry:519 %vaddlvq_s32.i = tail call i32 @llvm.aarch64.neon.saddlv.i32.v16i8(<16 x i8> %sum_h)520 %idxprom = sext i32 %idx to i64521 %arrayidx = getelementptr inbounds i64, ptr %H, i64 %idxprom522 store i32 %vaddlvq_s32.i, ptr %arrayidx, align 8523 ret void524}525 526define void @store_saddlv_v4i16(ptr %H, <4 x i16> %sum_h, i32 %idx) {527; CHECK-LABEL: store_saddlv_v4i16:528; CHECK: ; %bb.0: ; %entry529; CHECK-NEXT: saddlv.4h s0, v0530; CHECK-NEXT: ; kill: def $w1 killed $w1 def $x1531; CHECK-NEXT: sbfiz x8, x1, #3, #32532; CHECK-NEXT: str s0, [x0, x8]533; CHECK-NEXT: ret534entry:535 %vaddlvq_s32.i = tail call i32 @llvm.aarch64.neon.saddlv.i32.v4i16(<4 x i16> %sum_h)536 %idxprom = sext i32 %idx to i64537 %arrayidx = getelementptr inbounds i64, ptr %H, i64 %idxprom538 store i32 %vaddlvq_s32.i, ptr %arrayidx, align 8539 ret void540}541 542define void @store_saddlv_v8i16(ptr %H, <8 x i16> %sum_h, i32 %idx) {543; CHECK-LABEL: store_saddlv_v8i16:544; CHECK: ; %bb.0: ; %entry545; CHECK-NEXT: saddlv.8h s0, v0546; CHECK-NEXT: ; kill: def $w1 killed $w1 def $x1547; CHECK-NEXT: sbfiz x8, x1, #3, #32548; CHECK-NEXT: str s0, [x0, x8]549; CHECK-NEXT: ret550entry:551 %vaddlvq_s32.i = tail call i32 @llvm.aarch64.neon.saddlv.i32.v8i16(<8 x i16> %sum_h)552 %idxprom = sext i32 %idx to i64553 %arrayidx = getelementptr inbounds i64, ptr %H, i64 %idxprom554 store i32 %vaddlvq_s32.i, ptr %arrayidx, align 8555 ret void556}557 558define void @store_saddlv_v2i32(ptr %H, <2 x i32> %sum_h, i32 %idx) {559; CHECK-LABEL: store_saddlv_v2i32:560; CHECK: ; %bb.0: ; %entry561; CHECK-NEXT: saddlp.1d v0, v0562; CHECK-NEXT: str d0, [x0, w1, sxtw #3]563; CHECK-NEXT: ret564entry:565 %vaddlvq_s32.i = tail call i64 @llvm.aarch64.neon.saddlv.i64.v2i32(<2 x i32> %sum_h)566 %idxprom = sext i32 %idx to i64567 %arrayidx = getelementptr inbounds i64, ptr %H, i64 %idxprom568 store i64 %vaddlvq_s32.i, ptr %arrayidx, align 8569 ret void570}571 572define void @store_saddlv_v4i32(ptr %H, <4 x i32> %sum_h, i32 %idx) {573; CHECK-LABEL: store_saddlv_v4i32:574; CHECK: ; %bb.0: ; %entry575; CHECK-NEXT: saddlv.4s d0, v0576; CHECK-NEXT: str d0, [x0, w1, sxtw #3]577; CHECK-NEXT: ret578entry:579 %vaddlvq_s32.i = tail call i64 @llvm.aarch64.neon.saddlv.i64.v4i32(<4 x i32> %sum_h)580 %idxprom = sext i32 %idx to i64581 %arrayidx = getelementptr inbounds i64, ptr %H, i64 %idxprom582 store i64 %vaddlvq_s32.i, ptr %arrayidx, align 8583 ret void584}585