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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -mattr=+aes -o - %s| FileCheck %s --check-prefixes=CHECK3 4; User code intends to execute {pmull, pmull2} instructions on {lower, higher} half of the same vector registers directly.5; Test that PMULL2 are generated for higher-half operands.6; The suboptimal code generation fails to use higher-half contents in place; instead, it moves higher-lane contents to lower lane7; to make use of PMULL everywhere, and generates unnecessary moves.8define void @test1(ptr %0, ptr %1) {9; CHECK-LABEL: test1:10; CHECK: // %bb.0:11; CHECK-NEXT: mov w8, #56824 // =0xddf812; CHECK-NEXT: mov w9, #61186 // =0xef0213; CHECK-NEXT: movk w8, #40522, lsl #1614; CHECK-NEXT: movk w9, #29710, lsl #1615; CHECK-NEXT: ldp q0, q1, [x1]16; CHECK-NEXT: dup v2.2d, x817; CHECK-NEXT: fmov d3, x918; CHECK-NEXT: pmull v4.1q, v0.1d, v3.1d19; CHECK-NEXT: pmull v3.1q, v1.1d, v3.1d20; CHECK-NEXT: pmull2 v0.1q, v0.2d, v2.2d21; CHECK-NEXT: pmull2 v1.1q, v1.2d, v2.2d22; CHECK-NEXT: eor v0.16b, v4.16b, v0.16b23; CHECK-NEXT: eor v1.16b, v3.16b, v1.16b24; CHECK-NEXT: stp q0, q1, [x1]25; CHECK-NEXT: ret26 %3 = load <2 x i64>, ptr %127 %4 = getelementptr inbounds <2 x i64>, ptr %1, i64 128 %5 = load <2 x i64>, ptr %429 %6 = extractelement <2 x i64> %3, i64 130 %7 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %6, i64 2655706616)31 %8 = extractelement <2 x i64> %5, i64 132 %9 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %8, i64 2655706616)33 %10 = load <2 x i64>, ptr %034 %11 = getelementptr inbounds i8, ptr %0, i64 1635 %12 = load <2 x i64>, ptr %1136 %13 = extractelement <2 x i64> %3, i64 037 %14 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %13, i64 1947135746)38 %15 = extractelement <2 x i64> %5, i64 039 %16 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %15, i64 1947135746)40 %17 = xor <16 x i8> %14, %741 %18 = xor <16 x i8> %16, %942 store <16 x i8> %17, ptr %143 store <16 x i8> %18, ptr %444 ret void45}46 47; One operand is higher-half of SIMD register, and the other operand is lower-half of another SIMD register.48; Tests that codegen doesn't generate unnecessary moves.49define void @test2(ptr %0, <2 x i64> %1, <2 x i64> %2) {50; CHECK-LABEL: test2:51; CHECK: // %bb.0:52; CHECK-NEXT: dup v1.2d, v1.d[0]53; CHECK-NEXT: pmull2 v0.1q, v0.2d, v1.2d54; CHECK-NEXT: str q0, [x0]55; CHECK-NEXT: ret56 %4 = extractelement <2 x i64> %1, i64 157 %5 = extractelement <2 x i64> %2, i64 058 %6 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %4, i64 %5)59 store <16 x i8> %6, ptr %0, align 1660 ret void61}62 63; Operand %4 is the higher-half of v2i64, and operand %2 is an input parameter of i64.64; Test that %2 is duplicated into the proper lane of SIMD directly for optimal codegen.65define void @test3(ptr %0, <2 x i64> %1, i64 %2) {66; CHECK-LABEL: test3:67; CHECK: // %bb.0:68; CHECK-NEXT: dup v1.2d, x169; CHECK-NEXT: pmull2 v0.1q, v0.2d, v1.2d70; CHECK-NEXT: str q0, [x0]71; CHECK-NEXT: ret72 %4 = extractelement <2 x i64> %1, i64 173 %5 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %4, i64 %2)74 store <16 x i8> %5, ptr %0, align 1675 ret void76}77 78declare <16 x i8> @llvm.aarch64.neon.pmull64(i64, i64)79