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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=aarch64-linux-gnu -O2 -o - %s | FileCheck %s3 4define i64 @test_ssub_nonneg_rhs(i64 %x) {5; CHECK-LABEL: test_ssub_nonneg_rhs:6; CHECK: // %bb.0:7; CHECK-NEXT: mov x8, #-9223372036854775808 // =0x80000000000000008; CHECK-NEXT: subs x9, x0, #19; CHECK-NEXT: csel x0, x8, x9, vs10; CHECK-NEXT: ret11 %sat = call i64 @llvm.ssub.sat.i64(i64 %x, i64 1)12 ret i64 %sat13}14 15define i64 @test_ssub_neg_rhs(i64 %x) {16; CHECK-LABEL: test_ssub_neg_rhs:17; CHECK: // %bb.0:18; CHECK-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff19; CHECK-NEXT: adds x9, x0, #120; CHECK-NEXT: csel x0, x8, x9, vs21; CHECK-NEXT: ret22 %sat = call i64 @llvm.ssub.sat.i64(i64 %x, i64 -1)23 ret i64 %sat24}25 26define i64 @test_sadd_nonneg_rhs(i64 %x) {27; CHECK-LABEL: test_sadd_nonneg_rhs:28; CHECK: // %bb.0:29; CHECK-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff30; CHECK-NEXT: adds x9, x0, #131; CHECK-NEXT: csel x0, x8, x9, vs32; CHECK-NEXT: ret33 %sat = call i64 @llvm.sadd.sat.i64(i64 %x, i64 1)34 ret i64 %sat35}36 37 38define i64 @test_sadd_neg_rhs(i64 %x) {39; CHECK-LABEL: test_sadd_neg_rhs:40; CHECK: // %bb.0:41; CHECK-NEXT: mov x8, #-9223372036854775808 // =0x800000000000000042; CHECK-NEXT: subs x9, x0, #143; CHECK-NEXT: csel x0, x8, x9, vs44; CHECK-NEXT: ret45 %sat = call i64 @llvm.sadd.sat.i64(i64 %x, i64 -1)46 ret i64 %sat47}48 49define i64 @test_ssub_nonneg_lhs(i64 %x) {50; CHECK-LABEL: test_ssub_nonneg_lhs:51; CHECK: // %bb.0:52; CHECK-NEXT: mov w8, #1 // =0x153; CHECK-NEXT: mov x9, #9223372036854775807 // =0x7fffffffffffffff54; CHECK-NEXT: subs x8, x8, x055; CHECK-NEXT: csel x0, x9, x8, vs56; CHECK-NEXT: ret57 %sat = call i64 @llvm.ssub.sat.i64(i64 1, i64 %x)58 ret i64 %sat59}60 61define i64 @test_ssub_neg_lhs(i64 %x) {62; CHECK-LABEL: test_ssub_neg_lhs:63; CHECK: // %bb.0:64; CHECK-NEXT: mvn x0, x065; CHECK-NEXT: ret66 %sat = call i64 @llvm.ssub.sat.i64(i64 -1, i64 %x)67 ret i64 %sat68}69 70define i64 @test_sadd_nonneg_lhs(i64 %x) {71; CHECK-LABEL: test_sadd_nonneg_lhs:72; CHECK: // %bb.0:73; CHECK-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff74; CHECK-NEXT: adds x9, x0, #175; CHECK-NEXT: csel x0, x8, x9, vs76; CHECK-NEXT: ret77 %sat = call i64 @llvm.sadd.sat.i64(i64 1, i64 %x)78 ret i64 %sat79}80 81define i64 @test_sadd_neg_lhs(i64 %x) {82; CHECK-LABEL: test_sadd_neg_lhs:83; CHECK: // %bb.0:84; CHECK-NEXT: mov x8, #-9223372036854775808 // =0x800000000000000085; CHECK-NEXT: subs x9, x0, #186; CHECK-NEXT: csel x0, x8, x9, vs87; CHECK-NEXT: ret88 %sat = call i64 @llvm.sadd.sat.i64(i64 -1, i64 %x)89 ret i64 %sat90}91 92define i64 @test_ssub_nonneg_rhs_nonconst(i64 %x) {93; CHECK-LABEL: test_ssub_nonneg_rhs_nonconst:94; CHECK: // %bb.0:95; CHECK-NEXT: mov w8, #123 // =0x7b96; CHECK-NEXT: mov x9, #-9223372036854775808 // =0x800000000000000097; CHECK-NEXT: and x8, x0, x898; CHECK-NEXT: subs x8, x0, x899; CHECK-NEXT: csel x0, x9, x8, vs100; CHECK-NEXT: ret101 %y = and i64 %x, 123102 %sat = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y)103 ret i64 %sat104}105 106define i64 @test_ssub_neg_rhs_nonconst(i64 %x) {107; CHECK-LABEL: test_ssub_neg_rhs_nonconst:108; CHECK: // %bb.0:109; CHECK-NEXT: cmn x0, #1110; CHECK-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff111; CHECK-NEXT: csinv x9, x0, xzr, lt112; CHECK-NEXT: subs x9, x0, x9113; CHECK-NEXT: csel x0, x8, x9, vs114; CHECK-NEXT: ret115 %y = call i64 @llvm.smin(i64 %x, i64 -1)116 %sat = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y)117 ret i64 %sat118}119 120define i64 @test_sadd_nonneg_rhs_nonconst(i64 %x) {121; CHECK-LABEL: test_sadd_nonneg_rhs_nonconst:122; CHECK: // %bb.0:123; CHECK-NEXT: cmp x0, #1124; CHECK-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff125; CHECK-NEXT: csinc x9, x0, xzr, gt126; CHECK-NEXT: adds x9, x0, x9127; CHECK-NEXT: csel x0, x8, x9, vs128; CHECK-NEXT: ret129 %y = call i64 @llvm.smax(i64 %x, i64 1)130 %sat = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y)131 ret i64 %sat132}133 134 135define i64 @test_sadd_neg_rhs_nonconst(i64 %x) {136; CHECK-LABEL: test_sadd_neg_rhs_nonconst:137; CHECK: // %bb.0:138; CHECK-NEXT: orr x9, x0, #0x8000000000000000139; CHECK-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000140; CHECK-NEXT: adds x9, x0, x9141; CHECK-NEXT: csel x0, x8, x9, vs142; CHECK-NEXT: ret143 %y = or i64 %x, u0x8000000000000000144 %sat = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y)145 ret i64 %sat146}147 148define i64 @test_ssub_nonneg_lhs_nonconst(i64 %x) {149; CHECK-LABEL: test_ssub_nonneg_lhs_nonconst:150; CHECK: // %bb.0:151; CHECK-NEXT: mov w8, #123 // =0x7b152; CHECK-NEXT: mov x9, #9223372036854775807 // =0x7fffffffffffffff153; CHECK-NEXT: and x8, x0, x8154; CHECK-NEXT: subs x8, x8, x0155; CHECK-NEXT: csel x0, x9, x8, vs156; CHECK-NEXT: ret157 %y = and i64 %x, 123158 %sat = call i64 @llvm.ssub.sat.i64(i64 %y, i64 %x)159 ret i64 %sat160}161 162define i64 @test_ssub_neg_lhs_nonconst(i64 %x) {163; CHECK-LABEL: test_ssub_neg_lhs_nonconst:164; CHECK: // %bb.0:165; CHECK-NEXT: cmn x0, #1166; CHECK-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000167; CHECK-NEXT: csinv x9, x0, xzr, lt168; CHECK-NEXT: subs x9, x9, x0169; CHECK-NEXT: csel x0, x8, x9, vs170; CHECK-NEXT: ret171 %y = call i64 @llvm.smin(i64 %x, i64 -1)172 %sat = call i64 @llvm.ssub.sat.i64(i64 %y, i64 %x)173 ret i64 %sat174}175 176define i64 @test_sadd_nonneg_lhs_nonconst(i64 %x) {177; CHECK-LABEL: test_sadd_nonneg_lhs_nonconst:178; CHECK: // %bb.0:179; CHECK-NEXT: cmp x0, #1180; CHECK-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff181; CHECK-NEXT: csinc x9, x0, xzr, gt182; CHECK-NEXT: adds x9, x9, x0183; CHECK-NEXT: csel x0, x8, x9, vs184; CHECK-NEXT: ret185 %y = call i64 @llvm.smax(i64 %x, i64 1)186 %sat = call i64 @llvm.sadd.sat.i64(i64 %y, i64 %x)187 ret i64 %sat188}189 190define i64 @test_sadd_neg_lhs_nonconst(i64 %x) {191; CHECK-LABEL: test_sadd_neg_lhs_nonconst:192; CHECK: // %bb.0:193; CHECK-NEXT: orr x9, x0, #0x8000000000000000194; CHECK-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000195; CHECK-NEXT: adds x9, x9, x0196; CHECK-NEXT: csel x0, x8, x9, vs197; CHECK-NEXT: ret198 %y = or i64 %x, u0x8000000000000000199 %sat = call i64 @llvm.sadd.sat.i64(i64 %y, i64 %x)200 ret i64 %sat201}202 203declare i64 @llvm.sadd.sat.i64(i64, i64)204declare i64 @llvm.ssub.sat.i64(i64, i64)205declare i64 @llvm.smax(i64, i64)206declare i64 @llvm.smin(i64, i64)207