129 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6define i32 @i8_i32(<vscale x 16 x i8> %a) #0 {7; CHECK-LABEL: i8_i32:8; CHECK: // %bb.0: // %entry9; CHECK-NEXT: smov w0, v0.b[15]10; CHECK-NEXT: ret11entry:12 %elt = extractelement <vscale x 16 x i8> %a, i32 1513 %conv = sext i8 %elt to i3214 ret i32 %conv15}16 17define i64 @i8_i64(<vscale x 16 x i8> %a) #0 {18; CHECK-LABEL: i8_i64:19; CHECK: // %bb.0: // %entry20; CHECK-NEXT: smov x0, v0.b[15]21; CHECK-NEXT: ret22entry:23 %elt = extractelement <vscale x 16 x i8> %a, i32 1524 %conv = sext i8 %elt to i6425 ret i64 %conv26}27 28define i32 @i16_i32(<vscale x 8 x i16> %a) #0 {29; CHECK-LABEL: i16_i32:30; CHECK: // %bb.0: // %entry31; CHECK-NEXT: smov w0, v0.h[7]32; CHECK-NEXT: ret33entry:34 %elt = extractelement <vscale x 8 x i16> %a, i32 735 %conv = sext i16 %elt to i3236 ret i32 %conv37}38 39define i64 @i16_i64(<vscale x 8 x i16> %a) #0 {40; CHECK-LABEL: i16_i64:41; CHECK: // %bb.0: // %entry42; CHECK-NEXT: smov x0, v0.h[7]43; CHECK-NEXT: ret44entry:45 %elt = extractelement <vscale x 8 x i16> %a, i32 746 %conv = sext i16 %elt to i6447 ret i64 %conv48}49 50define i64 @i32_i64(<vscale x 4 x i32> %a) #0 {51; CHECK-LABEL: i32_i64:52; CHECK: // %bb.0: // %entry53; CHECK-NEXT: smov x0, v0.s[3]54; CHECK-NEXT: ret55entry:56 %elt = extractelement <vscale x 4 x i32> %a, i32 357 %conv = sext i32 %elt to i6458 ret i64 %conv59}60 61; NOTE: Testing out-of-range indices62 63define i32 @i8_i32_oor(<vscale x 16 x i8> %a) #0 {64; CHECK-LABEL: i8_i32_oor:65; CHECK: // %bb.0: // %entry66; CHECK-NEXT: mov z0.b, z0.b[16]67; CHECK-NEXT: fmov w8, s068; CHECK-NEXT: sxtb w0, w869; CHECK-NEXT: ret70entry:71 %elt = extractelement <vscale x 16 x i8> %a, i32 1672 %conv = sext i8 %elt to i3273 ret i32 %conv74}75 76define i64 @i8_i64_oor(<vscale x 16 x i8> %a) #0 {77; CHECK-LABEL: i8_i64_oor:78; CHECK: // %bb.0: // %entry79; CHECK-NEXT: mov z0.b, z0.b[16]80; CHECK-NEXT: fmov w8, s081; CHECK-NEXT: sxtb x0, w882; CHECK-NEXT: ret83entry:84 %elt = extractelement <vscale x 16 x i8> %a, i32 1685 %conv = sext i8 %elt to i6486 ret i64 %conv87}88 89define i32 @i16_i32_oor(<vscale x 8 x i16> %a) #0 {90; CHECK-LABEL: i16_i32_oor:91; CHECK: // %bb.0: // %entry92; CHECK-NEXT: mov z0.h, z0.h[8]93; CHECK-NEXT: fmov w8, s094; CHECK-NEXT: sxth w0, w895; CHECK-NEXT: ret96entry:97 %elt = extractelement <vscale x 8 x i16> %a, i32 898 %conv = sext i16 %elt to i3299 ret i32 %conv100}101 102define i64 @i16_i64_oor(<vscale x 8 x i16> %a) #0 {103; CHECK-LABEL: i16_i64_oor:104; CHECK: // %bb.0: // %entry105; CHECK-NEXT: mov z0.h, z0.h[8]106; CHECK-NEXT: fmov w8, s0107; CHECK-NEXT: sxth x0, w8108; CHECK-NEXT: ret109entry:110 %elt = extractelement <vscale x 8 x i16> %a, i32 8111 %conv = sext i16 %elt to i64112 ret i64 %conv113}114 115define i64 @i32_i64_oor(<vscale x 4 x i32> %a) #0 {116; CHECK-LABEL: i32_i64_oor:117; CHECK: // %bb.0: // %entry118; CHECK-NEXT: mov z0.s, z0.s[4]119; CHECK-NEXT: fmov w8, s0120; CHECK-NEXT: sxtw x0, w8121; CHECK-NEXT: ret122entry:123 %elt = extractelement <vscale x 4 x i32> %a, i32 4124 %conv = sext i32 %elt to i64125 ret i64 %conv126}127 128attributes #0 = { "target-features"="+sve" }129