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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -mattr=+sve -aarch64-sve-vector-bits-min=128 -aarch64-sve-vector-bits-max=128 < %s | FileCheck %s3; RUN: llc -verify-machineinstrs -mtriple=aarch64_be-linux-gnu -mattr=+sve -aarch64-sve-vector-bits-min=128 -aarch64-sve-vector-bits-max=128 < %s | FileCheck %s --check-prefixes=CHECK-BE4; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -mattr=+sve,ldp-aligned-only -aarch64-sve-vector-bits-min=128 -aarch64-sve-vector-bits-max=128 < %s | FileCheck %s --check-prefixes=CHECK-LDPALIGNEDONLY5; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -mattr=+sve,stp-aligned-only -aarch64-sve-vector-bits-min=128 -aarch64-sve-vector-bits-max=128 < %s | FileCheck %s --check-prefixes=CHECK-STPALIGNEDONLY6; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s --check-prefixes=CHECK-OFF7; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -mattr=+sve -aarch64-sve-vector-bits-min=256 -aarch64-sve-vector-bits-max=256 < %s | FileCheck %s --check-prefixes=CHECK-OFF8 9define void @nxv16i8(ptr %ldptr, ptr %stptr) {10; CHECK-LABEL: nxv16i8:11; CHECK: // %bb.0:12; CHECK-NEXT: ldp q0, q1, [x0]13; CHECK-NEXT: stp q0, q1, [x1]14; CHECK-NEXT: ret15;16; CHECK-BE-LABEL: nxv16i8:17; CHECK-BE: // %bb.0:18; CHECK-BE-NEXT: ptrue p0.b19; CHECK-BE-NEXT: ld1b { z0.b }, p0/z, [x0]20; CHECK-BE-NEXT: ld1b { z1.b }, p0/z, [x0, #1, mul vl]21; CHECK-BE-NEXT: st1b { z0.b }, p0, [x1]22; CHECK-BE-NEXT: st1b { z1.b }, p0, [x1, #1, mul vl]23; CHECK-BE-NEXT: ret24;25; CHECK-LDPALIGNEDONLY-LABEL: nxv16i8:26; CHECK-LDPALIGNEDONLY: // %bb.0:27; CHECK-LDPALIGNEDONLY-NEXT: ldr z0, [x0]28; CHECK-LDPALIGNEDONLY-NEXT: ldr z1, [x0, #1, mul vl]29; CHECK-LDPALIGNEDONLY-NEXT: stp q0, q1, [x1]30; CHECK-LDPALIGNEDONLY-NEXT: ret31;32; CHECK-STPALIGNEDONLY-LABEL: nxv16i8:33; CHECK-STPALIGNEDONLY: // %bb.0:34; CHECK-STPALIGNEDONLY-NEXT: ldp q0, q1, [x0]35; CHECK-STPALIGNEDONLY-NEXT: str z0, [x1]36; CHECK-STPALIGNEDONLY-NEXT: str z1, [x1, #1, mul vl]37; CHECK-STPALIGNEDONLY-NEXT: ret38;39; CHECK-OFF-LABEL: nxv16i8:40; CHECK-OFF: // %bb.0:41; CHECK-OFF-NEXT: ldr z0, [x0]42; CHECK-OFF-NEXT: ldr z1, [x0, #1, mul vl]43; CHECK-OFF-NEXT: str z0, [x1]44; CHECK-OFF-NEXT: str z1, [x1, #1, mul vl]45; CHECK-OFF-NEXT: ret46 %vscale = tail call i64 @llvm.vscale()47 %vl = shl nuw nsw i64 %vscale, 448 %ldptr2 = getelementptr inbounds nuw i8, ptr %ldptr, i64 %vl49 %stptr2 = getelementptr inbounds nuw i8, ptr %stptr, i64 %vl50 %ld1 = load <vscale x 16 x i8>, ptr %ldptr, align 151 %ld2 = load <vscale x 16 x i8>, ptr %ldptr2, align 152 store <vscale x 16 x i8> %ld1, ptr %stptr, align 153 store <vscale x 16 x i8> %ld2, ptr %stptr2, align 154 ret void55}56 57define void @nxv16i8_max_range(ptr %ldptr, ptr %stptr) {58; CHECK-LABEL: nxv16i8_max_range:59; CHECK: // %bb.0:60; CHECK-NEXT: ldp q0, q1, [x0, #-1024]61; CHECK-NEXT: stp q0, q1, [x1, #1008]62; CHECK-NEXT: ret63;64; CHECK-BE-LABEL: nxv16i8_max_range:65; CHECK-BE: // %bb.0:66; CHECK-BE-NEXT: rdvl x8, #167; CHECK-BE-NEXT: mov x9, #-1008 // =0xfffffffffffffc1068; CHECK-BE-NEXT: mov x10, #-1024 // =0xfffffffffffffc0069; CHECK-BE-NEXT: lsr x8, x8, #470; CHECK-BE-NEXT: mov w11, #1008 // =0x3f071; CHECK-BE-NEXT: mov w12, #1024 // =0x40072; CHECK-BE-NEXT: ptrue p0.b73; CHECK-BE-NEXT: mul x9, x8, x974; CHECK-BE-NEXT: mul x10, x8, x1075; CHECK-BE-NEXT: mul x11, x8, x1176; CHECK-BE-NEXT: ld1b { z1.b }, p0/z, [x0, x9]77; CHECK-BE-NEXT: mul x8, x8, x1278; CHECK-BE-NEXT: ld1b { z0.b }, p0/z, [x0, x10]79; CHECK-BE-NEXT: st1b { z0.b }, p0, [x1, x11]80; CHECK-BE-NEXT: st1b { z1.b }, p0, [x1, x8]81; CHECK-BE-NEXT: ret82;83; CHECK-LDPALIGNEDONLY-LABEL: nxv16i8_max_range:84; CHECK-LDPALIGNEDONLY: // %bb.0:85; CHECK-LDPALIGNEDONLY-NEXT: ldr z0, [x0, #-64, mul vl]86; CHECK-LDPALIGNEDONLY-NEXT: ldr z1, [x0, #-63, mul vl]87; CHECK-LDPALIGNEDONLY-NEXT: stp q0, q1, [x1, #1008]88; CHECK-LDPALIGNEDONLY-NEXT: ret89;90; CHECK-STPALIGNEDONLY-LABEL: nxv16i8_max_range:91; CHECK-STPALIGNEDONLY: // %bb.0:92; CHECK-STPALIGNEDONLY-NEXT: ldp q0, q1, [x0, #-1024]93; CHECK-STPALIGNEDONLY-NEXT: str z0, [x1, #63, mul vl]94; CHECK-STPALIGNEDONLY-NEXT: str z1, [x1, #64, mul vl]95; CHECK-STPALIGNEDONLY-NEXT: ret96;97; CHECK-OFF-LABEL: nxv16i8_max_range:98; CHECK-OFF: // %bb.0:99; CHECK-OFF-NEXT: ldr z0, [x0, #-64, mul vl]100; CHECK-OFF-NEXT: ldr z1, [x0, #-63, mul vl]101; CHECK-OFF-NEXT: str z0, [x1, #63, mul vl]102; CHECK-OFF-NEXT: str z1, [x1, #64, mul vl]103; CHECK-OFF-NEXT: ret104 %vscale = tail call i64 @llvm.vscale()105 %ldoff1 = mul i64 %vscale, -1024106 %ldoff2 = mul i64 %vscale, -1008107 %stoff1 = mul i64 %vscale, 1008108 %stoff2 = mul i64 %vscale, 1024109 %ldptr1 = getelementptr inbounds nuw i8, ptr %ldptr, i64 %ldoff1110 %ldptr2 = getelementptr inbounds nuw i8, ptr %ldptr, i64 %ldoff2111 %stptr1 = getelementptr inbounds nuw i8, ptr %stptr, i64 %stoff1112 %stptr2 = getelementptr inbounds nuw i8, ptr %stptr, i64 %stoff2113 %ld1 = load <vscale x 16 x i8>, ptr %ldptr1, align 1114 %ld2 = load <vscale x 16 x i8>, ptr %ldptr2, align 1115 store <vscale x 16 x i8> %ld1, ptr %stptr1, align 1116 store <vscale x 16 x i8> %ld2, ptr %stptr2, align 1117 ret void118}119 120define void @nxv16i8_outside_range(ptr %ldptr, ptr %stptr) {121; CHECK-LABEL: nxv16i8_outside_range:122; CHECK: // %bb.0:123; CHECK-NEXT: ldr z0, [x0, #-65, mul vl]124; CHECK-NEXT: ldr z1, [x0, #-64, mul vl]125; CHECK-NEXT: str z0, [x1, #64, mul vl]126; CHECK-NEXT: str z1, [x1, #65, mul vl]127; CHECK-NEXT: ret128;129; CHECK-BE-LABEL: nxv16i8_outside_range:130; CHECK-BE: // %bb.0:131; CHECK-BE-NEXT: rdvl x8, #1132; CHECK-BE-NEXT: mov x9, #-1040 // =0xfffffffffffffbf0133; CHECK-BE-NEXT: mov x10, #-1024 // =0xfffffffffffffc00134; CHECK-BE-NEXT: lsr x8, x8, #4135; CHECK-BE-NEXT: mov w11, #1024 // =0x400136; CHECK-BE-NEXT: mov w12, #1040 // =0x410137; CHECK-BE-NEXT: ptrue p0.b138; CHECK-BE-NEXT: mul x9, x8, x9139; CHECK-BE-NEXT: mul x10, x8, x10140; CHECK-BE-NEXT: mul x11, x8, x11141; CHECK-BE-NEXT: ld1b { z0.b }, p0/z, [x0, x9]142; CHECK-BE-NEXT: mul x8, x8, x12143; CHECK-BE-NEXT: ld1b { z1.b }, p0/z, [x0, x10]144; CHECK-BE-NEXT: st1b { z0.b }, p0, [x1, x11]145; CHECK-BE-NEXT: st1b { z1.b }, p0, [x1, x8]146; CHECK-BE-NEXT: ret147;148; CHECK-LDPALIGNEDONLY-LABEL: nxv16i8_outside_range:149; CHECK-LDPALIGNEDONLY: // %bb.0:150; CHECK-LDPALIGNEDONLY-NEXT: ldr z0, [x0, #-65, mul vl]151; CHECK-LDPALIGNEDONLY-NEXT: ldr z1, [x0, #-64, mul vl]152; CHECK-LDPALIGNEDONLY-NEXT: str z0, [x1, #64, mul vl]153; CHECK-LDPALIGNEDONLY-NEXT: str z1, [x1, #65, mul vl]154; CHECK-LDPALIGNEDONLY-NEXT: ret155;156; CHECK-STPALIGNEDONLY-LABEL: nxv16i8_outside_range:157; CHECK-STPALIGNEDONLY: // %bb.0:158; CHECK-STPALIGNEDONLY-NEXT: ldr z0, [x0, #-65, mul vl]159; CHECK-STPALIGNEDONLY-NEXT: ldr z1, [x0, #-64, mul vl]160; CHECK-STPALIGNEDONLY-NEXT: str z0, [x1, #64, mul vl]161; CHECK-STPALIGNEDONLY-NEXT: str z1, [x1, #65, mul vl]162; CHECK-STPALIGNEDONLY-NEXT: ret163;164; CHECK-OFF-LABEL: nxv16i8_outside_range:165; CHECK-OFF: // %bb.0:166; CHECK-OFF-NEXT: ldr z0, [x0, #-65, mul vl]167; CHECK-OFF-NEXT: ldr z1, [x0, #-64, mul vl]168; CHECK-OFF-NEXT: str z0, [x1, #64, mul vl]169; CHECK-OFF-NEXT: str z1, [x1, #65, mul vl]170; CHECK-OFF-NEXT: ret171 %vscale = tail call i64 @llvm.vscale()172 %ldoff1 = mul i64 %vscale, -1040173 %ldoff2 = mul i64 %vscale, -1024174 %stoff1 = mul i64 %vscale, 1024175 %stoff2 = mul i64 %vscale, 1040176 %ldptr1 = getelementptr inbounds nuw i8, ptr %ldptr, i64 %ldoff1177 %ldptr2 = getelementptr inbounds nuw i8, ptr %ldptr, i64 %ldoff2178 %stptr1 = getelementptr inbounds nuw i8, ptr %stptr, i64 %stoff1179 %stptr2 = getelementptr inbounds nuw i8, ptr %stptr, i64 %stoff2180 %ld1 = load <vscale x 16 x i8>, ptr %ldptr1, align 1181 %ld2 = load <vscale x 16 x i8>, ptr %ldptr2, align 1182 store <vscale x 16 x i8> %ld1, ptr %stptr1, align 1183 store <vscale x 16 x i8> %ld2, ptr %stptr2, align 1184 ret void185}186 187define void @nxv16i8_2vl_stride(ptr %ldptr, ptr %stptr) {188; CHECK-LABEL: nxv16i8_2vl_stride:189; CHECK: // %bb.0:190; CHECK-NEXT: ldr z0, [x0]191; CHECK-NEXT: ldr z1, [x0, #2, mul vl]192; CHECK-NEXT: str z0, [x1]193; CHECK-NEXT: str z1, [x1, #2, mul vl]194; CHECK-NEXT: ret195;196; CHECK-BE-LABEL: nxv16i8_2vl_stride:197; CHECK-BE: // %bb.0:198; CHECK-BE-NEXT: ptrue p0.b199; CHECK-BE-NEXT: ld1b { z0.b }, p0/z, [x0]200; CHECK-BE-NEXT: ld1b { z1.b }, p0/z, [x0, #2, mul vl]201; CHECK-BE-NEXT: st1b { z0.b }, p0, [x1]202; CHECK-BE-NEXT: st1b { z1.b }, p0, [x1, #2, mul vl]203; CHECK-BE-NEXT: ret204;205; CHECK-LDPALIGNEDONLY-LABEL: nxv16i8_2vl_stride:206; CHECK-LDPALIGNEDONLY: // %bb.0:207; CHECK-LDPALIGNEDONLY-NEXT: ldr z0, [x0]208; CHECK-LDPALIGNEDONLY-NEXT: ldr z1, [x0, #2, mul vl]209; CHECK-LDPALIGNEDONLY-NEXT: str z0, [x1]210; CHECK-LDPALIGNEDONLY-NEXT: str z1, [x1, #2, mul vl]211; CHECK-LDPALIGNEDONLY-NEXT: ret212;213; CHECK-STPALIGNEDONLY-LABEL: nxv16i8_2vl_stride:214; CHECK-STPALIGNEDONLY: // %bb.0:215; CHECK-STPALIGNEDONLY-NEXT: ldr z0, [x0]216; CHECK-STPALIGNEDONLY-NEXT: ldr z1, [x0, #2, mul vl]217; CHECK-STPALIGNEDONLY-NEXT: str z0, [x1]218; CHECK-STPALIGNEDONLY-NEXT: str z1, [x1, #2, mul vl]219; CHECK-STPALIGNEDONLY-NEXT: ret220;221; CHECK-OFF-LABEL: nxv16i8_2vl_stride:222; CHECK-OFF: // %bb.0:223; CHECK-OFF-NEXT: ldr z0, [x0]224; CHECK-OFF-NEXT: ldr z1, [x0, #2, mul vl]225; CHECK-OFF-NEXT: str z0, [x1]226; CHECK-OFF-NEXT: str z1, [x1, #2, mul vl]227; CHECK-OFF-NEXT: ret228 %vscale = tail call i64 @llvm.vscale()229 %vl = shl nuw nsw i64 %vscale, 5230 %ldptr2 = getelementptr inbounds nuw i8, ptr %ldptr, i64 %vl231 %stptr2 = getelementptr inbounds nuw i8, ptr %stptr, i64 %vl232 %ld1 = load <vscale x 16 x i8>, ptr %ldptr, align 1233 %ld2 = load <vscale x 16 x i8>, ptr %ldptr2, align 1234 store <vscale x 16 x i8> %ld1, ptr %stptr, align 1235 store <vscale x 16 x i8> %ld2, ptr %stptr2, align 1236 ret void237}238 239define void @nxv2f64_32b_aligned(ptr %ldptr, ptr %stptr) {240; CHECK-LABEL: nxv2f64_32b_aligned:241; CHECK: // %bb.0:242; CHECK-NEXT: ldp q0, q1, [x0]243; CHECK-NEXT: stp q0, q1, [x1]244; CHECK-NEXT: ret245;246; CHECK-BE-LABEL: nxv2f64_32b_aligned:247; CHECK-BE: // %bb.0:248; CHECK-BE-NEXT: ptrue p0.d249; CHECK-BE-NEXT: ld1d { z0.d }, p0/z, [x0]250; CHECK-BE-NEXT: ld1d { z1.d }, p0/z, [x0, #1, mul vl]251; CHECK-BE-NEXT: st1d { z0.d }, p0, [x1]252; CHECK-BE-NEXT: st1d { z1.d }, p0, [x1, #1, mul vl]253; CHECK-BE-NEXT: ret254;255; CHECK-LDPALIGNEDONLY-LABEL: nxv2f64_32b_aligned:256; CHECK-LDPALIGNEDONLY: // %bb.0:257; CHECK-LDPALIGNEDONLY-NEXT: ldp q0, q1, [x0]258; CHECK-LDPALIGNEDONLY-NEXT: stp q0, q1, [x1]259; CHECK-LDPALIGNEDONLY-NEXT: ret260;261; CHECK-STPALIGNEDONLY-LABEL: nxv2f64_32b_aligned:262; CHECK-STPALIGNEDONLY: // %bb.0:263; CHECK-STPALIGNEDONLY-NEXT: ldp q0, q1, [x0]264; CHECK-STPALIGNEDONLY-NEXT: stp q0, q1, [x1]265; CHECK-STPALIGNEDONLY-NEXT: ret266;267; CHECK-OFF-LABEL: nxv2f64_32b_aligned:268; CHECK-OFF: // %bb.0:269; CHECK-OFF-NEXT: ldr z0, [x0]270; CHECK-OFF-NEXT: ldr z1, [x0, #1, mul vl]271; CHECK-OFF-NEXT: str z0, [x1]272; CHECK-OFF-NEXT: str z1, [x1, #1, mul vl]273; CHECK-OFF-NEXT: ret274 %vscale = tail call i64 @llvm.vscale()275 %vl = shl nuw nsw i64 %vscale, 4276 %ldptr2 = getelementptr inbounds nuw i8, ptr %ldptr, i64 %vl277 %stptr2 = getelementptr inbounds nuw i8, ptr %stptr, i64 %vl278 %ld1 = load <vscale x 2 x double>, ptr %ldptr, align 32279 %ld2 = load <vscale x 2 x double>, ptr %ldptr2, align 32280 store <vscale x 2 x double> %ld1, ptr %stptr, align 32281 store <vscale x 2 x double> %ld2, ptr %stptr2, align 32282 ret void283}284