303 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple aarch64-none-linux-gnu | FileCheck --check-prefix=CHECK-LE %s3; RUN: llc < %s -mtriple aarch64_be-none-linux-gnu | FileCheck --check-prefix=CHECK-BE %s4 5define <4 x i16> @test_combine_v4i16_v2i64(<2 x i64> %a, <2 x i64> %b) {6; CHECK-LE-LABEL: test_combine_v4i16_v2i64:7; CHECK-LE: // %bb.0:8; CHECK-LE-NEXT: uzp1 v0.4s, v0.4s, v1.4s9; CHECK-LE-NEXT: xtn v0.4h, v0.4s10; CHECK-LE-NEXT: ret11;12; CHECK-BE-LABEL: test_combine_v4i16_v2i64:13; CHECK-BE: // %bb.0:14; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #815; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #816; CHECK-BE-NEXT: xtn v0.2s, v0.2d17; CHECK-BE-NEXT: xtn v1.2s, v1.2d18; CHECK-BE-NEXT: rev32 v0.4h, v0.4h19; CHECK-BE-NEXT: rev32 v1.4h, v1.4h20; CHECK-BE-NEXT: uzp1 v0.4h, v0.4h, v1.4h21; CHECK-BE-NEXT: rev64 v0.4h, v0.4h22; CHECK-BE-NEXT: ret23 %a1 = trunc <2 x i64> %a to <2 x i32>24 %b1 = trunc <2 x i64> %b to <2 x i32>25 26 %a2 = bitcast <2 x i32> %a1 to <4 x i16>27 %b2 = bitcast <2 x i32> %b1 to <4 x i16>28 29 %ab = shufflevector <4 x i16> %a2, <4 x i16> %b2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>30 ret <4 x i16> %ab31}32 33define <4 x i16> @test_combine_v4i16_v4i32(<4 x i32> %a, <4 x i32> %b) {34; CHECK-LE-LABEL: test_combine_v4i16_v4i32:35; CHECK-LE: // %bb.0:36; CHECK-LE-NEXT: uzp1 v0.8h, v0.8h, v1.8h37; CHECK-LE-NEXT: xtn v0.4h, v0.4s38; CHECK-LE-NEXT: ret39;40; CHECK-BE-LABEL: test_combine_v4i16_v4i32:41; CHECK-BE: // %bb.0:42; CHECK-BE-NEXT: rev64 v1.4s, v1.4s43; CHECK-BE-NEXT: rev64 v0.4s, v0.4s44; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #845; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #846; CHECK-BE-NEXT: xtn v0.4h, v0.4s47; CHECK-BE-NEXT: xtn v1.4h, v1.4s48; CHECK-BE-NEXT: uzp1 v0.4h, v0.4h, v1.4h49; CHECK-BE-NEXT: rev64 v0.4h, v0.4h50; CHECK-BE-NEXT: ret51 %a1 = trunc <4 x i32> %a to <4 x i16>52 %b1 = trunc <4 x i32> %b to <4 x i16>53 54 %ab = shufflevector <4 x i16> %a1, <4 x i16> %b1, <4 x i32> <i32 0, i32 2, i32 4, i32 6>55 ret <4 x i16> %ab56}57 58define <4 x i16> @test_combine_v4i16_v8i16(<8 x i16> %a, <8 x i16> %b) {59; CHECK-LE-LABEL: test_combine_v4i16_v8i16:60; CHECK-LE: // %bb.0:61; CHECK-LE-NEXT: uzp1 v0.16b, v0.16b, v1.16b62; CHECK-LE-NEXT: xtn v0.4h, v0.4s63; CHECK-LE-NEXT: ret64;65; CHECK-BE-LABEL: test_combine_v4i16_v8i16:66; CHECK-BE: // %bb.0:67; CHECK-BE-NEXT: rev64 v1.8h, v1.8h68; CHECK-BE-NEXT: rev64 v0.8h, v0.8h69; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #870; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #871; CHECK-BE-NEXT: xtn v0.8b, v0.8h72; CHECK-BE-NEXT: xtn v1.8b, v1.8h73; CHECK-BE-NEXT: rev16 v0.8b, v0.8b74; CHECK-BE-NEXT: rev16 v1.8b, v1.8b75; CHECK-BE-NEXT: uzp1 v0.4h, v0.4h, v1.4h76; CHECK-BE-NEXT: rev64 v0.4h, v0.4h77; CHECK-BE-NEXT: ret78 %a1 = trunc <8 x i16> %a to <8 x i8>79 %b1 = trunc <8 x i16> %b to <8 x i8>80 81 %a2 = bitcast <8 x i8> %a1 to <4 x i16>82 %b2 = bitcast <8 x i8> %b1 to <4 x i16>83 84 %ab = shufflevector <4 x i16> %a2, <4 x i16> %b2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>85 ret <4 x i16> %ab86}87 88 89define <8 x i8> @test_combine_v8i8_v2i64(<2 x i64> %a, <2 x i64> %b) {90; CHECK-LE-LABEL: test_combine_v8i8_v2i64:91; CHECK-LE: // %bb.0:92; CHECK-LE-NEXT: uzp1 v0.4s, v0.4s, v1.4s93; CHECK-LE-NEXT: xtn v0.8b, v0.8h94; CHECK-LE-NEXT: ret95;96; CHECK-BE-LABEL: test_combine_v8i8_v2i64:97; CHECK-BE: // %bb.0:98; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #899; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8100; CHECK-BE-NEXT: xtn v0.2s, v0.2d101; CHECK-BE-NEXT: xtn v1.2s, v1.2d102; CHECK-BE-NEXT: rev32 v0.8b, v0.8b103; CHECK-BE-NEXT: rev32 v1.8b, v1.8b104; CHECK-BE-NEXT: uzp1 v0.8b, v0.8b, v1.8b105; CHECK-BE-NEXT: rev64 v0.8b, v0.8b106; CHECK-BE-NEXT: ret107 %a1 = trunc <2 x i64> %a to <2 x i32>108 %b1 = trunc <2 x i64> %b to <2 x i32>109 110 %a2 = bitcast <2 x i32> %a1 to <8 x i8>111 %b2 = bitcast <2 x i32> %b1 to <8 x i8>112 113 %ab = shufflevector <8 x i8> %a2, <8 x i8> %b2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>114 ret <8 x i8> %ab115}116 117define <8 x i8> @test_combine_v8i8_v4i32(<4 x i32> %a, <4 x i32> %b) {118; CHECK-LE-LABEL: test_combine_v8i8_v4i32:119; CHECK-LE: // %bb.0:120; CHECK-LE-NEXT: uzp1 v0.8h, v0.8h, v1.8h121; CHECK-LE-NEXT: xtn v0.8b, v0.8h122; CHECK-LE-NEXT: ret123;124; CHECK-BE-LABEL: test_combine_v8i8_v4i32:125; CHECK-BE: // %bb.0:126; CHECK-BE-NEXT: rev64 v1.4s, v1.4s127; CHECK-BE-NEXT: rev64 v0.4s, v0.4s128; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8129; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8130; CHECK-BE-NEXT: xtn v0.4h, v0.4s131; CHECK-BE-NEXT: xtn v1.4h, v1.4s132; CHECK-BE-NEXT: rev16 v0.8b, v0.8b133; CHECK-BE-NEXT: rev16 v1.8b, v1.8b134; CHECK-BE-NEXT: uzp1 v0.8b, v0.8b, v1.8b135; CHECK-BE-NEXT: rev64 v0.8b, v0.8b136; CHECK-BE-NEXT: ret137 %a1 = trunc <4 x i32> %a to <4 x i16>138 %b1 = trunc <4 x i32> %b to <4 x i16>139 140 %a2 = bitcast <4 x i16> %a1 to <8 x i8>141 %b2 = bitcast <4 x i16> %b1 to <8 x i8>142 143 %ab = shufflevector <8 x i8> %a2, <8 x i8> %b2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>144 ret <8 x i8> %ab145}146 147define <8 x i8> @test_combine_v8i8_v8i16(<8 x i16> %a, <8 x i16> %b) {148; CHECK-LE-LABEL: test_combine_v8i8_v8i16:149; CHECK-LE: // %bb.0:150; CHECK-LE-NEXT: uzp1 v0.16b, v0.16b, v1.16b151; CHECK-LE-NEXT: xtn v0.8b, v0.8h152; CHECK-LE-NEXT: ret153;154; CHECK-BE-LABEL: test_combine_v8i8_v8i16:155; CHECK-BE: // %bb.0:156; CHECK-BE-NEXT: rev64 v1.8h, v1.8h157; CHECK-BE-NEXT: rev64 v0.8h, v0.8h158; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8159; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8160; CHECK-BE-NEXT: xtn v0.8b, v0.8h161; CHECK-BE-NEXT: xtn v1.8b, v1.8h162; CHECK-BE-NEXT: uzp1 v0.8b, v0.8b, v1.8b163; CHECK-BE-NEXT: rev64 v0.8b, v0.8b164; CHECK-BE-NEXT: ret165 %a1 = trunc <8 x i16> %a to <8 x i8>166 %b1 = trunc <8 x i16> %b to <8 x i8>167 168 %ab = shufflevector <8 x i8> %a1, <8 x i8> %b1, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>169 ret <8 x i8> %ab170}171 172define <2 x i32> @test_combine_v2i32_v2i64(<2 x i64> %a, <2 x i64> %b) {173; CHECK-LE-LABEL: test_combine_v2i32_v2i64:174; CHECK-LE: // %bb.0:175; CHECK-LE-NEXT: xtn v0.2s, v0.2d176; CHECK-LE-NEXT: xtn v1.2s, v1.2d177; CHECK-LE-NEXT: zip1 v0.2s, v0.2s, v1.2s178; CHECK-LE-NEXT: ret179;180; CHECK-BE-LABEL: test_combine_v2i32_v2i64:181; CHECK-BE: // %bb.0:182; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8183; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8184; CHECK-BE-NEXT: xtn v0.2s, v0.2d185; CHECK-BE-NEXT: xtn v1.2s, v1.2d186; CHECK-BE-NEXT: zip1 v0.2s, v0.2s, v1.2s187; CHECK-BE-NEXT: rev64 v0.2s, v0.2s188; CHECK-BE-NEXT: ret189 %a1 = trunc <2 x i64> %a to <2 x i32>190 %b1 = trunc <2 x i64> %b to <2 x i32>191 192 %ab = shufflevector <2 x i32> %a1, <2 x i32> %b1, <2 x i32> <i32 0, i32 2>193 ret <2 x i32> %ab194}195 196define <2 x i32> @test_combine_v2i32_v4i32(<4 x i32> %a, <4 x i32> %b) {197; CHECK-LE-LABEL: test_combine_v2i32_v4i32:198; CHECK-LE: // %bb.0:199; CHECK-LE-NEXT: xtn v0.4h, v0.4s200; CHECK-LE-NEXT: xtn v1.4h, v1.4s201; CHECK-LE-NEXT: zip1 v0.2s, v0.2s, v1.2s202; CHECK-LE-NEXT: ret203;204; CHECK-BE-LABEL: test_combine_v2i32_v4i32:205; CHECK-BE: // %bb.0:206; CHECK-BE-NEXT: rev64 v1.4s, v1.4s207; CHECK-BE-NEXT: rev64 v0.4s, v0.4s208; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8209; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8210; CHECK-BE-NEXT: xtn v0.4h, v0.4s211; CHECK-BE-NEXT: xtn v1.4h, v1.4s212; CHECK-BE-NEXT: rev32 v0.4h, v0.4h213; CHECK-BE-NEXT: rev32 v1.4h, v1.4h214; CHECK-BE-NEXT: zip1 v0.2s, v0.2s, v1.2s215; CHECK-BE-NEXT: rev64 v0.2s, v0.2s216; CHECK-BE-NEXT: ret217 %a1 = trunc <4 x i32> %a to <4 x i16>218 %b1 = trunc <4 x i32> %b to <4 x i16>219 220 %a2 = bitcast <4 x i16> %a1 to <2 x i32>221 %b2 = bitcast <4 x i16> %b1 to <2 x i32>222 223 %ab = shufflevector <2 x i32> %a2, <2 x i32> %b2, <2 x i32> <i32 0, i32 2>224 ret <2 x i32> %ab225}226 227define <2 x i32> @test_combine_v2i32_v8i16(<8 x i16> %a, <8 x i16> %b) {228; CHECK-LE-LABEL: test_combine_v2i32_v8i16:229; CHECK-LE: // %bb.0:230; CHECK-LE-NEXT: xtn v0.8b, v0.8h231; CHECK-LE-NEXT: xtn v1.8b, v1.8h232; CHECK-LE-NEXT: zip1 v0.2s, v0.2s, v1.2s233; CHECK-LE-NEXT: ret234;235; CHECK-BE-LABEL: test_combine_v2i32_v8i16:236; CHECK-BE: // %bb.0:237; CHECK-BE-NEXT: rev64 v1.8h, v1.8h238; CHECK-BE-NEXT: rev64 v0.8h, v0.8h239; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8240; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8241; CHECK-BE-NEXT: xtn v0.8b, v0.8h242; CHECK-BE-NEXT: xtn v1.8b, v1.8h243; CHECK-BE-NEXT: rev32 v0.8b, v0.8b244; CHECK-BE-NEXT: rev32 v1.8b, v1.8b245; CHECK-BE-NEXT: zip1 v0.2s, v0.2s, v1.2s246; CHECK-BE-NEXT: rev64 v0.2s, v0.2s247; CHECK-BE-NEXT: ret248 %a1 = trunc <8 x i16> %a to <8 x i8>249 %b1 = trunc <8 x i16> %b to <8 x i8>250 251 %a2 = bitcast <8 x i8> %a1 to <2 x i32>252 %b2 = bitcast <8 x i8> %b1 to <2 x i32>253 254 %ab = shufflevector <2 x i32> %a2, <2 x i32> %b2, <2 x i32> <i32 0, i32 2>255 ret <2 x i32> %ab256}257 258define i8 @trunc_v4i64_v4i8(<4 x i64> %input) {259; CHECK-LE-LABEL: trunc_v4i64_v4i8:260; CHECK-LE: // %bb.0:261; CHECK-LE-NEXT: uzp1 v0.4s, v0.4s, v1.4s262; CHECK-LE-NEXT: xtn v0.4h, v0.4s263; CHECK-LE-NEXT: addv h0, v0.4h264; CHECK-LE-NEXT: fmov w0, s0265; CHECK-LE-NEXT: ret266;267; CHECK-BE-LABEL: trunc_v4i64_v4i8:268; CHECK-BE: // %bb.0:269; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8270; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8271; CHECK-BE-NEXT: xtn v1.2s, v1.2d272; CHECK-BE-NEXT: xtn v0.2s, v0.2d273; CHECK-BE-NEXT: uzp1 v0.4h, v0.4h, v1.4h274; CHECK-BE-NEXT: addv h0, v0.4h275; CHECK-BE-NEXT: fmov w0, s0276; CHECK-BE-NEXT: ret277 %var = trunc <4 x i64> %input to <4 x i8>278 ; llvm.vector.reduce.add.v4i8 is needed to reproduce the codegen (see `trunc_v4i64_v4i8_ret` below as a comparison)279 %res = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> %var)280 ret i8 %res281}282 283define <4 x i8> @trunc_v4i64_v4i8_ret(<4 x i64> %input) {284; CHECK-LE-LABEL: trunc_v4i64_v4i8_ret:285; CHECK-LE: // %bb.0:286; CHECK-LE-NEXT: uzp1 v0.4s, v0.4s, v1.4s287; CHECK-LE-NEXT: xtn v0.4h, v0.4s288; CHECK-LE-NEXT: ret289;290; CHECK-BE-LABEL: trunc_v4i64_v4i8_ret:291; CHECK-BE: // %bb.0:292; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8293; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8294; CHECK-BE-NEXT: uzp1 v0.4s, v0.4s, v1.4s295; CHECK-BE-NEXT: xtn v0.4h, v0.4s296; CHECK-BE-NEXT: rev64 v0.4h, v0.4h297; CHECK-BE-NEXT: ret298 %var = trunc <4 x i64> %input to <4 x i8>299 ret <4 x i8> %var300}301 302declare i8 @llvm.vector.reduce.add.v4i8(<4 x i8>)303