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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple aarch64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5; Tests for wider-than-legal extensions into mul/mla.6 7define <16 x i16> @mul_i16(<16 x i8> %a, <16 x i8> %b) {8; CHECK-SD-LABEL: mul_i16:9; CHECK-SD: // %bb.0: // %entry10; CHECK-SD-NEXT: umull2 v2.8h, v0.16b, v1.16b11; CHECK-SD-NEXT: umull v0.8h, v0.8b, v1.8b12; CHECK-SD-NEXT: mov v1.16b, v2.16b13; CHECK-SD-NEXT: ret14;15; CHECK-GI-LABEL: mul_i16:16; CHECK-GI: // %bb.0: // %entry17; CHECK-GI-NEXT: umull v2.8h, v0.8b, v1.8b18; CHECK-GI-NEXT: umull2 v1.8h, v0.16b, v1.16b19; CHECK-GI-NEXT: mov v0.16b, v2.16b20; CHECK-GI-NEXT: ret21entry:22 %ea = zext <16 x i8> %a to <16 x i16>23 %eb = zext <16 x i8> %b to <16 x i16>24 %m = mul <16 x i16> %ea, %eb25 ret <16 x i16> %m26}27 28define <16 x i32> @mul_i32(<16 x i8> %a, <16 x i8> %b) {29; CHECK-SD-LABEL: mul_i32:30; CHECK-SD: // %bb.0: // %entry31; CHECK-SD-NEXT: umull v2.8h, v0.8b, v1.8b32; CHECK-SD-NEXT: umull2 v4.8h, v0.16b, v1.16b33; CHECK-SD-NEXT: ushll v0.4s, v2.4h, #034; CHECK-SD-NEXT: ushll2 v3.4s, v4.8h, #035; CHECK-SD-NEXT: ushll2 v1.4s, v2.8h, #036; CHECK-SD-NEXT: ushll v2.4s, v4.4h, #037; CHECK-SD-NEXT: ret38;39; CHECK-GI-LABEL: mul_i32:40; CHECK-GI: // %bb.0: // %entry41; CHECK-GI-NEXT: umull v2.8h, v0.8b, v1.8b42; CHECK-GI-NEXT: umull2 v3.8h, v0.16b, v1.16b43; CHECK-GI-NEXT: ushll v0.4s, v2.4h, #044; CHECK-GI-NEXT: ushll2 v1.4s, v2.8h, #045; CHECK-GI-NEXT: ushll v2.4s, v3.4h, #046; CHECK-GI-NEXT: ushll2 v3.4s, v3.8h, #047; CHECK-GI-NEXT: ret48entry:49 %ea = zext <16 x i8> %a to <16 x i32>50 %eb = zext <16 x i8> %b to <16 x i32>51 %m = mul <16 x i32> %ea, %eb52 ret <16 x i32> %m53}54 55define <16 x i64> @mul_i64(<16 x i8> %a, <16 x i8> %b) {56; CHECK-SD-LABEL: mul_i64:57; CHECK-SD: // %bb.0: // %entry58; CHECK-SD-NEXT: umull v2.8h, v0.8b, v1.8b59; CHECK-SD-NEXT: umull2 v0.8h, v0.16b, v1.16b60; CHECK-SD-NEXT: ushll v3.4s, v2.4h, #061; CHECK-SD-NEXT: ushll2 v2.4s, v2.8h, #062; CHECK-SD-NEXT: ushll v5.4s, v0.4h, #063; CHECK-SD-NEXT: ushll2 v6.4s, v0.8h, #064; CHECK-SD-NEXT: ushll2 v1.2d, v3.4s, #065; CHECK-SD-NEXT: ushll v0.2d, v3.2s, #066; CHECK-SD-NEXT: ushll2 v3.2d, v2.4s, #067; CHECK-SD-NEXT: ushll v2.2d, v2.2s, #068; CHECK-SD-NEXT: ushll v4.2d, v5.2s, #069; CHECK-SD-NEXT: ushll2 v7.2d, v6.4s, #070; CHECK-SD-NEXT: ushll2 v5.2d, v5.4s, #071; CHECK-SD-NEXT: ushll v6.2d, v6.2s, #072; CHECK-SD-NEXT: ret73;74; CHECK-GI-LABEL: mul_i64:75; CHECK-GI: // %bb.0: // %entry76; CHECK-GI-NEXT: umull v2.8h, v0.8b, v1.8b77; CHECK-GI-NEXT: umull2 v0.8h, v0.16b, v1.16b78; CHECK-GI-NEXT: ushll v1.4s, v2.4h, #079; CHECK-GI-NEXT: ushll2 v3.4s, v2.8h, #080; CHECK-GI-NEXT: ushll v5.4s, v0.4h, #081; CHECK-GI-NEXT: ushll2 v7.4s, v0.8h, #082; CHECK-GI-NEXT: ushll v0.2d, v1.2s, #083; CHECK-GI-NEXT: ushll2 v1.2d, v1.4s, #084; CHECK-GI-NEXT: ushll v2.2d, v3.2s, #085; CHECK-GI-NEXT: ushll2 v3.2d, v3.4s, #086; CHECK-GI-NEXT: ushll v4.2d, v5.2s, #087; CHECK-GI-NEXT: ushll2 v5.2d, v5.4s, #088; CHECK-GI-NEXT: ushll v6.2d, v7.2s, #089; CHECK-GI-NEXT: ushll2 v7.2d, v7.4s, #090; CHECK-GI-NEXT: ret91entry:92 %ea = zext <16 x i8> %a to <16 x i64>93 %eb = zext <16 x i8> %b to <16 x i64>94 %m = mul <16 x i64> %ea, %eb95 ret <16 x i64> %m96}97 98 99define <16 x i16> @mla_i16(<16 x i8> %a, <16 x i8> %b, <16 x i16> %c) {100; CHECK-SD-LABEL: mla_i16:101; CHECK-SD: // %bb.0: // %entry102; CHECK-SD-NEXT: umlal2 v3.8h, v0.16b, v1.16b103; CHECK-SD-NEXT: umlal v2.8h, v0.8b, v1.8b104; CHECK-SD-NEXT: mov v0.16b, v2.16b105; CHECK-SD-NEXT: mov v1.16b, v3.16b106; CHECK-SD-NEXT: ret107;108; CHECK-GI-LABEL: mla_i16:109; CHECK-GI: // %bb.0: // %entry110; CHECK-GI-NEXT: umlal v2.8h, v0.8b, v1.8b111; CHECK-GI-NEXT: umlal2 v3.8h, v0.16b, v1.16b112; CHECK-GI-NEXT: mov v0.16b, v2.16b113; CHECK-GI-NEXT: mov v1.16b, v3.16b114; CHECK-GI-NEXT: ret115entry:116 %ea = zext <16 x i8> %a to <16 x i16>117 %eb = zext <16 x i8> %b to <16 x i16>118 %m = mul <16 x i16> %ea, %eb119 %d = add <16 x i16> %m, %c120 ret <16 x i16> %d121}122 123define <16 x i32> @mla_i32(<16 x i8> %a, <16 x i8> %b, <16 x i32> %c) {124; CHECK-SD-LABEL: mla_i32:125; CHECK-SD: // %bb.0: // %entry126; CHECK-SD-NEXT: umull2 v7.8h, v0.16b, v1.16b127; CHECK-SD-NEXT: umull v6.8h, v0.8b, v1.8b128; CHECK-SD-NEXT: uaddw2 v5.4s, v5.4s, v7.8h129; CHECK-SD-NEXT: uaddw v0.4s, v2.4s, v6.4h130; CHECK-SD-NEXT: uaddw2 v1.4s, v3.4s, v6.8h131; CHECK-SD-NEXT: uaddw v2.4s, v4.4s, v7.4h132; CHECK-SD-NEXT: mov v3.16b, v5.16b133; CHECK-SD-NEXT: ret134;135; CHECK-GI-LABEL: mla_i32:136; CHECK-GI: // %bb.0: // %entry137; CHECK-GI-NEXT: umull v6.8h, v0.8b, v1.8b138; CHECK-GI-NEXT: umull2 v7.8h, v0.16b, v1.16b139; CHECK-GI-NEXT: uaddw v0.4s, v2.4s, v6.4h140; CHECK-GI-NEXT: uaddw2 v1.4s, v3.4s, v6.8h141; CHECK-GI-NEXT: uaddw v2.4s, v4.4s, v7.4h142; CHECK-GI-NEXT: uaddw2 v3.4s, v5.4s, v7.8h143; CHECK-GI-NEXT: ret144entry:145 %ea = zext <16 x i8> %a to <16 x i32>146 %eb = zext <16 x i8> %b to <16 x i32>147 %m = mul <16 x i32> %ea, %eb148 %d = add <16 x i32> %m, %c149 ret <16 x i32> %d150}151 152define <16 x i64> @mla_i64(<16 x i8> %a, <16 x i8> %b, <16 x i64> %c) {153; CHECK-SD-LABEL: mla_i64:154; CHECK-SD: // %bb.0: // %entry155; CHECK-SD-NEXT: umull v16.8h, v0.8b, v1.8b156; CHECK-SD-NEXT: umull2 v0.8h, v0.16b, v1.16b157; CHECK-SD-NEXT: ldp q20, q21, [sp]158; CHECK-SD-NEXT: ushll v17.4s, v16.4h, #0159; CHECK-SD-NEXT: ushll2 v16.4s, v16.8h, #0160; CHECK-SD-NEXT: ushll2 v19.4s, v0.8h, #0161; CHECK-SD-NEXT: ushll v18.4s, v0.4h, #0162; CHECK-SD-NEXT: uaddw2 v1.2d, v3.2d, v17.4s163; CHECK-SD-NEXT: uaddw v0.2d, v2.2d, v17.2s164; CHECK-SD-NEXT: uaddw2 v3.2d, v5.2d, v16.4s165; CHECK-SD-NEXT: uaddw v2.2d, v4.2d, v16.2s166; CHECK-SD-NEXT: uaddw2 v16.2d, v21.2d, v19.4s167; CHECK-SD-NEXT: uaddw v4.2d, v6.2d, v18.2s168; CHECK-SD-NEXT: uaddw2 v5.2d, v7.2d, v18.4s169; CHECK-SD-NEXT: uaddw v6.2d, v20.2d, v19.2s170; CHECK-SD-NEXT: mov v7.16b, v16.16b171; CHECK-SD-NEXT: ret172;173; CHECK-GI-LABEL: mla_i64:174; CHECK-GI: // %bb.0: // %entry175; CHECK-GI-NEXT: umull v16.8h, v0.8b, v1.8b176; CHECK-GI-NEXT: umull2 v0.8h, v0.16b, v1.16b177; CHECK-GI-NEXT: ldp q19, q20, [sp]178; CHECK-GI-NEXT: ushll v1.4s, v16.4h, #0179; CHECK-GI-NEXT: ushll2 v16.4s, v16.8h, #0180; CHECK-GI-NEXT: ushll v17.4s, v0.4h, #0181; CHECK-GI-NEXT: ushll2 v18.4s, v0.8h, #0182; CHECK-GI-NEXT: uaddw v0.2d, v2.2d, v1.2s183; CHECK-GI-NEXT: uaddw2 v1.2d, v3.2d, v1.4s184; CHECK-GI-NEXT: uaddw v2.2d, v4.2d, v16.2s185; CHECK-GI-NEXT: uaddw2 v3.2d, v5.2d, v16.4s186; CHECK-GI-NEXT: uaddw v4.2d, v6.2d, v17.2s187; CHECK-GI-NEXT: uaddw2 v5.2d, v7.2d, v17.4s188; CHECK-GI-NEXT: uaddw v6.2d, v19.2d, v18.2s189; CHECK-GI-NEXT: uaddw2 v7.2d, v20.2d, v18.4s190; CHECK-GI-NEXT: ret191entry:192 %ea = zext <16 x i8> %a to <16 x i64>193 %eb = zext <16 x i8> %b to <16 x i64>194 %m = mul <16 x i64> %ea, %eb195 %d = add <16 x i64> %m, %c196 ret <16 x i64> %d197}198;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:199; CHECK: {{.*}}200