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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s | FileCheck %s3 4target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"5target triple = "aarch64-unknown-linux-gnu"6 7define <4 x i16> @f(<4 x i32> %vqdmlal_v3.i, <8 x i16> %x5) {8; CHECK-LABEL: f:9; CHECK: // %bb.0: // %entry10; CHECK-NEXT: dup v0.4h, v0.h[4]11; CHECK-NEXT: mov v0.h[1], v1.h[0]12; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q013; CHECK-NEXT: ret14entry:15 ; Check that we don't just dup the input vector. The code emitted is ext, dup, ext, ext16 ; but only match the last three instructions as the first two could be combined to17 ; a dup2 at some stage.18 %x4 = extractelement <4 x i32> %vqdmlal_v3.i, i32 219 %vgetq_lane = trunc i32 %x4 to i1620 %vecinit.i = insertelement <4 x i16> undef, i16 %vgetq_lane, i32 021 %vecinit2.i = insertelement <4 x i16> %vecinit.i, i16 %vgetq_lane, i32 222 %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vgetq_lane, i32 323 %vgetq_lane261 = extractelement <8 x i16> %x5, i32 024 %vset_lane267 = insertelement <4 x i16> %vecinit3.i, i16 %vgetq_lane261, i32 125 ret <4 x i16> %vset_lane26726}27