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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64 | FileCheck %s3 4define <8 x i16> @abdu_base(<8 x i16> %src1, <8 x i16> %src2) {5; CHECK-LABEL: abdu_base:6; CHECK: // %bb.0:7; CHECK-NEXT: uabd v0.8h, v0.8h, v1.8h8; CHECK-NEXT: ret9 %zextsrc1 = zext <8 x i16> %src1 to <8 x i32>10 %zextsrc2 = zext <8 x i16> %src2 to <8 x i32>11 %sub = sub <8 x i32> %zextsrc1, %zextsrc212 %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 0)13 %result = trunc <8 x i32> %abs to <8 x i16>14 ret <8 x i16> %result15}16 17define <8 x i16> @abdu_const(<8 x i16> %src1) {18; CHECK-LABEL: abdu_const:19; CHECK: // %bb.0:20; CHECK-NEXT: movi v1.4h, #121; CHECK-NEXT: mov v1.d[1], v1.d[0]22; CHECK-NEXT: uabd v0.8h, v0.8h, v1.8h23; CHECK-NEXT: ret24 %zextsrc1 = zext <8 x i16> %src1 to <8 x i32>25 %sub = sub <8 x i32> %zextsrc1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>26 %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 0)27 %result = trunc <8 x i32> %abs to <8 x i16>28 ret <8 x i16> %result29}30 31define <8 x i16> @abdu_const_lhs(<8 x i16> %src1) {32; CHECK-LABEL: abdu_const_lhs:33; CHECK: // %bb.0:34; CHECK-NEXT: movi v1.4h, #135; CHECK-NEXT: mov v1.d[1], v1.d[0]36; CHECK-NEXT: uabd v0.8h, v0.8h, v1.8h37; CHECK-NEXT: ret38 %zextsrc1 = zext <8 x i16> %src1 to <8 x i32>39 %sub = sub <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, %zextsrc140 %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 0)41 %result = trunc <8 x i32> %abs to <8 x i16>42 ret <8 x i16> %result43}44 45define <8 x i16> @abdu_const_zero(<8 x i16> %src1) {46; CHECK-LABEL: abdu_const_zero:47; CHECK: // %bb.0:48; CHECK-NEXT: ret49 %zextsrc1 = zext <8 x i16> %src1 to <8 x i32>50 %sub = sub <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, %zextsrc151 %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 0)52 %result = trunc <8 x i32> %abs to <8 x i16>53 ret <8 x i16> %result54}55 56define <8 x i16> @abdu_const_both() {57; CHECK-LABEL: abdu_const_both:58; CHECK: // %bb.0:59; CHECK-NEXT: movi v0.8h, #260; CHECK-NEXT: ret61 %sub = sub <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>62 %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 0)63 %result = trunc <8 x i32> %abs to <8 x i16>64 ret <8 x i16> %result65}66 67define <8 x i16> @abdu_const_bothhigh() {68; CHECK-LABEL: abdu_const_bothhigh:69; CHECK: // %bb.0:70; CHECK-NEXT: movi v0.8h, #171; CHECK-NEXT: ret72 %zextsrc1 = zext <8 x i16> <i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534> to <8 x i32>73 %zextsrc2 = zext <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535> to <8 x i32>74 %sub = sub <8 x i32> %zextsrc1, %zextsrc275 %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 0)76 %result = trunc <8 x i32> %abs to <8 x i16>77 ret <8 x i16> %result78}79 80define <8 x i16> @abdu_undef(<8 x i16> %src1) {81; CHECK-LABEL: abdu_undef:82; CHECK: // %bb.0:83; CHECK-NEXT: ret84 %zextsrc1 = zext <8 x i16> %src1 to <8 x i32>85 %zextsrc2 = zext <8 x i16> undef to <8 x i32>86 %sub = sub <8 x i32> %zextsrc1, %zextsrc287 %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 0)88 %result = trunc <8 x i32> %abs to <8 x i16>89 ret <8 x i16> %result90}91 92define <8 x i16> @abdu_ugt(<8 x i16>, <8 x i16>) {93; CHECK-LABEL: abdu_ugt:94; CHECK: // %bb.0:95; CHECK-NEXT: uabd v0.8h, v0.8h, v1.8h96; CHECK-NEXT: ret97 %3 = icmp ugt <8 x i16> %0, %198 %4 = sub <8 x i16> %0, %199 %5 = sub <8 x i16> %1, %0100 %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5101 ret <8 x i16> %6102}103 104define <8 x i16> @abdu_uge(<8 x i16>, <8 x i16>) {105; CHECK-LABEL: abdu_uge:106; CHECK: // %bb.0:107; CHECK-NEXT: uabd v0.8h, v0.8h, v1.8h108; CHECK-NEXT: ret109 %3 = icmp uge <8 x i16> %0, %1110 %4 = sub <8 x i16> %0, %1111 %5 = sub <8 x i16> %1, %0112 %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5113 ret <8 x i16> %6114}115 116define <8 x i16> @abdu_ult(<8 x i16>, <8 x i16>) {117; CHECK-LABEL: abdu_ult:118; CHECK: // %bb.0:119; CHECK-NEXT: uabd v0.8h, v0.8h, v1.8h120; CHECK-NEXT: ret121 %3 = icmp ult <8 x i16> %0, %1122 %4 = sub <8 x i16> %0, %1123 %5 = sub <8 x i16> %1, %0124 %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4125 ret <8 x i16> %6126}127 128define <8 x i16> @abdu_ule(<8 x i16>, <8 x i16>) {129; CHECK-LABEL: abdu_ule:130; CHECK: // %bb.0:131; CHECK-NEXT: uabd v0.8h, v0.8h, v1.8h132; CHECK-NEXT: ret133 %3 = icmp ule <8 x i16> %0, %1134 %4 = sub <8 x i16> %0, %1135 %5 = sub <8 x i16> %1, %0136 %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4137 ret <8 x i16> %6138}139 140define <8 x i16> @abds_sgt(<8 x i16>, <8 x i16>) {141; CHECK-LABEL: abds_sgt:142; CHECK: // %bb.0:143; CHECK-NEXT: sabd v0.8h, v0.8h, v1.8h144; CHECK-NEXT: ret145 %3 = icmp sgt <8 x i16> %0, %1146 %4 = sub <8 x i16> %0, %1147 %5 = sub <8 x i16> %1, %0148 %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5149 ret <8 x i16> %6150}151 152define <8 x i16> @abds_sge(<8 x i16>, <8 x i16>) {153; CHECK-LABEL: abds_sge:154; CHECK: // %bb.0:155; CHECK-NEXT: sabd v0.8h, v0.8h, v1.8h156; CHECK-NEXT: ret157 %3 = icmp sge <8 x i16> %0, %1158 %4 = sub <8 x i16> %0, %1159 %5 = sub <8 x i16> %1, %0160 %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5161 ret <8 x i16> %6162}163 164define <8 x i16> @abds_slt(<8 x i16>, <8 x i16>) {165; CHECK-LABEL: abds_slt:166; CHECK: // %bb.0:167; CHECK-NEXT: sabd v0.8h, v0.8h, v1.8h168; CHECK-NEXT: ret169 %3 = icmp slt <8 x i16> %0, %1170 %4 = sub <8 x i16> %0, %1171 %5 = sub <8 x i16> %1, %0172 %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4173 ret <8 x i16> %6174}175 176define <8 x i16> @abds_sle(<8 x i16>, <8 x i16>) {177; CHECK-LABEL: abds_sle:178; CHECK: // %bb.0:179; CHECK-NEXT: sabd v0.8h, v0.8h, v1.8h180; CHECK-NEXT: ret181 %3 = icmp sle <8 x i16> %0, %1182 %4 = sub <8 x i16> %0, %1183 %5 = sub <8 x i16> %1, %0184 %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4185 ret <8 x i16> %6186}187 188 189define <8 x i16> @abdu_i_base(<8 x i16> %src1, <8 x i16> %src2) {190; CHECK-LABEL: abdu_i_base:191; CHECK: // %bb.0:192; CHECK-NEXT: uabd v0.8h, v0.8h, v1.8h193; CHECK-NEXT: ret194 %result = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> %src1, <8 x i16> %src2)195 ret <8 x i16> %result196}197 198define <8 x i16> @abdu_i_const(<8 x i16> %src1) {199; CHECK-LABEL: abdu_i_const:200; CHECK: // %bb.0:201; CHECK-NEXT: movi v1.8h, #1202; CHECK-NEXT: uabd v0.8h, v0.8h, v1.8h203; CHECK-NEXT: ret204 %result = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> %src1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)205 ret <8 x i16> %result206}207 208define <8 x i16> @abdu_i_const_lhs(<8 x i16> %src1) {209; CHECK-LABEL: abdu_i_const_lhs:210; CHECK: // %bb.0:211; CHECK-NEXT: movi v1.8h, #1212; CHECK-NEXT: uabd v0.8h, v0.8h, v1.8h213; CHECK-NEXT: ret214 %result = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <8 x i16> %src1)215 ret <8 x i16> %result216}217 218define <8 x i16> @abdu_i_const_zero(float %t, <8 x i16> %src1) {219; CHECK-LABEL: abdu_i_const_zero:220; CHECK: // %bb.0:221; CHECK-NEXT: mov v0.16b, v1.16b222; CHECK-NEXT: ret223 %result = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, <8 x i16> %src1)224 ret <8 x i16> %result225}226 227define <8 x i16> @abdu_i_const_both() {228; CHECK-LABEL: abdu_i_const_both:229; CHECK: // %bb.0:230; CHECK-NEXT: movi v0.8h, #2231; CHECK-NEXT: ret232 %result = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)233 ret <8 x i16> %result234}235 236define <8 x i16> @abdu_i_const_bothhigh() {237; CHECK-LABEL: abdu_i_const_bothhigh:238; CHECK: // %bb.0:239; CHECK-NEXT: movi v0.8h, #1240; CHECK-NEXT: ret241 %result = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> <i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534>, <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535>)242 ret <8 x i16> %result243}244 245define <8 x i16> @abdu_i_const_onehigh() {246; CHECK-LABEL: abdu_i_const_onehigh:247; CHECK: // %bb.0:248; CHECK-NEXT: mov w8, #32765 // =0x7ffd249; CHECK-NEXT: dup v0.8h, w8250; CHECK-NEXT: ret251 %result = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766>, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)252 ret <8 x i16> %result253}254 255define <8 x i16> @abdu_i_const_oneneg() {256; CHECK-LABEL: abdu_i_const_oneneg:257; CHECK: // %bb.0:258; CHECK-NEXT: movi v0.8h, #128, lsl #8259; CHECK-NEXT: ret260 %result = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766>, <8 x i16> <i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534>)261 ret <8 x i16> %result262}263 264define <8 x i16> @abdu_i_zero(<8 x i16> %t, <8 x i16> %src1) {265; CHECK-LABEL: abdu_i_zero:266; CHECK: // %bb.0:267; CHECK-NEXT: mov v0.16b, v1.16b268; CHECK-NEXT: ret269 %result = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, <8 x i16> %src1)270 ret <8 x i16> %result271}272 273define <8 x i16> @abdu_i_undef(<8 x i16> %t, <8 x i16> %src1) {274; CHECK-LABEL: abdu_i_undef:275; CHECK: // %bb.0:276; CHECK-NEXT: movi v0.2d, #0000000000000000277; CHECK-NEXT: ret278 %result = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> undef, <8 x i16> %src1)279 ret <8 x i16> %result280}281 282define <8 x i16> @abdu_i_reassoc(<8 x i16> %src1) {283; CHECK-LABEL: abdu_i_reassoc:284; CHECK: // %bb.0:285; CHECK-NEXT: movi v1.8h, #3286; CHECK-NEXT: movi v2.8h, #1287; CHECK-NEXT: uabd v0.8h, v0.8h, v1.8h288; CHECK-NEXT: uabd v0.8h, v0.8h, v2.8h289; CHECK-NEXT: ret290 %r1 = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> %src1, <8 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>)291 %result = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> %r1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)292 ret <8 x i16> %result293}294 295 296 297 298 299define <8 x i16> @abds_base(<8 x i16> %src1, <8 x i16> %src2) {300; CHECK-LABEL: abds_base:301; CHECK: // %bb.0:302; CHECK-NEXT: sabd v0.8h, v0.8h, v1.8h303; CHECK-NEXT: ret304 %zextsrc1 = sext <8 x i16> %src1 to <8 x i32>305 %zextsrc2 = sext <8 x i16> %src2 to <8 x i32>306 %sub = sub <8 x i32> %zextsrc1, %zextsrc2307 %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 0)308 %result = trunc <8 x i32> %abs to <8 x i16>309 ret <8 x i16> %result310}311 312define <8 x i16> @abds_const(<8 x i16> %src1) {313; CHECK-LABEL: abds_const:314; CHECK: // %bb.0:315; CHECK-NEXT: movi v1.4h, #1316; CHECK-NEXT: mov v1.d[1], v1.d[0]317; CHECK-NEXT: sabd v0.8h, v0.8h, v1.8h318; CHECK-NEXT: ret319 %zextsrc1 = sext <8 x i16> %src1 to <8 x i32>320 %sub = sub <8 x i32> %zextsrc1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>321 %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 0)322 %result = trunc <8 x i32> %abs to <8 x i16>323 ret <8 x i16> %result324}325 326define <8 x i16> @abds_const_lhs(<8 x i16> %src1) {327; CHECK-LABEL: abds_const_lhs:328; CHECK: // %bb.0:329; CHECK-NEXT: movi v1.4h, #1330; CHECK-NEXT: mov v1.d[1], v1.d[0]331; CHECK-NEXT: sabd v0.8h, v0.8h, v1.8h332; CHECK-NEXT: ret333 %zextsrc1 = sext <8 x i16> %src1 to <8 x i32>334 %sub = sub <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, %zextsrc1335 %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 0)336 %result = trunc <8 x i32> %abs to <8 x i16>337 ret <8 x i16> %result338}339 340define <8 x i16> @abds_const_zero(<8 x i16> %src1) {341; CHECK-LABEL: abds_const_zero:342; CHECK: // %bb.0:343; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8344; CHECK-NEXT: abs v0.4h, v0.4h345; CHECK-NEXT: abs v1.4h, v1.4h346; CHECK-NEXT: mov v0.d[1], v1.d[0]347; CHECK-NEXT: ret348 %zextsrc1 = sext <8 x i16> %src1 to <8 x i32>349 %sub = sub <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, %zextsrc1350 %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 0)351 %result = trunc <8 x i32> %abs to <8 x i16>352 ret <8 x i16> %result353}354 355define <8 x i16> @abds_const_both() {356; CHECK-LABEL: abds_const_both:357; CHECK: // %bb.0:358; CHECK-NEXT: movi v0.8h, #2359; CHECK-NEXT: ret360 %sub = sub <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>361 %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 0)362 %result = trunc <8 x i32> %abs to <8 x i16>363 ret <8 x i16> %result364}365 366define <8 x i16> @abds_const_bothhigh() {367; CHECK-LABEL: abds_const_bothhigh:368; CHECK: // %bb.0:369; CHECK-NEXT: movi v0.8h, #1370; CHECK-NEXT: ret371 %zextsrc1 = sext <8 x i16> <i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534> to <8 x i32>372 %zextsrc2 = sext <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535> to <8 x i32>373 %sub = sub <8 x i32> %zextsrc1, %zextsrc2374 %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 0)375 %result = trunc <8 x i32> %abs to <8 x i16>376 ret <8 x i16> %result377}378 379define <8 x i16> @abds_undef(<8 x i16> %src1) {380; CHECK-LABEL: abds_undef:381; CHECK: // %bb.0:382; CHECK-NEXT: sshll v1.4s, v0.4h, #0383; CHECK-NEXT: sshll2 v0.4s, v0.8h, #0384; CHECK-NEXT: abs v0.4s, v0.4s385; CHECK-NEXT: abs v1.4s, v1.4s386; CHECK-NEXT: uzp1 v0.8h, v1.8h, v0.8h387; CHECK-NEXT: ret388 %zextsrc1 = sext <8 x i16> %src1 to <8 x i32>389 %zextsrc2 = sext <8 x i16> undef to <8 x i32>390 %sub = sub <8 x i32> %zextsrc1, %zextsrc2391 %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 0)392 %result = trunc <8 x i32> %abs to <8 x i16>393 ret <8 x i16> %result394}395 396 397 398define <8 x i16> @abds_i_base(<8 x i16> %src1, <8 x i16> %src2) {399; CHECK-LABEL: abds_i_base:400; CHECK: // %bb.0:401; CHECK-NEXT: sabd v0.8h, v0.8h, v1.8h402; CHECK-NEXT: ret403 %result = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> %src1, <8 x i16> %src2)404 ret <8 x i16> %result405}406 407define <8 x i16> @abds_i_const(<8 x i16> %src1) {408; CHECK-LABEL: abds_i_const:409; CHECK: // %bb.0:410; CHECK-NEXT: movi v1.8h, #1411; CHECK-NEXT: sabd v0.8h, v0.8h, v1.8h412; CHECK-NEXT: ret413 %result = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> %src1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)414 ret <8 x i16> %result415}416 417define <8 x i16> @abds_i_const_lhs(<8 x i16> %src1) {418; CHECK-LABEL: abds_i_const_lhs:419; CHECK: // %bb.0:420; CHECK-NEXT: movi v1.8h, #1421; CHECK-NEXT: sabd v0.8h, v0.8h, v1.8h422; CHECK-NEXT: ret423 %result = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <8 x i16> %src1)424 ret <8 x i16> %result425}426 427define <8 x i16> @abds_i_const_zero(<8 x i16> %src1) {428; CHECK-LABEL: abds_i_const_zero:429; CHECK: // %bb.0:430; CHECK-NEXT: abs v0.8h, v0.8h431; CHECK-NEXT: ret432 %result = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, <8 x i16> %src1)433 ret <8 x i16> %result434}435 436define <8 x i16> @abds_i_const_both() {437; CHECK-LABEL: abds_i_const_both:438; CHECK: // %bb.0:439; CHECK-NEXT: movi v0.8h, #2440; CHECK-NEXT: ret441 %result = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)442 ret <8 x i16> %result443}444 445define <8 x i16> @abds_i_const_bothhigh() {446; CHECK-LABEL: abds_i_const_bothhigh:447; CHECK: // %bb.0:448; CHECK-NEXT: movi v0.8h, #1449; CHECK-NEXT: ret450 %result = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766>, <8 x i16> <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767>)451 ret <8 x i16> %result452}453 454define <8 x i16> @abds_i_const_onehigh() {455; CHECK-LABEL: abds_i_const_onehigh:456; CHECK: // %bb.0:457; CHECK-NEXT: mov w8, #32765 // =0x7ffd458; CHECK-NEXT: dup v0.8h, w8459; CHECK-NEXT: ret460 %result = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766>, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)461 ret <8 x i16> %result462}463 464define <8 x i16> @abds_i_const_oneneg() {465; CHECK-LABEL: abds_i_const_oneneg:466; CHECK: // %bb.0:467; CHECK-NEXT: movi v0.8h, #128, lsl #8468; CHECK-NEXT: ret469 %result = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766>, <8 x i16> <i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534>)470 ret <8 x i16> %result471}472 473define <8 x i16> @abds_i_zero(<8 x i16> %t, <8 x i16> %src1) {474; CHECK-LABEL: abds_i_zero:475; CHECK: // %bb.0:476; CHECK-NEXT: abs v0.8h, v1.8h477; CHECK-NEXT: ret478 %result = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, <8 x i16> %src1)479 ret <8 x i16> %result480}481 482define <8 x i16> @abds_i_undef(<8 x i16> %t, <8 x i16> %src1) {483; CHECK-LABEL: abds_i_undef:484; CHECK: // %bb.0:485; CHECK-NEXT: movi v0.2d, #0000000000000000486; CHECK-NEXT: ret487 %result = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> undef, <8 x i16> %src1)488 ret <8 x i16> %result489}490 491define <8 x i16> @abds_i_reassoc(<8 x i16> %src1) {492; CHECK-LABEL: abds_i_reassoc:493; CHECK: // %bb.0:494; CHECK-NEXT: movi v1.8h, #3495; CHECK-NEXT: movi v2.8h, #1496; CHECK-NEXT: sabd v0.8h, v0.8h, v1.8h497; CHECK-NEXT: sabd v0.8h, v0.8h, v2.8h498; CHECK-NEXT: ret499 %r1 = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> %src1, <8 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>)500 %result = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> %r1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)501 ret <8 x i16> %result502}503 504define <1 x i64> @recursive() {505; CHECK-LABEL: recursive:506; CHECK: // %bb.0:507; CHECK-NEXT: movi v0.8b, #254508; CHECK-NEXT: ushll v1.8h, v0.8b, #0509; CHECK-NEXT: dup v0.8b, v0.b[0]510; CHECK-NEXT: saddlp v1.1d, v1.2s511; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b512; CHECK-NEXT: ret513 %1 = tail call <8 x i8> @llvm.aarch64.neon.umax.v8i8(<8 x i8> zeroinitializer, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)514 %2 = tail call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %1, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)515 %3 = zext <8 x i8> %2 to <8 x i16>516 %4 = bitcast <8 x i16> %3 to <4 x i32>517 %5 = shufflevector <4 x i32> %4, <4 x i32> zeroinitializer, <2 x i32> <i32 0, i32 1>518 %6 = shufflevector <8 x i8> %2, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>519 %7 = bitcast <16 x i8> %6 to <2 x i64>520 %8 = shufflevector <2 x i64> %7, <2 x i64> zeroinitializer, <1 x i32> zeroinitializer521 %9 = tail call <1 x i64> @llvm.aarch64.neon.saddlp.v1i64.v2i32(<2 x i32> %5)522 %10 = or <1 x i64> %8, %9523 ret <1 x i64> %10524}525 526declare <8 x i8> @llvm.aarch64.neon.umax.v8i8(<8 x i8>, <8 x i8>)527declare <1 x i64> @llvm.aarch64.neon.saddlp.v1i64.v2i32(<2 x i32>)528declare <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8>, <8 x i8>)529declare <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16>, <8 x i16>)530declare <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16>, <8 x i16>)531declare <8 x i32> @llvm.abs.v8i32(<8 x i32>, i1)532