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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5; ===== Legal Scalars =====6 7define i8 @abs_i8(i8 %a){8; CHECK-SD-LABEL: abs_i8:9; CHECK-SD: // %bb.0: // %entry10; CHECK-SD-NEXT: sxtb w8, w011; CHECK-SD-NEXT: cmp w8, #012; CHECK-SD-NEXT: cneg w0, w8, mi13; CHECK-SD-NEXT: ret14;15; CHECK-GI-LABEL: abs_i8:16; CHECK-GI: // %bb.0: // %entry17; CHECK-GI-NEXT: sxtb w8, w018; CHECK-GI-NEXT: cmp w8, #019; CHECK-GI-NEXT: cneg w0, w0, le20; CHECK-GI-NEXT: ret21entry:22 %res = call i8 @llvm.abs.i8(i8 %a, i1 0)23 ret i8 %res24}25declare i8 @llvm.abs.i8(i8, i1)26 27define i16 @abs_i16(i16 %a){28; CHECK-SD-LABEL: abs_i16:29; CHECK-SD: // %bb.0: // %entry30; CHECK-SD-NEXT: sxth w8, w031; CHECK-SD-NEXT: cmp w8, #032; CHECK-SD-NEXT: cneg w0, w8, mi33; CHECK-SD-NEXT: ret34;35; CHECK-GI-LABEL: abs_i16:36; CHECK-GI: // %bb.0: // %entry37; CHECK-GI-NEXT: sxth w8, w038; CHECK-GI-NEXT: cmp w8, #039; CHECK-GI-NEXT: cneg w0, w0, le40; CHECK-GI-NEXT: ret41entry:42 %res = call i16 @llvm.abs.i16(i16 %a, i1 0)43 ret i16 %res44}45declare i16 @llvm.abs.i16(i16, i1)46 47define i32 @abs_i32(i32 %a){48; CHECK-SD-LABEL: abs_i32:49; CHECK-SD: // %bb.0: // %entry50; CHECK-SD-NEXT: cmp w0, #051; CHECK-SD-NEXT: cneg w0, w0, mi52; CHECK-SD-NEXT: ret53;54; CHECK-GI-LABEL: abs_i32:55; CHECK-GI: // %bb.0: // %entry56; CHECK-GI-NEXT: cmp w0, #057; CHECK-GI-NEXT: cneg w0, w0, le58; CHECK-GI-NEXT: ret59entry:60 %res = call i32 @llvm.abs.i32(i32 %a, i1 0)61 ret i32 %res62}63declare i32 @llvm.abs.i32(i32, i1)64 65define i64 @abs_i64(i64 %a){66; CHECK-SD-LABEL: abs_i64:67; CHECK-SD: // %bb.0: // %entry68; CHECK-SD-NEXT: cmp x0, #069; CHECK-SD-NEXT: cneg x0, x0, mi70; CHECK-SD-NEXT: ret71;72; CHECK-GI-LABEL: abs_i64:73; CHECK-GI: // %bb.0: // %entry74; CHECK-GI-NEXT: cmp x0, #075; CHECK-GI-NEXT: cneg x0, x0, le76; CHECK-GI-NEXT: ret77entry:78 %res = call i64 @llvm.abs.i64(i64 %a, i1 0)79 ret i64 %res80}81declare i64 @llvm.abs.i64(i64, i1)82 83define i128 @abs_i128(i128 %a){84; CHECK-SD-LABEL: abs_i128:85; CHECK-SD: // %bb.0: // %entry86; CHECK-SD-NEXT: asr x8, x1, #6387; CHECK-SD-NEXT: eor x9, x0, x888; CHECK-SD-NEXT: eor x10, x1, x889; CHECK-SD-NEXT: subs x0, x9, x890; CHECK-SD-NEXT: sbc x1, x10, x891; CHECK-SD-NEXT: ret92;93; CHECK-GI-LABEL: abs_i128:94; CHECK-GI: // %bb.0: // %entry95; CHECK-GI-NEXT: asr x8, x1, #6396; CHECK-GI-NEXT: adds x9, x0, x897; CHECK-GI-NEXT: adc x10, x1, x898; CHECK-GI-NEXT: eor x0, x9, x899; CHECK-GI-NEXT: eor x1, x10, x8100; CHECK-GI-NEXT: ret101entry:102 %res = call i128 @llvm.abs.i128(i128 %a, i1 0)103 ret i128 %res104}105declare i128 @llvm.abs.i128(i128, i1)106 107; ===== Legal Vector Types =====108 109define <8 x i8> @abs_v8i8(<8 x i8> %a){110; CHECK-LABEL: abs_v8i8:111; CHECK: // %bb.0: // %entry112; CHECK-NEXT: abs v0.8b, v0.8b113; CHECK-NEXT: ret114entry:115 %res = call <8 x i8> @llvm.abs.v8i8(<8 x i8> %a, i1 0)116 ret <8 x i8> %res117}118declare <8 x i8> @llvm.abs.v8i8(<8 x i8>, i1)119 120define <16 x i8> @abs_v16i8(<16 x i8> %a){121; CHECK-LABEL: abs_v16i8:122; CHECK: // %bb.0: // %entry123; CHECK-NEXT: abs v0.16b, v0.16b124; CHECK-NEXT: ret125entry:126 %res = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %a, i1 0)127 ret <16 x i8> %res128}129declare <16 x i8> @llvm.abs.v16i8(<16 x i8>, i1)130 131define <4 x i16> @abs_v4i16(<4 x i16> %a){132; CHECK-LABEL: abs_v4i16:133; CHECK: // %bb.0: // %entry134; CHECK-NEXT: abs v0.4h, v0.4h135; CHECK-NEXT: ret136entry:137 %res = call <4 x i16> @llvm.abs.v4i16(<4 x i16> %a, i1 0)138 ret <4 x i16> %res139}140declare <4 x i16> @llvm.abs.v4i16(<4 x i16>, i1)141 142define <8 x i16> @abs_v8i16(<8 x i16> %a){143; CHECK-LABEL: abs_v8i16:144; CHECK: // %bb.0: // %entry145; CHECK-NEXT: abs v0.8h, v0.8h146; CHECK-NEXT: ret147entry:148 %res = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a, i1 0)149 ret <8 x i16> %res150}151declare <8 x i16> @llvm.abs.v8i16(<8 x i16>, i1)152 153define <2 x i32> @abs_v2i32(<2 x i32> %a){154; CHECK-LABEL: abs_v2i32:155; CHECK: // %bb.0: // %entry156; CHECK-NEXT: abs v0.2s, v0.2s157; CHECK-NEXT: ret158entry:159 %res = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %a, i1 0)160 ret <2 x i32> %res161}162declare <2 x i32> @llvm.abs.v2i32(<2 x i32>, i1)163 164define <4 x i32> @abs_v4i32(<4 x i32> %a){165; CHECK-LABEL: abs_v4i32:166; CHECK: // %bb.0: // %entry167; CHECK-NEXT: abs v0.4s, v0.4s168; CHECK-NEXT: ret169entry:170 %res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a, i1 0)171 ret <4 x i32> %res172}173declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)174 175define <2 x i64> @abs_v2i64(<2 x i64> %a){176; CHECK-LABEL: abs_v2i64:177; CHECK: // %bb.0: // %entry178; CHECK-NEXT: abs v0.2d, v0.2d179; CHECK-NEXT: ret180entry:181 %res = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a, i1 0)182 ret <2 x i64> %res183}184declare <2 x i64> @llvm.abs.v2i64(<2 x i64>, i1)185 186; ===== Smaller/Larger Width Vectors with Legal Element Sizes =====187 188define <4 x i8> @abs_v4i8(<4 x i8> %a){189; CHECK-LABEL: abs_v4i8:190; CHECK: // %bb.0: // %entry191; CHECK-NEXT: shl v0.4h, v0.4h, #8192; CHECK-NEXT: sshr v0.4h, v0.4h, #8193; CHECK-NEXT: abs v0.4h, v0.4h194; CHECK-NEXT: ret195entry:196 %res = call <4 x i8> @llvm.abs.v4i8(<4 x i8> %a, i1 0)197 ret <4 x i8> %res198}199declare <4 x i8> @llvm.abs.v4i8(<4 x i8>, i1)200 201define <32 x i8> @abs_v32i8(<32 x i8> %a){202; CHECK-LABEL: abs_v32i8:203; CHECK: // %bb.0: // %entry204; CHECK-NEXT: abs v0.16b, v0.16b205; CHECK-NEXT: abs v1.16b, v1.16b206; CHECK-NEXT: ret207entry:208 %res = call <32 x i8> @llvm.abs.v32i8(<32 x i8> %a, i1 0)209 ret <32 x i8> %res210}211declare <32 x i8> @llvm.abs.v32i8(<32 x i8>, i1)212 213define <2 x i16> @abs_v2i16(<2 x i16> %a){214; CHECK-LABEL: abs_v2i16:215; CHECK: // %bb.0: // %entry216; CHECK-NEXT: shl v0.2s, v0.2s, #16217; CHECK-NEXT: sshr v0.2s, v0.2s, #16218; CHECK-NEXT: abs v0.2s, v0.2s219; CHECK-NEXT: ret220entry:221 %res = call <2 x i16> @llvm.abs.v2i16(<2 x i16> %a, i1 0)222 ret <2 x i16> %res223}224declare <2 x i16> @llvm.abs.v2i16(<2 x i16>, i1)225 226define <16 x i16> @abs_v16i16(<16 x i16> %a){227; CHECK-LABEL: abs_v16i16:228; CHECK: // %bb.0: // %entry229; CHECK-NEXT: abs v0.8h, v0.8h230; CHECK-NEXT: abs v1.8h, v1.8h231; CHECK-NEXT: ret232entry:233 %res = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a, i1 0)234 ret <16 x i16> %res235}236declare <16 x i16> @llvm.abs.v16i16(<16 x i16>, i1)237 238define <1 x i32> @abs_v1i32(<1 x i32> %a){239; CHECK-SD-LABEL: abs_v1i32:240; CHECK-SD: // %bb.0: // %entry241; CHECK-SD-NEXT: abs v0.2s, v0.2s242; CHECK-SD-NEXT: ret243;244; CHECK-GI-LABEL: abs_v1i32:245; CHECK-GI: // %bb.0: // %entry246; CHECK-GI-NEXT: fmov w8, s0247; CHECK-GI-NEXT: fmov w9, s0248; CHECK-GI-NEXT: cmp w8, #0249; CHECK-GI-NEXT: cneg w8, w9, le250; CHECK-GI-NEXT: fmov s0, w8251; CHECK-GI-NEXT: ret252entry:253 %res = call <1 x i32> @llvm.abs.v1i32(<1 x i32> %a, i1 0)254 ret <1 x i32> %res255}256declare <1 x i32> @llvm.abs.v1i32(<1 x i32>, i1)257 258define <8 x i32> @abs_v8i32(<8 x i32> %a){259; CHECK-LABEL: abs_v8i32:260; CHECK: // %bb.0: // %entry261; CHECK-NEXT: abs v0.4s, v0.4s262; CHECK-NEXT: abs v1.4s, v1.4s263; CHECK-NEXT: ret264entry:265 %res = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %a, i1 0)266 ret <8 x i32> %res267}268declare <8 x i32> @llvm.abs.v8i32(<8 x i32>, i1)269 270define <4 x i64> @abs_v4i64(<4 x i64> %a){271; CHECK-LABEL: abs_v4i64:272; CHECK: // %bb.0: // %entry273; CHECK-NEXT: abs v0.2d, v0.2d274; CHECK-NEXT: abs v1.2d, v1.2d275; CHECK-NEXT: ret276entry:277 %res = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a, i1 0)278 ret <4 x i64> %res279}280declare <4 x i64> @llvm.abs.v4i64(<4 x i64>, i1)281 282define <2 x i128> @abs_v4i128(<2 x i128> %a){283; CHECK-SD-LABEL: abs_v4i128:284; CHECK-SD: // %bb.0: // %entry285; CHECK-SD-NEXT: asr x8, x1, #63286; CHECK-SD-NEXT: asr x9, x3, #63287; CHECK-SD-NEXT: eor x10, x0, x8288; CHECK-SD-NEXT: eor x11, x1, x8289; CHECK-SD-NEXT: subs x0, x10, x8290; CHECK-SD-NEXT: eor x10, x2, x9291; CHECK-SD-NEXT: sbc x1, x11, x8292; CHECK-SD-NEXT: eor x8, x3, x9293; CHECK-SD-NEXT: subs x2, x10, x9294; CHECK-SD-NEXT: sbc x3, x8, x9295; CHECK-SD-NEXT: ret296;297; CHECK-GI-LABEL: abs_v4i128:298; CHECK-GI: // %bb.0: // %entry299; CHECK-GI-NEXT: asr x8, x1, #63300; CHECK-GI-NEXT: asr x9, x3, #63301; CHECK-GI-NEXT: adds x10, x0, x8302; CHECK-GI-NEXT: adc x11, x1, x8303; CHECK-GI-NEXT: adds x12, x2, x9304; CHECK-GI-NEXT: eor x0, x10, x8305; CHECK-GI-NEXT: adc x13, x3, x9306; CHECK-GI-NEXT: eor x1, x11, x8307; CHECK-GI-NEXT: eor x2, x12, x9308; CHECK-GI-NEXT: eor x3, x13, x9309; CHECK-GI-NEXT: ret310entry:311 %res = call <2 x i128> @llvm.abs.v2i128(<2 x i128> %a, i1 0)312 ret <2 x i128> %res313}314declare <2 x i128> @llvm.abs.v2i128(<2 x i128>, i1)315 316; ===== Vectors with Non-Pow 2 Widths =====317 318define <3 x i8> @abs_v3i8(<3 x i8> %a){319; CHECK-SD-LABEL: abs_v3i8:320; CHECK-SD: // %bb.0: // %entry321; CHECK-SD-NEXT: fmov s0, w0322; CHECK-SD-NEXT: mov v0.h[1], w1323; CHECK-SD-NEXT: mov v0.h[2], w2324; CHECK-SD-NEXT: shl v0.4h, v0.4h, #8325; CHECK-SD-NEXT: sshr v0.4h, v0.4h, #8326; CHECK-SD-NEXT: abs v0.4h, v0.4h327; CHECK-SD-NEXT: umov w0, v0.h[0]328; CHECK-SD-NEXT: umov w1, v0.h[1]329; CHECK-SD-NEXT: umov w2, v0.h[2]330; CHECK-SD-NEXT: ret331;332; CHECK-GI-LABEL: abs_v3i8:333; CHECK-GI: // %bb.0: // %entry334; CHECK-GI-NEXT: fmov s0, w0335; CHECK-GI-NEXT: mov v0.b[1], w1336; CHECK-GI-NEXT: mov v0.b[2], w2337; CHECK-GI-NEXT: abs v0.8b, v0.8b338; CHECK-GI-NEXT: umov w0, v0.b[0]339; CHECK-GI-NEXT: umov w1, v0.b[1]340; CHECK-GI-NEXT: umov w2, v0.b[2]341; CHECK-GI-NEXT: ret342entry:343 %res = call <3 x i8> @llvm.abs.v3i8(<3 x i8> %a, i1 0)344 ret <3 x i8> %res345}346declare <3 x i8> @llvm.abs.v3i8(<3 x i8>, i1)347 348define <7 x i8> @abs_v7i8(<7 x i8> %a){349; CHECK-LABEL: abs_v7i8:350; CHECK: // %bb.0: // %entry351; CHECK-NEXT: abs v0.8b, v0.8b352; CHECK-NEXT: ret353entry:354 %res = call <7 x i8> @llvm.abs.v7i8(<7 x i8> %a, i1 0)355 ret <7 x i8> %res356}357declare <7 x i8> @llvm.abs.v7i8(<7 x i8>, i1)358 359define <3 x i16> @abs_v3i16(<3 x i16> %a){360; CHECK-LABEL: abs_v3i16:361; CHECK: // %bb.0: // %entry362; CHECK-NEXT: abs v0.4h, v0.4h363; CHECK-NEXT: ret364entry:365 %res = call <3 x i16> @llvm.abs.v3i16(<3 x i16> %a, i1 0)366 ret <3 x i16> %res367}368declare <3 x i16> @llvm.abs.v3i16(<3 x i16>, i1)369 370define <7 x i16> @abs_v7i16(<7 x i16> %a){371; CHECK-LABEL: abs_v7i16:372; CHECK: // %bb.0: // %entry373; CHECK-NEXT: abs v0.8h, v0.8h374; CHECK-NEXT: ret375entry:376 %res = call <7 x i16> @llvm.abs.v7i16(<7 x i16> %a, i1 0)377 ret <7 x i16> %res378}379declare <7 x i16> @llvm.abs.v7i16(<7 x i16>, i1)380 381define <3 x i32> @abs_v3i32(<3 x i32> %a){382; CHECK-LABEL: abs_v3i32:383; CHECK: // %bb.0: // %entry384; CHECK-NEXT: abs v0.4s, v0.4s385; CHECK-NEXT: ret386entry:387 %res = call <3 x i32> @llvm.abs.v3i32(<3 x i32> %a, i1 0)388 ret <3 x i32> %res389}390declare <3 x i32> @llvm.abs.v3i32(<3 x i32>, i1)391