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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SVE3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s --check-prefixes=CHECK,CHECK-STREAMING4 5; == Scalable ==6 7define <vscale x 16 x i1> @lane_mask_nxv16i1_i32(i32 %index, i32 %TC) {8; CHECK-LABEL: lane_mask_nxv16i1_i32:9; CHECK: // %bb.0:10; CHECK-NEXT: whilelo p0.b, w0, w111; CHECK-NEXT: ret12 %active.lane.mask = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i32(i32 %index, i32 %TC)13 ret <vscale x 16 x i1> %active.lane.mask14}15 16define <vscale x 8 x i1> @lane_mask_nxv8i1_i32(i32 %index, i32 %TC) {17; CHECK-LABEL: lane_mask_nxv8i1_i32:18; CHECK: // %bb.0:19; CHECK-NEXT: whilelo p0.h, w0, w120; CHECK-NEXT: ret21 %active.lane.mask = call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i32(i32 %index, i32 %TC)22 ret <vscale x 8 x i1> %active.lane.mask23}24 25define <vscale x 4 x i1> @lane_mask_nxv4i1_i32(i32 %index, i32 %TC) {26; CHECK-LABEL: lane_mask_nxv4i1_i32:27; CHECK: // %bb.0:28; CHECK-NEXT: whilelo p0.s, w0, w129; CHECK-NEXT: ret30 %active.lane.mask = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 %index, i32 %TC)31 ret <vscale x 4 x i1> %active.lane.mask32}33 34define <vscale x 2 x i1> @lane_mask_nxv2i1_i32(i32 %index, i32 %TC) {35; CHECK-LABEL: lane_mask_nxv2i1_i32:36; CHECK: // %bb.0:37; CHECK-NEXT: whilelo p0.d, w0, w138; CHECK-NEXT: ret39 %active.lane.mask = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i32(i32 %index, i32 %TC)40 ret <vscale x 2 x i1> %active.lane.mask41}42 43define <vscale x 16 x i1> @lane_mask_nxv16i1_i64(i64 %index, i64 %TC) {44; CHECK-LABEL: lane_mask_nxv16i1_i64:45; CHECK: // %bb.0:46; CHECK-NEXT: whilelo p0.b, x0, x147; CHECK-NEXT: ret48 %active.lane.mask = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 %index, i64 %TC)49 ret <vscale x 16 x i1> %active.lane.mask50}51 52define <vscale x 8 x i1> @lane_mask_nxv8i1_i64(i64 %index, i64 %TC) {53; CHECK-LABEL: lane_mask_nxv8i1_i64:54; CHECK: // %bb.0:55; CHECK-NEXT: whilelo p0.h, x0, x156; CHECK-NEXT: ret57 %active.lane.mask = call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i64(i64 %index, i64 %TC)58 ret <vscale x 8 x i1> %active.lane.mask59}60 61define <vscale x 4 x i1> @lane_mask_nxv4i1_i64(i64 %index, i64 %TC) {62; CHECK-LABEL: lane_mask_nxv4i1_i64:63; CHECK: // %bb.0:64; CHECK-NEXT: whilelo p0.s, x0, x165; CHECK-NEXT: ret66 %active.lane.mask = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 %index, i64 %TC)67 ret <vscale x 4 x i1> %active.lane.mask68}69 70define <vscale x 2 x i1> @lane_mask_nxv2i1_i64(i64 %index, i64 %TC) {71; CHECK-LABEL: lane_mask_nxv2i1_i64:72; CHECK: // %bb.0:73; CHECK-NEXT: whilelo p0.d, x0, x174; CHECK-NEXT: ret75 %active.lane.mask = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 %index, i64 %TC)76 ret <vscale x 2 x i1> %active.lane.mask77}78 79define <vscale x 16 x i1> @lane_mask_nxv16i1_i8(i8 %index, i8 %TC) {80; CHECK-LABEL: lane_mask_nxv16i1_i8:81; CHECK: // %bb.0:82; CHECK-NEXT: and w8, w1, #0xff83; CHECK-NEXT: and w9, w0, #0xff84; CHECK-NEXT: whilelo p0.b, w9, w885; CHECK-NEXT: ret86 %active.lane.mask = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i8(i8 %index, i8 %TC)87 ret <vscale x 16 x i1> %active.lane.mask88}89 90define <vscale x 8 x i1> @lane_mask_nxv8i1_i8(i8 %index, i8 %TC) {91; CHECK-LABEL: lane_mask_nxv8i1_i8:92; CHECK: // %bb.0:93; CHECK-NEXT: and w8, w1, #0xff94; CHECK-NEXT: and w9, w0, #0xff95; CHECK-NEXT: whilelo p0.h, w9, w896; CHECK-NEXT: ret97 %active.lane.mask = call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i8(i8 %index, i8 %TC)98 ret <vscale x 8 x i1> %active.lane.mask99}100 101define <vscale x 4 x i1> @lane_mask_nxv4i1_i8(i8 %index, i8 %TC) {102; CHECK-LABEL: lane_mask_nxv4i1_i8:103; CHECK: // %bb.0:104; CHECK-NEXT: and w8, w1, #0xff105; CHECK-NEXT: and w9, w0, #0xff106; CHECK-NEXT: whilelo p0.s, w9, w8107; CHECK-NEXT: ret108 %active.lane.mask = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i8(i8 %index, i8 %TC)109 ret <vscale x 4 x i1> %active.lane.mask110}111 112define <vscale x 2 x i1> @lane_mask_nxv2i1_i8(i8 %index, i8 %TC) {113; CHECK-LABEL: lane_mask_nxv2i1_i8:114; CHECK: // %bb.0:115; CHECK-NEXT: and w8, w1, #0xff116; CHECK-NEXT: and w9, w0, #0xff117; CHECK-NEXT: whilelo p0.d, w9, w8118; CHECK-NEXT: ret119 %active.lane.mask = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i8(i8 %index, i8 %TC)120 ret <vscale x 2 x i1> %active.lane.mask121}122 123 124; Illegal types125 126define <vscale x 32 x i1> @lane_mask_nxv32i1_i32(i32 %index, i32 %TC) {127; CHECK-LABEL: lane_mask_nxv32i1_i32:128; CHECK: // %bb.0:129; CHECK-NEXT: rdvl x8, #1130; CHECK-NEXT: adds w8, w0, w8131; CHECK-NEXT: csinv w8, w8, wzr, lo132; CHECK-NEXT: whilelo p0.b, w0, w1133; CHECK-NEXT: whilelo p1.b, w8, w1134; CHECK-NEXT: ret135 %active.lane.mask = call <vscale x 32 x i1> @llvm.get.active.lane.mask.nxv32i1.i32(i32 %index, i32 %TC)136 ret <vscale x 32 x i1> %active.lane.mask137}138 139define <vscale x 32 x i1> @lane_mask_nxv32i1_i64(i64 %index, i64 %TC) {140; CHECK-LABEL: lane_mask_nxv32i1_i64:141; CHECK: // %bb.0:142; CHECK-NEXT: rdvl x8, #1143; CHECK-NEXT: adds x8, x0, x8144; CHECK-NEXT: csinv x8, x8, xzr, lo145; CHECK-NEXT: whilelo p0.b, x0, x1146; CHECK-NEXT: whilelo p1.b, x8, x1147; CHECK-NEXT: ret148 %active.lane.mask = call <vscale x 32 x i1> @llvm.get.active.lane.mask.nxv32i1.i64(i64 %index, i64 %TC)149 ret <vscale x 32 x i1> %active.lane.mask150}151 152define <vscale x 32 x i1> @lane_mask_nxv32i1_i8(i8 %index, i8 %TC) {153; CHECK-LABEL: lane_mask_nxv32i1_i8:154; CHECK: // %bb.0:155; CHECK-NEXT: rdvl x8, #1156; CHECK-NEXT: and w9, w0, #0xff157; CHECK-NEXT: mov w10, #255 // =0xff158; CHECK-NEXT: add w8, w9, w8, uxtb159; CHECK-NEXT: and w11, w1, #0xff160; CHECK-NEXT: cmp w8, #255161; CHECK-NEXT: csel w8, w8, w10, lo162; CHECK-NEXT: whilelo p0.b, w9, w11163; CHECK-NEXT: whilelo p1.b, w8, w11164; CHECK-NEXT: ret165 %active.lane.mask = call <vscale x 32 x i1> @llvm.get.active.lane.mask.nxv32i1.i8(i8 %index, i8 %TC)166 ret <vscale x 32 x i1> %active.lane.mask167}168 169define <vscale x 7 x i1> @lane_mask_nxv7i1_i64(i64 %index, i64 %TC) {170; CHECK-LABEL: lane_mask_nxv7i1_i64:171; CHECK: // %bb.0:172; CHECK-NEXT: whilelo p0.h, x0, x1173; CHECK-NEXT: ret174 %active.lane.mask = call <vscale x 7 x i1> @llvm.get.active.lane.mask.nxv7i1.i64(i64 %index, i64 %TC)175 ret <vscale x 7 x i1> %active.lane.mask176}177 178define <vscale x 1 x i1> @lane_mask_nxv1i1_i32(i32 %index, i32 %TC) {179; CHECK-LABEL: lane_mask_nxv1i1_i32:180; CHECK: // %bb.0:181; CHECK-NEXT: index z0.s, #0, #1182; CHECK-NEXT: mov z1.s, w0183; CHECK-NEXT: ptrue p0.s184; CHECK-NEXT: uqadd z0.s, z0.s, z1.s185; CHECK-NEXT: mov z1.s, w1186; CHECK-NEXT: cmphi p0.s, p0/z, z1.s, z0.s187; CHECK-NEXT: punpklo p0.h, p0.b188; CHECK-NEXT: punpklo p0.h, p0.b189; CHECK-NEXT: ret190 %active.lane.mask = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i32(i32 %index, i32 %TC)191 ret <vscale x 1 x i1> %active.lane.mask192}193 194; UTC_ARGS: --disable195; This test exists to protect against a compiler crash caused by an attempt to196; convert (via changeVectorElementType) an MVT into an EVT, which is impossible.197; The test's output is large and not relevant so check lines have been disabled.198define <vscale x 64 x i1> @lane_mask_nxv64i1_i64(i64 %index, i64 %TC) {199; CHECK-LABEL: lane_mask_nxv64i1_i64:200 %active.lane.mask = call <vscale x 64 x i1> @llvm.get.active.lane.mask.nxv64i1.i64(i64 %index, i64 %TC)201 ret <vscale x 64 x i1> %active.lane.mask202}203; UTC_ARGS: --enable204 205; == Fixed width ==206 207define <16 x i1> @lane_mask_v16i1_i32(i32 %index, i32 %TC) {208; CHECK-LABEL: lane_mask_v16i1_i32:209; CHECK: // %bb.0:210; CHECK-NEXT: whilelo p0.b, w0, w1211; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff212; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0213; CHECK-NEXT: ret214 %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i32 %TC)215 ret <16 x i1> %active.lane.mask216}217 218define <8 x i1> @lane_mask_v8i1_i32(i32 %index, i32 %TC) {219; CHECK-LABEL: lane_mask_v8i1_i32:220; CHECK: // %bb.0:221; CHECK-NEXT: whilelo p0.b, w0, w1222; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff223; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0224; CHECK-NEXT: ret225 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %TC)226 ret <8 x i1> %active.lane.mask227}228 229define <4 x i1> @lane_mask_v4i1_i32(i32 %index, i32 %TC) {230; CHECK-LABEL: lane_mask_v4i1_i32:231; CHECK: // %bb.0:232; CHECK-NEXT: whilelo p0.h, w0, w1233; CHECK-NEXT: mov z0.h, p0/z, #-1 // =0xffffffffffffffff234; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0235; CHECK-NEXT: ret236 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %TC)237 ret <4 x i1> %active.lane.mask238}239 240define <2 x i1> @lane_mask_v2i1_i32(i32 %index, i32 %TC) {241; CHECK-LABEL: lane_mask_v2i1_i32:242; CHECK: // %bb.0:243; CHECK-NEXT: whilelo p0.s, w0, w1244; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff245; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0246; CHECK-NEXT: ret247 %active.lane.mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 %index, i32 %TC)248 ret <2 x i1> %active.lane.mask249}250 251define <16 x i1> @lane_mask_v16i1_i64(i64 %index, i64 %TC) {252; CHECK-LABEL: lane_mask_v16i1_i64:253; CHECK: // %bb.0:254; CHECK-NEXT: whilelo p0.b, x0, x1255; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff256; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0257; CHECK-NEXT: ret258 %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 %index, i64 %TC)259 ret <16 x i1> %active.lane.mask260}261 262define <8 x i1> @lane_mask_v8i1_i64(i64 %index, i64 %TC) {263; CHECK-LABEL: lane_mask_v8i1_i64:264; CHECK: // %bb.0:265; CHECK-NEXT: whilelo p0.b, x0, x1266; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff267; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0268; CHECK-NEXT: ret269 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 %index, i64 %TC)270 ret <8 x i1> %active.lane.mask271}272 273define <4 x i1> @lane_mask_v4i1_i64(i64 %index, i64 %TC) {274; CHECK-LABEL: lane_mask_v4i1_i64:275; CHECK: // %bb.0:276; CHECK-NEXT: whilelo p0.h, x0, x1277; CHECK-NEXT: mov z0.h, p0/z, #-1 // =0xffffffffffffffff278; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0279; CHECK-NEXT: ret280 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 %index, i64 %TC)281 ret <4 x i1> %active.lane.mask282}283 284define <2 x i1> @lane_mask_v2i1_i64(i64 %index, i64 %TC) {285; CHECK-LABEL: lane_mask_v2i1_i64:286; CHECK: // %bb.0:287; CHECK-NEXT: whilelo p0.s, x0, x1288; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff289; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0290; CHECK-NEXT: ret291 %active.lane.mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 %index, i64 %TC)292 ret <2 x i1> %active.lane.mask293}294 295define <16 x i1> @lane_mask_v16i1_i8(i8 %index, i8 %TC) {296; CHECK-SVE-LABEL: lane_mask_v16i1_i8:297; CHECK-SVE: // %bb.0:298; CHECK-SVE-NEXT: index z0.b, #0, #1299; CHECK-SVE-NEXT: dup v1.16b, w0300; CHECK-SVE-NEXT: uqadd v0.16b, v1.16b, v0.16b301; CHECK-SVE-NEXT: dup v1.16b, w1302; CHECK-SVE-NEXT: cmhi v0.16b, v1.16b, v0.16b303; CHECK-SVE-NEXT: ret304;305; CHECK-STREAMING-LABEL: lane_mask_v16i1_i8:306; CHECK-STREAMING: // %bb.0:307; CHECK-STREAMING-NEXT: index z0.b, w0, #1308; CHECK-STREAMING-NEXT: mov z1.b, w0309; CHECK-STREAMING-NEXT: ptrue p0.b, vl16310; CHECK-STREAMING-NEXT: cmphi p1.b, p0/z, z1.b, z0.b311; CHECK-STREAMING-NEXT: mov z1.b, p1/z, #-1 // =0xffffffffffffffff312; CHECK-STREAMING-NEXT: orr z0.d, z0.d, z1.d313; CHECK-STREAMING-NEXT: mov z1.b, w1314; CHECK-STREAMING-NEXT: cmphi p0.b, p0/z, z1.b, z0.b315; CHECK-STREAMING-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff316; CHECK-STREAMING-NEXT: // kill: def $q0 killed $q0 killed $z0317; CHECK-STREAMING-NEXT: ret318 %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i8(i8 %index, i8 %TC)319 ret <16 x i1> %active.lane.mask320}321 322define <8 x i1> @lane_mask_v8i1_i8(i8 %index, i8 %TC) {323; CHECK-SVE-LABEL: lane_mask_v8i1_i8:324; CHECK-SVE: // %bb.0:325; CHECK-SVE-NEXT: index z0.b, #0, #1326; CHECK-SVE-NEXT: dup v1.8b, w0327; CHECK-SVE-NEXT: uqadd v0.8b, v1.8b, v0.8b328; CHECK-SVE-NEXT: dup v1.8b, w1329; CHECK-SVE-NEXT: cmhi v0.8b, v1.8b, v0.8b330; CHECK-SVE-NEXT: ret331;332; CHECK-STREAMING-LABEL: lane_mask_v8i1_i8:333; CHECK-STREAMING: // %bb.0:334; CHECK-STREAMING-NEXT: index z0.b, w0, #1335; CHECK-STREAMING-NEXT: mov z1.b, w0336; CHECK-STREAMING-NEXT: ptrue p0.b, vl8337; CHECK-STREAMING-NEXT: cmphi p1.b, p0/z, z1.b, z0.b338; CHECK-STREAMING-NEXT: mov z1.b, p1/z, #-1 // =0xffffffffffffffff339; CHECK-STREAMING-NEXT: orr z0.d, z0.d, z1.d340; CHECK-STREAMING-NEXT: mov z1.b, w1341; CHECK-STREAMING-NEXT: cmphi p0.b, p0/z, z1.b, z0.b342; CHECK-STREAMING-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff343; CHECK-STREAMING-NEXT: // kill: def $d0 killed $d0 killed $z0344; CHECK-STREAMING-NEXT: ret345 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i8(i8 %index, i8 %TC)346 ret <8 x i1> %active.lane.mask347}348 349define <4 x i1> @lane_mask_v4i1_i8(i8 %index, i8 %TC) {350; CHECK-SVE-LABEL: lane_mask_v4i1_i8:351; CHECK-SVE: // %bb.0:352; CHECK-SVE-NEXT: dup v0.4h, w0353; CHECK-SVE-NEXT: index z1.h, #0, #1354; CHECK-SVE-NEXT: movi d2, #0xff00ff00ff00ff355; CHECK-SVE-NEXT: dup v3.4h, w1356; CHECK-SVE-NEXT: bic v0.4h, #255, lsl #8357; CHECK-SVE-NEXT: bic v3.4h, #255, lsl #8358; CHECK-SVE-NEXT: add v0.4h, v0.4h, v1.4h359; CHECK-SVE-NEXT: umin v0.4h, v0.4h, v2.4h360; CHECK-SVE-NEXT: cmhi v0.4h, v3.4h, v0.4h361; CHECK-SVE-NEXT: ret362;363; CHECK-STREAMING-LABEL: lane_mask_v4i1_i8:364; CHECK-STREAMING: // %bb.0:365; CHECK-STREAMING-NEXT: mov z1.h, w0366; CHECK-STREAMING-NEXT: index z0.h, #0, #1367; CHECK-STREAMING-NEXT: ptrue p0.h, vl4368; CHECK-STREAMING-NEXT: and z1.h, z1.h, #0xff369; CHECK-STREAMING-NEXT: add z0.h, z1.h, z0.h370; CHECK-STREAMING-NEXT: mov z1.h, w1371; CHECK-STREAMING-NEXT: umin z0.h, z0.h, #255372; CHECK-STREAMING-NEXT: and z1.h, z1.h, #0xff373; CHECK-STREAMING-NEXT: cmphi p0.h, p0/z, z1.h, z0.h374; CHECK-STREAMING-NEXT: mov z0.h, p0/z, #-1 // =0xffffffffffffffff375; CHECK-STREAMING-NEXT: // kill: def $d0 killed $d0 killed $z0376; CHECK-STREAMING-NEXT: ret377 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i8(i8 %index, i8 %TC)378 ret <4 x i1> %active.lane.mask379}380 381define <2 x i1> @lane_mask_v2i1_i8(i8 %index, i8 %TC) {382; CHECK-SVE-LABEL: lane_mask_v2i1_i8:383; CHECK-SVE: // %bb.0:384; CHECK-SVE-NEXT: movi d0, #0x0000ff000000ff385; CHECK-SVE-NEXT: dup v1.2s, w0386; CHECK-SVE-NEXT: index z2.s, #0, #1387; CHECK-SVE-NEXT: dup v3.2s, w1388; CHECK-SVE-NEXT: and v1.8b, v1.8b, v0.8b389; CHECK-SVE-NEXT: add v1.2s, v1.2s, v2.2s390; CHECK-SVE-NEXT: and v2.8b, v3.8b, v0.8b391; CHECK-SVE-NEXT: umin v0.2s, v1.2s, v0.2s392; CHECK-SVE-NEXT: cmhi v0.2s, v2.2s, v0.2s393; CHECK-SVE-NEXT: ret394;395; CHECK-STREAMING-LABEL: lane_mask_v2i1_i8:396; CHECK-STREAMING: // %bb.0:397; CHECK-STREAMING-NEXT: and w8, w0, #0xff398; CHECK-STREAMING-NEXT: ptrue p0.s, vl2399; CHECK-STREAMING-NEXT: index z0.s, w8, #1400; CHECK-STREAMING-NEXT: and w8, w1, #0xff401; CHECK-STREAMING-NEXT: mov z1.s, w8402; CHECK-STREAMING-NEXT: umin z0.s, z0.s, #255403; CHECK-STREAMING-NEXT: cmphi p0.s, p0/z, z1.s, z0.s404; CHECK-STREAMING-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff405; CHECK-STREAMING-NEXT: // kill: def $d0 killed $d0 killed $z0406; CHECK-STREAMING-NEXT: ret407 %active.lane.mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i8(i8 %index, i8 %TC)408 ret <2 x i1> %active.lane.mask409}410 411define <vscale x 4 x i1> @lane_mask_nxv4i1_imm3() {412; CHECK-LABEL: lane_mask_nxv4i1_imm3:413; CHECK: // %bb.0: // %entry414; CHECK-NEXT: ptrue p0.s, vl3415; CHECK-NEXT: ret416entry:417 %active.lane.mask = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 0, i64 3)418 ret <vscale x 4 x i1> %active.lane.mask419}420 421define <vscale x 4 x i1> @lane_mask_nxv4i1_imm5() {422; CHECK-LABEL: lane_mask_nxv4i1_imm5:423; CHECK: // %bb.0: // %entry424; CHECK-NEXT: mov w8, #5 // =0x5425; CHECK-NEXT: whilelo p0.s, xzr, x8426; CHECK-NEXT: ret427entry:428 %active.lane.mask = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 0, i64 5)429 ret <vscale x 4 x i1> %active.lane.mask430}431 432define <vscale x 4 x i1> @lane_mask_nxv4i1_imm4() {433; CHECK-LABEL: lane_mask_nxv4i1_imm4:434; CHECK: // %bb.0: // %entry435; CHECK-NEXT: ptrue p0.s, vl4436; CHECK-NEXT: ret437entry:438 %active.lane.mask = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 10, i64 14)439 ret <vscale x 4 x i1> %active.lane.mask440}441 442define <vscale x 16 x i1> @lane_mask_nxv16i1_imm10() {443; CHECK-LABEL: lane_mask_nxv16i1_imm10:444; CHECK: // %bb.0: // %entry445; CHECK-NEXT: mov w8, #10 // =0xa446; CHECK-NEXT: whilelo p0.b, xzr, x8447; CHECK-NEXT: ret448entry:449 %active.lane.mask = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 10)450 ret <vscale x 16 x i1> %active.lane.mask451}452 453define <vscale x 16 x i1> @lane_mask_nxv16i1_imm256() vscale_range(16, 16) {454; CHECK-LABEL: lane_mask_nxv16i1_imm256:455; CHECK: // %bb.0: // %entry456; CHECK-NEXT: ptrue p0.b, vl256457; CHECK-NEXT: ret458entry:459 %active.lane.mask = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 256)460 ret <vscale x 16 x i1> %active.lane.mask461}462 463define <8 x i1> @lane_mask_v8i1_imm3() {464; CHECK-LABEL: lane_mask_v8i1_imm3:465; CHECK: // %bb.0: // %entry466; CHECK-NEXT: ptrue p0.b, vl3467; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff468; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0469; CHECK-NEXT: ret470entry:471 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 0, i64 3)472 ret <8 x i1> %active.lane.mask473}474 475declare <vscale x 32 x i1> @llvm.get.active.lane.mask.nxv32i1.i32(i32, i32)476declare <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i32(i32, i32)477declare <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i32(i32, i32)478declare <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32, i32)479declare <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i32(i32, i32)480declare <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i32(i32, i32)481 482declare <vscale x 64 x i1> @llvm.get.active.lane.mask.nxv64i1.i64(i64, i64)483declare <vscale x 32 x i1> @llvm.get.active.lane.mask.nxv32i1.i64(i64, i64)484declare <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64, i64)485declare <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i64(i64, i64)486declare <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64, i64)487declare <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64, i64)488 489declare <vscale x 32 x i1> @llvm.get.active.lane.mask.nxv32i1.i8(i8, i8)490declare <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i8(i8, i8)491declare <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i8(i8, i8)492declare <vscale x 7 x i1> @llvm.get.active.lane.mask.nxv7i1.i8(i8, i8)493declare <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i8(i8, i8)494declare <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i8(i8, i8)495 496declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32)497declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)498declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)499declare <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32, i32)500 501declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64, i64)502declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64, i64)503declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64, i64)504declare <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64, i64)505 506declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i8(i8, i8)507declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i8(i8, i8)508declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i8(i8, i8)509declare <2 x i1> @llvm.get.active.lane.mask.v2i1.i8(i8, i8)510