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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=aarch64-none-elf -mattr=+aes < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64-none-elf -mattr=+aes -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define i64 @add_i64_ext_load(<1 x i64> %A, ptr %B) nounwind {6; CHECK-SD-LABEL: add_i64_ext_load:7; CHECK-SD: // %bb.0:8; CHECK-SD-NEXT: ldr d1, [x0]9; CHECK-SD-NEXT: add d0, d0, d110; CHECK-SD-NEXT: fmov x0, d011; CHECK-SD-NEXT: ret12;13; CHECK-GI-LABEL: add_i64_ext_load:14; CHECK-GI: // %bb.0:15; CHECK-GI-NEXT: fmov x9, d016; CHECK-GI-NEXT: ldr x8, [x0]17; CHECK-GI-NEXT: add x0, x9, x818; CHECK-GI-NEXT: ret19 %a = extractelement <1 x i64> %A, i32 020 %b = load i64, ptr %B21 %c = add i64 %a, %b22 ret i64 %c23}24 25define i64 @sub_i64_ext_load(<1 x i64> %A, ptr %B) nounwind {26; CHECK-SD-LABEL: sub_i64_ext_load:27; CHECK-SD: // %bb.0:28; CHECK-SD-NEXT: ldr d1, [x0]29; CHECK-SD-NEXT: sub d0, d0, d130; CHECK-SD-NEXT: fmov x0, d031; CHECK-SD-NEXT: ret32;33; CHECK-GI-LABEL: sub_i64_ext_load:34; CHECK-GI: // %bb.0:35; CHECK-GI-NEXT: fmov x9, d036; CHECK-GI-NEXT: ldr x8, [x0]37; CHECK-GI-NEXT: sub x0, x9, x838; CHECK-GI-NEXT: ret39 %a = extractelement <1 x i64> %A, i32 040 %b = load i64, ptr %B41 %c = sub i64 %a, %b42 ret i64 %c43}44 45define void @add_i64_ext_load_store(<1 x i64> %A, ptr %B) nounwind {46; CHECK-SD-LABEL: add_i64_ext_load_store:47; CHECK-SD: // %bb.0:48; CHECK-SD-NEXT: ldr d1, [x0]49; CHECK-SD-NEXT: add d0, d0, d150; CHECK-SD-NEXT: str d0, [x0]51; CHECK-SD-NEXT: ret52;53; CHECK-GI-LABEL: add_i64_ext_load_store:54; CHECK-GI: // %bb.0:55; CHECK-GI-NEXT: fmov x9, d056; CHECK-GI-NEXT: ldr x8, [x0]57; CHECK-GI-NEXT: add x8, x9, x858; CHECK-GI-NEXT: str x8, [x0]59; CHECK-GI-NEXT: ret60 %a = extractelement <1 x i64> %A, i32 061 %b = load i64, ptr %B62 %c = add i64 %a, %b63 store i64 %c, ptr %B64 ret void65}66 67define i64 @add_v2i64_ext_load(<2 x i64> %A, ptr %B) nounwind {68; CHECK-LABEL: add_v2i64_ext_load:69; CHECK: // %bb.0:70; CHECK-NEXT: fmov x9, d071; CHECK-NEXT: ldr x8, [x0]72; CHECK-NEXT: add x0, x9, x873; CHECK-NEXT: ret74 %a = extractelement <2 x i64> %A, i32 075 %b = load i64, ptr %B76 %c = add i64 %a, %b77 ret i64 %c78}79 80define i64 @add_i64_ext_ext(<1 x i64> %A, <1 x i64> %B) nounwind {81; CHECK-SD-LABEL: add_i64_ext_ext:82; CHECK-SD: // %bb.0:83; CHECK-SD-NEXT: add d0, d0, d184; CHECK-SD-NEXT: fmov x0, d085; CHECK-SD-NEXT: ret86;87; CHECK-GI-LABEL: add_i64_ext_ext:88; CHECK-GI: // %bb.0:89; CHECK-GI-NEXT: fmov x8, d090; CHECK-GI-NEXT: fmov x9, d191; CHECK-GI-NEXT: add x0, x8, x992; CHECK-GI-NEXT: ret93 %a = extractelement <1 x i64> %A, i32 094 %b = extractelement <1 x i64> %B, i32 095 %c = add i64 %a, %b96 ret i64 %c97}98 99define i32 @add_i32_ext_load(<1 x i32> %A, ptr %B) nounwind {100; CHECK-SD-LABEL: add_i32_ext_load:101; CHECK-SD: // %bb.0:102; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0103; CHECK-SD-NEXT: fmov w9, s0104; CHECK-SD-NEXT: ldr w8, [x0]105; CHECK-SD-NEXT: add w0, w9, w8106; CHECK-SD-NEXT: ret107;108; CHECK-GI-LABEL: add_i32_ext_load:109; CHECK-GI: // %bb.0:110; CHECK-GI-NEXT: fmov w9, s0111; CHECK-GI-NEXT: ldr w8, [x0]112; CHECK-GI-NEXT: add w0, w9, w8113; CHECK-GI-NEXT: ret114 %a = extractelement <1 x i32> %A, i32 0115 %b = load i32, ptr %B116 %c = add i32 %a, %b117 ret i32 %c118}119 120define i64 @add_i64_ext_ext_test1(<1 x i64> %A, <2 x i64> %B) nounwind {121; CHECK-SD-LABEL: add_i64_ext_ext_test1:122; CHECK-SD: // %bb.0:123; CHECK-SD-NEXT: ext v2.16b, v1.16b, v1.16b, #8124; CHECK-SD-NEXT: add d0, d0, d1125; CHECK-SD-NEXT: add d0, d0, d2126; CHECK-SD-NEXT: fmov x0, d0127; CHECK-SD-NEXT: ret128;129; CHECK-GI-LABEL: add_i64_ext_ext_test1:130; CHECK-GI: // %bb.0:131; CHECK-GI-NEXT: mov x8, v1.d[1]132; CHECK-GI-NEXT: fmov x9, d0133; CHECK-GI-NEXT: fmov x10, d1134; CHECK-GI-NEXT: add x9, x9, x10135; CHECK-GI-NEXT: add x0, x9, x8136; CHECK-GI-NEXT: ret137 %a = extractelement <1 x i64> %A, i32 0138 %b = extractelement <2 x i64> %B, i32 0139 %c = extractelement <2 x i64> %B, i32 1140 %d = add i64 %a, %b141 %e = add i64 %d, %c142 ret i64 %e143}144 145define i64 @sub_i64_ext_ext_test1(<1 x i64> %A, <2 x i64> %B) nounwind {146; CHECK-SD-LABEL: sub_i64_ext_ext_test1:147; CHECK-SD: // %bb.0:148; CHECK-SD-NEXT: ext v2.16b, v1.16b, v1.16b, #8149; CHECK-SD-NEXT: sub d0, d0, d1150; CHECK-SD-NEXT: sub d0, d0, d2151; CHECK-SD-NEXT: fmov x0, d0152; CHECK-SD-NEXT: ret153;154; CHECK-GI-LABEL: sub_i64_ext_ext_test1:155; CHECK-GI: // %bb.0:156; CHECK-GI-NEXT: mov x8, v1.d[1]157; CHECK-GI-NEXT: fmov x9, d0158; CHECK-GI-NEXT: fmov x10, d1159; CHECK-GI-NEXT: sub x9, x9, x10160; CHECK-GI-NEXT: sub x0, x9, x8161; CHECK-GI-NEXT: ret162 %a = extractelement <1 x i64> %A, i32 0163 %b = extractelement <2 x i64> %B, i32 0164 %c = extractelement <2 x i64> %B, i32 1165 %d = sub i64 %a, %b166 %e = sub i64 %d, %c167 ret i64 %e168}169