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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -run-pass=aarch64-mi-peephole-opt -o - -mtriple=aarch64-unknown-linux -verify-machineinstrs %s | FileCheck %s3 4# Main intention is to verify machine instructions have valid register classes.5# Use of UBFM[W|X]ri is used as an arbitrary instruction that requires GPR[32|64]RegClass.6# If the ADD/SUB optimization generates invalid register classes, this test will fail.7---8name: addi9body: |10 bb.0.entry:11 liveins: $w012 ; CHECK-LABEL: name: addi13 ; CHECK: liveins: $w014 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY $w016 ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 273, 1217 ; CHECK-NEXT: [[ADDWri1:%[0-9]+]]:gpr32common = ADDWri [[ADDWri]], 3549, 018 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[ADDWri1]], 28, 3119 ; CHECK-NEXT: $w0 = COPY [[UBFMWri]]20 ; CHECK-NEXT: RET_ReallyLR implicit $w021 %0:gpr32 = COPY $w022 %1:gpr32 = MOVi32imm 112175723 %2:gpr32 = ADDWrr %0, %124 %3:gpr32 = UBFMWri %2, 28, 3125 $w0 = COPY %326 RET_ReallyLR implicit $w027...28---29name: addl30body: |31 bb.0.entry:32 liveins: $x033 ; CHECK-LABEL: name: addl34 ; CHECK: liveins: $x035 ; CHECK-NEXT: {{ $}}36 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x037 ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 273, 1238 ; CHECK-NEXT: [[ADDXri1:%[0-9]+]]:gpr64common = ADDXri [[ADDXri]], 3549, 039 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ADDXri1]].sub_3240 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 28, 3141 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[UBFMWri]], %subreg.sub_3242 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]43 ; CHECK-NEXT: RET_ReallyLR implicit $x044 %0:gpr64 = COPY $x045 %1:gpr32 = MOVi32imm 112175746 %2:gpr64 = SUBREG_TO_REG 0, %1, %subreg.sub_3247 %3:gpr64 = ADDXrr %0, killed %248 %4:gpr64 = UBFMXri %3, 28, 3149 $x0 = COPY %450 RET_ReallyLR implicit $x051...52---53name: addl_negate54body: |55 bb.0.entry:56 liveins: $x057 ; CHECK-LABEL: name: addl_negate58 ; CHECK: liveins: $x059 ; CHECK-NEXT: {{ $}}60 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x061 ; CHECK-NEXT: [[SUBXri:%[0-9]+]]:gpr64sp = SUBXri [[COPY]], 273, 1262 ; CHECK-NEXT: [[SUBXri1:%[0-9]+]]:gpr64common = SUBXri [[SUBXri]], 3549, 063 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[SUBXri1]].sub_3264 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 28, 3165 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[UBFMWri]], %subreg.sub_3266 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]67 ; CHECK-NEXT: RET_ReallyLR implicit $x068 %0:gpr64 = COPY $x069 %1:gpr64 = MOVi64imm -112175770 %2:gpr64 = ADDXrr %0, killed %171 %3:gpr64 = UBFMXri %2, 28, 3172 $x0 = COPY %373 RET_ReallyLR implicit $x074...75---76name: add_xzr77body: |78 bb.0.entry:79 liveins: $x080 ; CHECK-LABEL: name: add_xzr81 ; CHECK: liveins: $x082 ; CHECK-NEXT: {{ $}}83 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x084 ; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -210509885 ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64common = ADDXrr $xzr, [[MOVi64imm]]86 ; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY]], [[ADDXrr]]87 ; CHECK-NEXT: $x0 = COPY [[MADDXrrr]]88 ; CHECK-NEXT: RET_ReallyLR implicit $x089 %0:gpr64 = COPY $x090 %2:gpr64 = MOVi64imm -210509891 %4:gpr64common = ADDXrr $xzr, %292 %3:gpr64 = MADDXrrr %0, %0, %493 $x0 = COPY %394 RET_ReallyLR implicit $x095...96---97name: sub_xzr98body: |99 bb.0.entry:100 liveins: $x0101 ; CHECK-LABEL: name: sub_xzr102 ; CHECK: liveins: $x0103 ; CHECK-NEXT: {{ $}}104 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0105 ; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -2105098106 ; CHECK-NEXT: [[SUBXrr:%[0-9]+]]:gpr64common = SUBXrr $xzr, [[MOVi64imm]]107 ; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY]], [[SUBXrr]]108 ; CHECK-NEXT: $x0 = COPY [[MADDXrrr]]109 ; CHECK-NEXT: RET_ReallyLR implicit $x0110 %0:gpr64 = COPY $x0111 %2:gpr64 = MOVi64imm -2105098112 %4:gpr64common = SUBXrr $xzr, %2113 %3:gpr64 = MADDXrrr %0, %0, %4114 $x0 = COPY %3115 RET_ReallyLR implicit $x0116...117---118name: adds_xzr119body: |120 bb.0.entry:121 liveins: $x0122 ; CHECK-LABEL: name: adds_xzr123 ; CHECK: liveins: $x0124 ; CHECK-NEXT: {{ $}}125 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0126 ; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -2105098127 ; CHECK-NEXT: [[ADDSXrr:%[0-9]+]]:gpr64common = ADDSXrr $xzr, [[MOVi64imm]], implicit-def $nzcv128 ; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY]], [[ADDSXrr]]129 ; CHECK-NEXT: $x0 = COPY [[MADDXrrr]]130 ; CHECK-NEXT: RET_ReallyLR implicit $x0131 %0:gpr64 = COPY $x0132 %2:gpr64 = MOVi64imm -2105098133 %4:gpr64common = ADDSXrr $xzr, %2, implicit-def $nzcv134 %3:gpr64 = MADDXrrr %0, %0, %4135 $x0 = COPY %3136 RET_ReallyLR implicit $x0137...138---139name: subs_xzr140body: |141 bb.0.entry:142 liveins: $x0143 ; CHECK-LABEL: name: subs_xzr144 ; CHECK: liveins: $x0145 ; CHECK-NEXT: {{ $}}146 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0147 ; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -2105098148 ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64common = SUBSXrr $xzr, [[MOVi64imm]], implicit-def $nzcv149 ; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY]], [[SUBSXrr]]150 ; CHECK-NEXT: $x0 = COPY [[MADDXrrr]]151 ; CHECK-NEXT: RET_ReallyLR implicit $x0152 %0:gpr64 = COPY $x0153 %2:gpr64 = MOVi64imm -2105098154 %4:gpr64common = SUBSXrr $xzr, %2, implicit-def $nzcv155 %3:gpr64 = MADDXrrr %0, %0, %4156 $x0 = COPY %3157 RET_ReallyLR implicit $x0158