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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s3 4declare void @use(i32 %arg)5declare void @vec_use(<4 x i32> %arg)6 7; (x+c1)+c28 9define i32 @add_const_add_const(i32 %arg) {10; CHECK-LABEL: add_const_add_const:11; CHECK: // %bb.0:12; CHECK-NEXT: add w0, w0, #1013; CHECK-NEXT: ret14 %t0 = add i32 %arg, 815 %t1 = add i32 %t0, 216 ret i32 %t117}18 19define i32 @add_const_add_const_extrause(i32 %arg) {20; CHECK-LABEL: add_const_add_const_extrause:21; CHECK: // %bb.0:22; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill23; CHECK-NEXT: .cfi_def_cfa_offset 1624; CHECK-NEXT: .cfi_offset w19, -825; CHECK-NEXT: .cfi_offset w30, -1626; CHECK-NEXT: mov w19, w027; CHECK-NEXT: add w0, w0, #828; CHECK-NEXT: bl use29; CHECK-NEXT: add w0, w19, #1030; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload31; CHECK-NEXT: ret32 %t0 = add i32 %arg, 833 call void @use(i32 %t0)34 %t1 = add i32 %t0, 235 ret i32 %t136}37 38define <4 x i32> @vec_add_const_add_const(<4 x i32> %arg) {39; CHECK-LABEL: vec_add_const_add_const:40; CHECK: // %bb.0:41; CHECK-NEXT: movi v1.4s, #1042; CHECK-NEXT: add v0.4s, v0.4s, v1.4s43; CHECK-NEXT: ret44 %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>45 %t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>46 ret <4 x i32> %t147}48 49define <4 x i32> @vec_add_const_add_const_extrause(<4 x i32> %arg) {50; CHECK-LABEL: vec_add_const_add_const_extrause:51; CHECK: // %bb.0:52; CHECK-NEXT: sub sp, sp, #3253; CHECK-NEXT: str x30, [sp, #16] // 8-byte Spill54; CHECK-NEXT: .cfi_def_cfa_offset 3255; CHECK-NEXT: .cfi_offset w30, -1656; CHECK-NEXT: movi v1.4s, #857; CHECK-NEXT: str q0, [sp] // 16-byte Spill58; CHECK-NEXT: add v0.4s, v0.4s, v1.4s59; CHECK-NEXT: bl vec_use60; CHECK-NEXT: movi v0.4s, #1061; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload62; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Reload63; CHECK-NEXT: add v0.4s, v1.4s, v0.4s64; CHECK-NEXT: add sp, sp, #3265; CHECK-NEXT: ret66 %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>67 call void @vec_use(<4 x i32> %t0)68 %t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>69 ret <4 x i32> %t170}71 72define <4 x i32> @vec_add_const_add_const_nonsplat(<4 x i32> %arg) {73; CHECK-LABEL: vec_add_const_add_const_nonsplat:74; CHECK: // %bb.0:75; CHECK-NEXT: adrp x8, .LCPI4_076; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI4_0]77; CHECK-NEXT: add v0.4s, v0.4s, v1.4s78; CHECK-NEXT: ret79 %t0 = add <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8>80 %t1 = add <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2>81 ret <4 x i32> %t182}83 84; (x+c1)-c285 86define i32 @add_const_sub_const(i32 %arg) {87; CHECK-LABEL: add_const_sub_const:88; CHECK: // %bb.0:89; CHECK-NEXT: add w0, w0, #690; CHECK-NEXT: ret91 %t0 = add i32 %arg, 892 %t1 = sub i32 %t0, 293 ret i32 %t194}95 96define i32 @add_const_sub_const_extrause(i32 %arg) {97; CHECK-LABEL: add_const_sub_const_extrause:98; CHECK: // %bb.0:99; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill100; CHECK-NEXT: .cfi_def_cfa_offset 16101; CHECK-NEXT: .cfi_offset w19, -8102; CHECK-NEXT: .cfi_offset w30, -16103; CHECK-NEXT: mov w19, w0104; CHECK-NEXT: add w0, w0, #8105; CHECK-NEXT: bl use106; CHECK-NEXT: add w0, w19, #6107; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload108; CHECK-NEXT: ret109 %t0 = add i32 %arg, 8110 call void @use(i32 %t0)111 %t1 = sub i32 %t0, 2112 ret i32 %t1113}114 115define <4 x i32> @vec_add_const_sub_const(<4 x i32> %arg) {116; CHECK-LABEL: vec_add_const_sub_const:117; CHECK: // %bb.0:118; CHECK-NEXT: movi v1.4s, #6119; CHECK-NEXT: add v0.4s, v0.4s, v1.4s120; CHECK-NEXT: ret121 %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>122 %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>123 ret <4 x i32> %t1124}125 126define <4 x i32> @vec_add_const_sub_const_extrause(<4 x i32> %arg) {127; CHECK-LABEL: vec_add_const_sub_const_extrause:128; CHECK: // %bb.0:129; CHECK-NEXT: sub sp, sp, #32130; CHECK-NEXT: str x30, [sp, #16] // 8-byte Spill131; CHECK-NEXT: .cfi_def_cfa_offset 32132; CHECK-NEXT: .cfi_offset w30, -16133; CHECK-NEXT: movi v1.4s, #8134; CHECK-NEXT: str q0, [sp] // 16-byte Spill135; CHECK-NEXT: add v0.4s, v0.4s, v1.4s136; CHECK-NEXT: bl vec_use137; CHECK-NEXT: movi v0.4s, #6138; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload139; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Reload140; CHECK-NEXT: add v0.4s, v1.4s, v0.4s141; CHECK-NEXT: add sp, sp, #32142; CHECK-NEXT: ret143 %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>144 call void @vec_use(<4 x i32> %t0)145 %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>146 ret <4 x i32> %t1147}148 149define <4 x i32> @vec_add_const_sub_const_nonsplat(<4 x i32> %arg) {150; CHECK-LABEL: vec_add_const_sub_const_nonsplat:151; CHECK: // %bb.0:152; CHECK-NEXT: adrp x8, .LCPI9_0153; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI9_0]154; CHECK-NEXT: add v0.4s, v0.4s, v1.4s155; CHECK-NEXT: ret156 %t0 = add <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8>157 %t1 = sub <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2>158 ret <4 x i32> %t1159}160 161; c2-(x+c1)162 163define i32 @add_const_const_sub(i32 %arg) {164; CHECK-LABEL: add_const_const_sub:165; CHECK: // %bb.0:166; CHECK-NEXT: mov w8, #-6 // =0xfffffffa167; CHECK-NEXT: sub w0, w8, w0168; CHECK-NEXT: ret169 %t0 = add i32 %arg, 8170 %t1 = sub i32 2, %t0171 ret i32 %t1172}173 174define i32 @add_const_const_sub_extrause(i32 %arg) {175; CHECK-LABEL: add_const_const_sub_extrause:176; CHECK: // %bb.0:177; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill178; CHECK-NEXT: .cfi_def_cfa_offset 16179; CHECK-NEXT: .cfi_offset w19, -8180; CHECK-NEXT: .cfi_offset w30, -16181; CHECK-NEXT: mov w19, w0182; CHECK-NEXT: add w0, w0, #8183; CHECK-NEXT: bl use184; CHECK-NEXT: mov w8, #-6 // =0xfffffffa185; CHECK-NEXT: sub w0, w8, w19186; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload187; CHECK-NEXT: ret188 %t0 = add i32 %arg, 8189 call void @use(i32 %t0)190 %t1 = sub i32 2, %t0191 ret i32 %t1192}193 194define <4 x i32> @vec_add_const_const_sub(<4 x i32> %arg) {195; CHECK-LABEL: vec_add_const_const_sub:196; CHECK: // %bb.0:197; CHECK-NEXT: mvni v1.4s, #5198; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s199; CHECK-NEXT: ret200 %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>201 %t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0202 ret <4 x i32> %t1203}204 205define <4 x i32> @vec_add_const_const_sub_extrause(<4 x i32> %arg) {206; CHECK-LABEL: vec_add_const_const_sub_extrause:207; CHECK: // %bb.0:208; CHECK-NEXT: sub sp, sp, #32209; CHECK-NEXT: str x30, [sp, #16] // 8-byte Spill210; CHECK-NEXT: .cfi_def_cfa_offset 32211; CHECK-NEXT: .cfi_offset w30, -16212; CHECK-NEXT: movi v1.4s, #8213; CHECK-NEXT: str q0, [sp] // 16-byte Spill214; CHECK-NEXT: add v0.4s, v0.4s, v1.4s215; CHECK-NEXT: bl vec_use216; CHECK-NEXT: mvni v0.4s, #5217; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload218; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Reload219; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s220; CHECK-NEXT: add sp, sp, #32221; CHECK-NEXT: ret222 %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>223 call void @vec_use(<4 x i32> %t0)224 %t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0225 ret <4 x i32> %t1226}227 228define <4 x i32> @vec_add_const_const_sub_nonsplat(<4 x i32> %arg) {229; CHECK-LABEL: vec_add_const_const_sub_nonsplat:230; CHECK: // %bb.0:231; CHECK-NEXT: adrp x8, .LCPI14_0232; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_0]233; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s234; CHECK-NEXT: ret235 %t0 = add <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8>236 %t1 = sub <4 x i32> <i32 2, i32 3, i32 undef, i32 2>, %t0237 ret <4 x i32> %t1238}239 240; (x-c1)+c2241 242define i32 @sub_const_add_const(i32 %arg) {243; CHECK-LABEL: sub_const_add_const:244; CHECK: // %bb.0:245; CHECK-NEXT: sub w0, w0, #6246; CHECK-NEXT: ret247 %t0 = sub i32 %arg, 8248 %t1 = add i32 %t0, 2249 ret i32 %t1250}251 252define i32 @sub_const_add_const_extrause(i32 %arg) {253; CHECK-LABEL: sub_const_add_const_extrause:254; CHECK: // %bb.0:255; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill256; CHECK-NEXT: .cfi_def_cfa_offset 16257; CHECK-NEXT: .cfi_offset w19, -8258; CHECK-NEXT: .cfi_offset w30, -16259; CHECK-NEXT: mov w19, w0260; CHECK-NEXT: sub w0, w0, #8261; CHECK-NEXT: bl use262; CHECK-NEXT: sub w0, w19, #6263; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload264; CHECK-NEXT: ret265 %t0 = sub i32 %arg, 8266 call void @use(i32 %t0)267 %t1 = add i32 %t0, 2268 ret i32 %t1269}270 271define <4 x i32> @vec_sub_const_add_const(<4 x i32> %arg) {272; CHECK-LABEL: vec_sub_const_add_const:273; CHECK: // %bb.0:274; CHECK-NEXT: mvni v1.4s, #5275; CHECK-NEXT: add v0.4s, v0.4s, v1.4s276; CHECK-NEXT: ret277 %t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>278 %t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>279 ret <4 x i32> %t1280}281 282define <4 x i32> @vec_sub_const_add_const_extrause(<4 x i32> %arg) {283; CHECK-LABEL: vec_sub_const_add_const_extrause:284; CHECK: // %bb.0:285; CHECK-NEXT: sub sp, sp, #32286; CHECK-NEXT: str x30, [sp, #16] // 8-byte Spill287; CHECK-NEXT: .cfi_def_cfa_offset 32288; CHECK-NEXT: .cfi_offset w30, -16289; CHECK-NEXT: movi v1.4s, #8290; CHECK-NEXT: str q0, [sp] // 16-byte Spill291; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s292; CHECK-NEXT: bl vec_use293; CHECK-NEXT: mvni v0.4s, #5294; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload295; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Reload296; CHECK-NEXT: add v0.4s, v1.4s, v0.4s297; CHECK-NEXT: add sp, sp, #32298; CHECK-NEXT: ret299 %t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>300 call void @vec_use(<4 x i32> %t0)301 %t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>302 ret <4 x i32> %t1303}304 305define <4 x i32> @vec_sub_const_add_const_nonsplat(<4 x i32> %arg) {306; CHECK-LABEL: vec_sub_const_add_const_nonsplat:307; CHECK: // %bb.0:308; CHECK-NEXT: adrp x8, .LCPI19_0309; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI19_0]310; CHECK-NEXT: add v0.4s, v0.4s, v1.4s311; CHECK-NEXT: ret312 %t0 = sub <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8>313 %t1 = add <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2>314 ret <4 x i32> %t1315}316 317; (x-c1)-c2318 319define i32 @sub_const_sub_const(i32 %arg) {320; CHECK-LABEL: sub_const_sub_const:321; CHECK: // %bb.0:322; CHECK-NEXT: sub w0, w0, #10323; CHECK-NEXT: ret324 %t0 = sub i32 %arg, 8325 %t1 = sub i32 %t0, 2326 ret i32 %t1327}328 329define i32 @sub_const_sub_const_extrause(i32 %arg) {330; CHECK-LABEL: sub_const_sub_const_extrause:331; CHECK: // %bb.0:332; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill333; CHECK-NEXT: .cfi_def_cfa_offset 16334; CHECK-NEXT: .cfi_offset w19, -8335; CHECK-NEXT: .cfi_offset w30, -16336; CHECK-NEXT: mov w19, w0337; CHECK-NEXT: sub w0, w0, #8338; CHECK-NEXT: bl use339; CHECK-NEXT: sub w0, w19, #10340; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload341; CHECK-NEXT: ret342 %t0 = sub i32 %arg, 8343 call void @use(i32 %t0)344 %t1 = sub i32 %t0, 2345 ret i32 %t1346}347 348define <4 x i32> @vec_sub_const_sub_const(<4 x i32> %arg) {349; CHECK-LABEL: vec_sub_const_sub_const:350; CHECK: // %bb.0:351; CHECK-NEXT: movi v1.4s, #10352; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s353; CHECK-NEXT: ret354 %t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>355 %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>356 ret <4 x i32> %t1357}358 359define <4 x i32> @vec_sub_const_sub_const_extrause(<4 x i32> %arg) {360; CHECK-LABEL: vec_sub_const_sub_const_extrause:361; CHECK: // %bb.0:362; CHECK-NEXT: sub sp, sp, #32363; CHECK-NEXT: str x30, [sp, #16] // 8-byte Spill364; CHECK-NEXT: .cfi_def_cfa_offset 32365; CHECK-NEXT: .cfi_offset w30, -16366; CHECK-NEXT: movi v1.4s, #8367; CHECK-NEXT: str q0, [sp] // 16-byte Spill368; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s369; CHECK-NEXT: bl vec_use370; CHECK-NEXT: movi v0.4s, #10371; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload372; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Reload373; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s374; CHECK-NEXT: add sp, sp, #32375; CHECK-NEXT: ret376 %t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>377 call void @vec_use(<4 x i32> %t0)378 %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>379 ret <4 x i32> %t1380}381 382define <4 x i32> @vec_sub_const_sub_const_nonsplat(<4 x i32> %arg) {383; CHECK-LABEL: vec_sub_const_sub_const_nonsplat:384; CHECK: // %bb.0:385; CHECK-NEXT: adrp x8, .LCPI24_0386; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI24_0]387; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s388; CHECK-NEXT: ret389 %t0 = sub <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8>390 %t1 = sub <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2>391 ret <4 x i32> %t1392}393 394; c2-(x-c1)395 396define i32 @sub_const_const_sub(i32 %arg) {397; CHECK-LABEL: sub_const_const_sub:398; CHECK: // %bb.0:399; CHECK-NEXT: mov w8, #10 // =0xa400; CHECK-NEXT: sub w0, w8, w0401; CHECK-NEXT: ret402 %t0 = sub i32 %arg, 8403 %t1 = sub i32 2, %t0404 ret i32 %t1405}406 407define i32 @sub_const_const_sub_extrause(i32 %arg) {408; CHECK-LABEL: sub_const_const_sub_extrause:409; CHECK: // %bb.0:410; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill411; CHECK-NEXT: .cfi_def_cfa_offset 16412; CHECK-NEXT: .cfi_offset w19, -8413; CHECK-NEXT: .cfi_offset w30, -16414; CHECK-NEXT: mov w19, w0415; CHECK-NEXT: sub w0, w0, #8416; CHECK-NEXT: bl use417; CHECK-NEXT: mov w8, #10 // =0xa418; CHECK-NEXT: sub w0, w8, w19419; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload420; CHECK-NEXT: ret421 %t0 = sub i32 %arg, 8422 call void @use(i32 %t0)423 %t1 = sub i32 2, %t0424 ret i32 %t1425}426 427define <4 x i32> @vec_sub_const_const_sub(<4 x i32> %arg) {428; CHECK-LABEL: vec_sub_const_const_sub:429; CHECK: // %bb.0:430; CHECK-NEXT: movi v1.4s, #10431; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s432; CHECK-NEXT: ret433 %t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>434 %t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0435 ret <4 x i32> %t1436}437 438define <4 x i32> @vec_sub_const_const_sub_extrause(<4 x i32> %arg) {439; CHECK-LABEL: vec_sub_const_const_sub_extrause:440; CHECK: // %bb.0:441; CHECK-NEXT: sub sp, sp, #32442; CHECK-NEXT: str x30, [sp, #16] // 8-byte Spill443; CHECK-NEXT: .cfi_def_cfa_offset 32444; CHECK-NEXT: .cfi_offset w30, -16445; CHECK-NEXT: movi v1.4s, #8446; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s447; CHECK-NEXT: str q0, [sp] // 16-byte Spill448; CHECK-NEXT: bl vec_use449; CHECK-NEXT: movi v0.4s, #2450; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload451; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Reload452; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s453; CHECK-NEXT: add sp, sp, #32454; CHECK-NEXT: ret455 %t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>456 call void @vec_use(<4 x i32> %t0)457 %t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0458 ret <4 x i32> %t1459}460 461define <4 x i32> @vec_sub_const_const_sub_nonsplat(<4 x i32> %arg) {462; CHECK-LABEL: vec_sub_const_const_sub_nonsplat:463; CHECK: // %bb.0:464; CHECK-NEXT: adrp x8, .LCPI29_0465; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI29_0]466; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s467; CHECK-NEXT: ret468 %t0 = sub <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8>469 %t1 = sub <4 x i32> <i32 2, i32 3, i32 undef, i32 2>, %t0470 ret <4 x i32> %t1471}472 473; (c1-x)+c2474 475define i32 @const_sub_add_const(i32 %arg) {476; CHECK-LABEL: const_sub_add_const:477; CHECK: // %bb.0:478; CHECK-NEXT: mov w8, #10 // =0xa479; CHECK-NEXT: sub w0, w8, w0480; CHECK-NEXT: ret481 %t0 = sub i32 8, %arg482 %t1 = add i32 %t0, 2483 ret i32 %t1484}485 486define i32 @const_sub_add_const_extrause(i32 %arg) {487; CHECK-LABEL: const_sub_add_const_extrause:488; CHECK: // %bb.0:489; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill490; CHECK-NEXT: .cfi_def_cfa_offset 16491; CHECK-NEXT: .cfi_offset w19, -8492; CHECK-NEXT: .cfi_offset w30, -16493; CHECK-NEXT: mov w8, #8 // =0x8494; CHECK-NEXT: mov w19, w0495; CHECK-NEXT: sub w0, w8, w0496; CHECK-NEXT: bl use497; CHECK-NEXT: mov w8, #10 // =0xa498; CHECK-NEXT: sub w0, w8, w19499; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload500; CHECK-NEXT: ret501 %t0 = sub i32 8, %arg502 call void @use(i32 %t0)503 %t1 = add i32 %t0, 2504 ret i32 %t1505}506 507define <4 x i32> @vec_const_sub_add_const(<4 x i32> %arg) {508; CHECK-LABEL: vec_const_sub_add_const:509; CHECK: // %bb.0:510; CHECK-NEXT: movi v1.4s, #10511; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s512; CHECK-NEXT: ret513 %t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg514 %t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>515 ret <4 x i32> %t1516}517 518define <4 x i32> @vec_const_sub_add_const_extrause(<4 x i32> %arg) {519; CHECK-LABEL: vec_const_sub_add_const_extrause:520; CHECK: // %bb.0:521; CHECK-NEXT: sub sp, sp, #32522; CHECK-NEXT: str x30, [sp, #16] // 8-byte Spill523; CHECK-NEXT: .cfi_def_cfa_offset 32524; CHECK-NEXT: .cfi_offset w30, -16525; CHECK-NEXT: movi v1.4s, #8526; CHECK-NEXT: str q0, [sp] // 16-byte Spill527; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s528; CHECK-NEXT: bl vec_use529; CHECK-NEXT: movi v0.4s, #10530; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload531; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Reload532; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s533; CHECK-NEXT: add sp, sp, #32534; CHECK-NEXT: ret535 %t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg536 call void @vec_use(<4 x i32> %t0)537 %t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>538 ret <4 x i32> %t1539}540 541define <4 x i32> @vec_const_sub_add_const_nonsplat(<4 x i32> %arg) {542; CHECK-LABEL: vec_const_sub_add_const_nonsplat:543; CHECK: // %bb.0:544; CHECK-NEXT: adrp x8, .LCPI34_0545; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI34_0]546; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s547; CHECK-NEXT: ret548 %t0 = sub <4 x i32> <i32 21, i32 undef, i32 8, i32 8>, %arg549 %t1 = add <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2>550 ret <4 x i32> %t1551}552 553; (c1-x)-c2554 555define i32 @const_sub_sub_const(i32 %arg) {556; CHECK-LABEL: const_sub_sub_const:557; CHECK: // %bb.0:558; CHECK-NEXT: mov w8, #6 // =0x6559; CHECK-NEXT: sub w0, w8, w0560; CHECK-NEXT: ret561 %t0 = sub i32 8, %arg562 %t1 = sub i32 %t0, 2563 ret i32 %t1564}565 566define i32 @const_sub_sub_const_extrause(i32 %arg) {567; CHECK-LABEL: const_sub_sub_const_extrause:568; CHECK: // %bb.0:569; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill570; CHECK-NEXT: .cfi_def_cfa_offset 16571; CHECK-NEXT: .cfi_offset w19, -8572; CHECK-NEXT: .cfi_offset w30, -16573; CHECK-NEXT: mov w8, #8 // =0x8574; CHECK-NEXT: mov w19, w0575; CHECK-NEXT: sub w0, w8, w0576; CHECK-NEXT: bl use577; CHECK-NEXT: mov w8, #6 // =0x6578; CHECK-NEXT: sub w0, w8, w19579; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload580; CHECK-NEXT: ret581 %t0 = sub i32 8, %arg582 call void @use(i32 %t0)583 %t1 = sub i32 %t0, 2584 ret i32 %t1585}586 587define <4 x i32> @vec_const_sub_sub_const(<4 x i32> %arg) {588; CHECK-LABEL: vec_const_sub_sub_const:589; CHECK: // %bb.0:590; CHECK-NEXT: movi v1.4s, #6591; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s592; CHECK-NEXT: ret593 %t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg594 %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>595 ret <4 x i32> %t1596}597 598define <4 x i32> @vec_const_sub_sub_const_extrause(<4 x i32> %arg) {599; CHECK-LABEL: vec_const_sub_sub_const_extrause:600; CHECK: // %bb.0:601; CHECK-NEXT: sub sp, sp, #32602; CHECK-NEXT: str x30, [sp, #16] // 8-byte Spill603; CHECK-NEXT: .cfi_def_cfa_offset 32604; CHECK-NEXT: .cfi_offset w30, -16605; CHECK-NEXT: movi v1.4s, #8606; CHECK-NEXT: str q0, [sp] // 16-byte Spill607; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s608; CHECK-NEXT: bl vec_use609; CHECK-NEXT: movi v0.4s, #6610; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload611; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Reload612; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s613; CHECK-NEXT: add sp, sp, #32614; CHECK-NEXT: ret615 %t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg616 call void @vec_use(<4 x i32> %t0)617 %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>618 ret <4 x i32> %t1619}620 621define <4 x i32> @vec_const_sub_sub_const_nonsplat(<4 x i32> %arg) {622; CHECK-LABEL: vec_const_sub_sub_const_nonsplat:623; CHECK: // %bb.0:624; CHECK-NEXT: adrp x8, .LCPI39_0625; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI39_0]626; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s627; CHECK-NEXT: ret628 %t0 = sub <4 x i32> <i32 21, i32 undef, i32 8, i32 8>, %arg629 %t1 = sub <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2>630 ret <4 x i32> %t1631}632 633; c2-(c1-x)634 635define i32 @const_sub_const_sub(i32 %arg) {636; CHECK-LABEL: const_sub_const_sub:637; CHECK: // %bb.0:638; CHECK-NEXT: sub w0, w0, #6639; CHECK-NEXT: ret640 %t0 = sub i32 8, %arg641 %t1 = sub i32 2, %t0642 ret i32 %t1643}644 645define i32 @const_sub_const_sub_extrause(i32 %arg) {646; CHECK-LABEL: const_sub_const_sub_extrause:647; CHECK: // %bb.0:648; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill649; CHECK-NEXT: .cfi_def_cfa_offset 16650; CHECK-NEXT: .cfi_offset w19, -8651; CHECK-NEXT: .cfi_offset w30, -16652; CHECK-NEXT: mov w8, #8 // =0x8653; CHECK-NEXT: sub w19, w8, w0654; CHECK-NEXT: mov w0, w19655; CHECK-NEXT: bl use656; CHECK-NEXT: mov w8, #2 // =0x2657; CHECK-NEXT: sub w0, w8, w19658; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload659; CHECK-NEXT: ret660 %t0 = sub i32 8, %arg661 call void @use(i32 %t0)662 %t1 = sub i32 2, %t0663 ret i32 %t1664}665 666define <4 x i32> @vec_const_sub_const_sub(<4 x i32> %arg) {667; CHECK-LABEL: vec_const_sub_const_sub:668; CHECK: // %bb.0:669; CHECK-NEXT: mvni v1.4s, #5670; CHECK-NEXT: add v0.4s, v0.4s, v1.4s671; CHECK-NEXT: ret672 %t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg673 %t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0674 ret <4 x i32> %t1675}676 677define <4 x i32> @vec_const_sub_const_sub_extrause(<4 x i32> %arg) {678; CHECK-LABEL: vec_const_sub_const_sub_extrause:679; CHECK: // %bb.0:680; CHECK-NEXT: sub sp, sp, #32681; CHECK-NEXT: str x30, [sp, #16] // 8-byte Spill682; CHECK-NEXT: .cfi_def_cfa_offset 32683; CHECK-NEXT: .cfi_offset w30, -16684; CHECK-NEXT: movi v1.4s, #8685; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s686; CHECK-NEXT: str q0, [sp] // 16-byte Spill687; CHECK-NEXT: bl vec_use688; CHECK-NEXT: movi v0.4s, #2689; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload690; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Reload691; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s692; CHECK-NEXT: add sp, sp, #32693; CHECK-NEXT: ret694 %t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg695 call void @vec_use(<4 x i32> %t0)696 %t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0697 ret <4 x i32> %t1698}699 700define <4 x i32> @vec_const_sub_const_sub_nonsplat(<4 x i32> %arg) {701; CHECK-LABEL: vec_const_sub_const_sub_nonsplat:702; CHECK: // %bb.0:703; CHECK-NEXT: adrp x8, .LCPI44_0704; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI44_0]705; CHECK-NEXT: add v0.4s, v0.4s, v1.4s706; CHECK-NEXT: ret707 %t0 = sub <4 x i32> <i32 21, i32 undef, i32 8, i32 8>, %arg708 %t1 = sub <4 x i32> <i32 2, i32 3, i32 undef, i32 2>, %t0709 ret <4 x i32> %t1710}711