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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-none-elf < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64-none-elf -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define <2 x i32> @test_v2i64(<2 x i64> %n) {6; CHECK-SD-LABEL: test_v2i64:7; CHECK-SD: // %bb.0: // %entry8; CHECK-SD-NEXT: sshr v0.2d, v0.2d, #359; CHECK-SD-NEXT: xtn v0.2s, v0.2d10; CHECK-SD-NEXT: usra v0.2s, v0.2s, #3111; CHECK-SD-NEXT: ret12;13; CHECK-GI-LABEL: test_v2i64:14; CHECK-GI: // %bb.0: // %entry15; CHECK-GI-NEXT: ushr v1.2d, v0.2d, #6316; CHECK-GI-NEXT: sshr v0.2d, v0.2d, #3517; CHECK-GI-NEXT: xtn v1.2s, v1.2d18; CHECK-GI-NEXT: xtn v0.2s, v0.2d19; CHECK-GI-NEXT: add v0.2s, v1.2s, v0.2s20; CHECK-GI-NEXT: ret21entry:22 %shr = lshr <2 x i64> %n, splat (i64 63)23 %vmovn.i4 = trunc nuw nsw <2 x i64> %shr to <2 x i32>24 %shr1 = ashr <2 x i64> %n, splat (i64 35)25 %vmovn.i = trunc nsw <2 x i64> %shr1 to <2 x i32>26 %add = add nsw <2 x i32> %vmovn.i4, %vmovn.i27 ret <2 x i32> %add28}29 30define <4 x i16> @test_v4i32(<4 x i32> %n) {31; CHECK-SD-LABEL: test_v4i32:32; CHECK-SD: // %bb.0: // %entry33; CHECK-SD-NEXT: sshr v0.4s, v0.4s, #1734; CHECK-SD-NEXT: xtn v0.4h, v0.4s35; CHECK-SD-NEXT: usra v0.4h, v0.4h, #1536; CHECK-SD-NEXT: ret37;38; CHECK-GI-LABEL: test_v4i32:39; CHECK-GI: // %bb.0: // %entry40; CHECK-GI-NEXT: ushr v1.4s, v0.4s, #3141; CHECK-GI-NEXT: sshr v0.4s, v0.4s, #1742; CHECK-GI-NEXT: xtn v1.4h, v1.4s43; CHECK-GI-NEXT: xtn v0.4h, v0.4s44; CHECK-GI-NEXT: add v0.4h, v1.4h, v0.4h45; CHECK-GI-NEXT: ret46entry:47 %shr = lshr <4 x i32> %n, splat (i32 31)48 %vmovn.i4 = trunc nuw nsw <4 x i32> %shr to <4 x i16>49 %shr1 = ashr <4 x i32> %n, splat (i32 17)50 %vmovn.i = trunc nsw <4 x i32> %shr1 to <4 x i16>51 %add = add nsw <4 x i16> %vmovn.i4, %vmovn.i52 ret <4 x i16> %add53}54 55define <8 x i8> @test_v8i16(<8 x i16> %n) {56; CHECK-SD-LABEL: test_v8i16:57; CHECK-SD: // %bb.0: // %entry58; CHECK-SD-NEXT: sshr v0.8h, v0.8h, #959; CHECK-SD-NEXT: xtn v0.8b, v0.8h60; CHECK-SD-NEXT: usra v0.8b, v0.8b, #761; CHECK-SD-NEXT: ret62;63; CHECK-GI-LABEL: test_v8i16:64; CHECK-GI: // %bb.0: // %entry65; CHECK-GI-NEXT: ushr v1.8h, v0.8h, #1566; CHECK-GI-NEXT: sshr v0.8h, v0.8h, #967; CHECK-GI-NEXT: xtn v1.8b, v1.8h68; CHECK-GI-NEXT: xtn v0.8b, v0.8h69; CHECK-GI-NEXT: add v0.8b, v1.8b, v0.8b70; CHECK-GI-NEXT: ret71entry:72 %shr = lshr <8 x i16> %n, splat (i16 15)73 %vmovn.i4 = trunc nuw nsw <8 x i16> %shr to <8 x i8>74 %shr1 = ashr <8 x i16> %n, splat (i16 9)75 %vmovn.i = trunc nsw <8 x i16> %shr1 to <8 x i8>76 %add = add nsw <8 x i8> %vmovn.i4, %vmovn.i77 ret <8 x i8> %add78}79 80define <2 x i32> @test_v2i64_smallsrl(<2 x i64> %n) {81; CHECK-LABEL: test_v2i64_smallsrl:82; CHECK: // %bb.0: // %entry83; CHECK-NEXT: ushr v1.2d, v0.2d, #6284; CHECK-NEXT: sshr v0.2d, v0.2d, #3585; CHECK-NEXT: xtn v1.2s, v1.2d86; CHECK-NEXT: xtn v0.2s, v0.2d87; CHECK-NEXT: add v0.2s, v1.2s, v0.2s88; CHECK-NEXT: ret89entry:90 %shr = lshr <2 x i64> %n, splat (i64 62)91 %vmovn.i4 = trunc nuw nsw <2 x i64> %shr to <2 x i32>92 %shr1 = ashr <2 x i64> %n, splat (i64 35)93 %vmovn.i = trunc nsw <2 x i64> %shr1 to <2 x i32>94 %add = add nsw <2 x i32> %vmovn.i4, %vmovn.i95 ret <2 x i32> %add96}97 98define <2 x i32> @test_v2i64_smallsra(<2 x i64> %n) {99; CHECK-LABEL: test_v2i64_smallsra:100; CHECK: // %bb.0: // %entry101; CHECK-NEXT: ushr v1.2d, v0.2d, #63102; CHECK-NEXT: shrn v0.2s, v0.2d, #27103; CHECK-NEXT: xtn v1.2s, v1.2d104; CHECK-NEXT: add v0.2s, v1.2s, v0.2s105; CHECK-NEXT: ret106entry:107 %shr = lshr <2 x i64> %n, splat (i64 63)108 %vmovn.i4 = trunc nuw nsw <2 x i64> %shr to <2 x i32>109 %shr1 = ashr <2 x i64> %n, splat (i64 27)110 %vmovn.i = trunc nsw <2 x i64> %shr1 to <2 x i32>111 %add = add nsw <2 x i32> %vmovn.i4, %vmovn.i112 ret <2 x i32> %add113}114 115