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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 32# RUN: llc -run-pass=machine-scheduler %s -o - | FileCheck %s3# RUN: llc -passes=machine-scheduler %s -o - | FileCheck %s4 5--- |6 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"7 target triple = "aarch64"8 9 define i32 @test_add(ptr %0) #0 {10 %2 = ptrtoint ptr %0 to i6411 %3 = and i64 %2, -6412 %4 = inttoptr i64 %3 to ptr13 %5 = load i32, ptr %4, align 6414 %6 = getelementptr inbounds i32, ptr %4, i64 115 %7 = load i32, ptr %6, align 416 %8 = add nsw i32 %7, %517 ret i32 %818 }19 20 attributes #0 = { "target-cpu"="ampere1" }21 22...23---24name: test_add25tracksRegLiveness: true26registers:27 - { id: 0, class: gpr64, preferred-register: '' }28 - { id: 1, class: gpr64sp, preferred-register: '' }29 - { id: 2, class: gpr32, preferred-register: '' }30 - { id: 3, class: gpr32, preferred-register: '' }31 - { id: 4, class: gpr32, preferred-register: '' }32liveins:33 - { reg: '$x0', virtual-reg: '%0' }34body: |35 bb.0 (%ir-block.1):36 liveins: $x037 38 ; CHECK-LABEL: name: test_add39 ; CHECK: liveins: $x040 ; CHECK-NEXT: {{ $}}41 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x042 ; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[COPY]], 786543 ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[ANDXri]], 0 :: (load (s32) from %ir.4, align 64)44 ; CHECK-NEXT: [[LDRWui1:%[0-9]+]]:gpr32 = LDRWui [[ANDXri]], 1 :: (load (s32) from %ir.6)45 ; CHECK-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = nsw ADDWrr [[LDRWui1]], [[LDRWui]]46 ; CHECK-NEXT: $w0 = COPY [[ADDWrr]]47 ; CHECK-NEXT: RET_ReallyLR implicit $w048 %0:gpr64 = COPY $x049 %1:gpr64sp = ANDXri %0, 786550 %2:gpr32 = LDRWui %1, 0 :: (load (s32) from %ir.4, align 64)51 %3:gpr32 = LDRWui %1, 1 :: (load (s32) from %ir.6)52 %4:gpr32 = nsw ADDWrr %3, %253 $w0 = COPY %454 RET_ReallyLR implicit $w055 56...57