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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-enable-collect-loh=false -aarch64-enable-sink-fold=true < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-enable-collect-loh=false -aarch64-enable-sink-fold=true -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5@board = common global [400 x i8] zeroinitializer, align 16@next_string = common global i32 0, align 47@string_number = common global [400 x i32] zeroinitializer, align 48 9; Function Attrs: nounwind ssp10define void @new_position(i32 %pos) {11; CHECK-SD-LABEL: new_position:12; CHECK-SD: ; %bb.0: ; %entry13; CHECK-SD-NEXT: adrp x8, _board@GOTPAGE14; CHECK-SD-NEXT: ldr x8, [x8, _board@GOTPAGEOFF]15; CHECK-SD-NEXT: ldrb w8, [x8, w0, sxtw]16; CHECK-SD-NEXT: sub w8, w8, #117; CHECK-SD-NEXT: cmp w8, #118; CHECK-SD-NEXT: b.hi LBB0_219; CHECK-SD-NEXT: ; %bb.1: ; %if.then20; CHECK-SD-NEXT: adrp x8, _next_string@GOTPAGE21; CHECK-SD-NEXT: adrp x9, _string_number@GOTPAGE22; CHECK-SD-NEXT: ldr x8, [x8, _next_string@GOTPAGEOFF]23; CHECK-SD-NEXT: ldr x9, [x9, _string_number@GOTPAGEOFF]24; CHECK-SD-NEXT: ldr w8, [x8]25; CHECK-SD-NEXT: str w8, [x9, w0, sxtw #2]26; CHECK-SD-NEXT: LBB0_2: ; %if.end27; CHECK-SD-NEXT: ret28;29; CHECK-GI-LABEL: new_position:30; CHECK-GI: ; %bb.0: ; %entry31; CHECK-GI-NEXT: adrp x8, _board@GOTPAGE32; CHECK-GI-NEXT: ldr x8, [x8, _board@GOTPAGEOFF]33; CHECK-GI-NEXT: ldrb w8, [x8, w0, sxtw]34; CHECK-GI-NEXT: sub w8, w8, #135; CHECK-GI-NEXT: cmp w8, #236; CHECK-GI-NEXT: b.hs LBB0_237; CHECK-GI-NEXT: ; %bb.1: ; %if.then38; CHECK-GI-NEXT: adrp x8, _next_string@GOTPAGE39; CHECK-GI-NEXT: adrp x9, _string_number@GOTPAGE40; CHECK-GI-NEXT: ldr x8, [x8, _next_string@GOTPAGEOFF]41; CHECK-GI-NEXT: ldr x9, [x9, _string_number@GOTPAGEOFF]42; CHECK-GI-NEXT: ldr w8, [x8]43; CHECK-GI-NEXT: str w8, [x9, w0, sxtw #2]44; CHECK-GI-NEXT: LBB0_2: ; %if.end45; CHECK-GI-NEXT: ret46entry:47 %idxprom = sext i32 %pos to i6448 %arrayidx = getelementptr inbounds [400 x i8], ptr @board, i64 0, i64 %idxprom49 %tmp = load i8, ptr %arrayidx, align 150 %.off = add i8 %tmp, -151 %switch = icmp ult i8 %.off, 252 br i1 %switch, label %if.then, label %if.end53 54if.then: ; preds = %entry55 %tmp1 = load i32, ptr @next_string, align 456 %arrayidx8 = getelementptr inbounds [400 x i32], ptr @string_number, i64 0, i64 %idxprom57 store i32 %tmp1, ptr %arrayidx8, align 458 br label %if.end59 60if.end: ; preds = %if.then, %entry61 ret void62}63 64define zeroext i1 @test8_0(i8 zeroext %x) align 2 {65; CHECK-LABEL: test8_0:66; CHECK: ; %bb.0: ; %entry67; CHECK-NEXT: sub w8, w0, #18268; CHECK-NEXT: cmn w8, #2069; CHECK-NEXT: cset w0, lo70; CHECK-NEXT: ret71entry:72 %0 = add i8 %x, 7473 %1 = icmp ult i8 %0, -2074 br i1 %1, label %ret_true, label %ret_false75ret_false:76 ret i1 false77ret_true:78 ret i1 true79}80 81define zeroext i1 @test8_1(i8 zeroext %x) align 2 {82; CHECK-SD-LABEL: test8_1:83; CHECK-SD: ; %bb.0: ; %entry84; CHECK-SD-NEXT: sub w8, w0, #1085; CHECK-SD-NEXT: cmp w8, #8986; CHECK-SD-NEXT: cset w0, hi87; CHECK-SD-NEXT: ret88;89; CHECK-GI-LABEL: test8_1:90; CHECK-GI: ; %bb.0: ; %entry91; CHECK-GI-NEXT: sub w8, w0, #1092; CHECK-GI-NEXT: cmp w8, #9093; CHECK-GI-NEXT: cset w0, hs94; CHECK-GI-NEXT: ret95entry:96 %0 = add i8 %x, 24697 %1 = icmp uge i8 %0, 9098 br i1 %1, label %ret_true, label %ret_false99ret_false:100 ret i1 false101ret_true:102 ret i1 true103}104 105define zeroext i1 @test8_2(i8 zeroext %x) align 2 {106; CHECK-SD-LABEL: test8_2:107; CHECK-SD: ; %bb.0: ; %entry108; CHECK-SD-NEXT: cmp w0, #208109; CHECK-SD-NEXT: cset w0, ne110; CHECK-SD-NEXT: ret111;112; CHECK-GI-LABEL: test8_2:113; CHECK-GI: ; %bb.0: ; %entry114; CHECK-GI-NEXT: sub w8, w0, #29115; CHECK-GI-NEXT: and w8, w8, #0xff116; CHECK-GI-NEXT: cmp w8, #179117; CHECK-GI-NEXT: cset w0, ne118; CHECK-GI-NEXT: ret119entry:120 %0 = add i8 %x, 227121 %1 = icmp ne i8 %0, 179122 br i1 %1, label %ret_true, label %ret_false123ret_false:124 ret i1 false125ret_true:126 ret i1 true127}128 129define zeroext i1 @test8_3(i8 zeroext %x) align 2 {130; CHECK-SD-LABEL: test8_3:131; CHECK-SD: ; %bb.0: ; %entry132; CHECK-SD-NEXT: cmp w0, #209133; CHECK-SD-NEXT: cset w0, eq134; CHECK-SD-NEXT: ret135;136; CHECK-GI-LABEL: test8_3:137; CHECK-GI: ; %bb.0: ; %entry138; CHECK-GI-NEXT: sub w8, w0, #55139; CHECK-GI-NEXT: and w8, w8, #0xff140; CHECK-GI-NEXT: cmp w8, #154141; CHECK-GI-NEXT: cset w0, eq142; CHECK-GI-NEXT: ret143entry:144 %0 = add i8 %x, 201145 %1 = icmp eq i8 %0, 154146 br i1 %1, label %ret_true, label %ret_false147ret_false:148 ret i1 false149ret_true:150 ret i1 true151}152 153define zeroext i1 @test8_4(i8 zeroext %x) align 2 {154; CHECK-SD-LABEL: test8_4:155; CHECK-SD: ; %bb.0: ; %entry156; CHECK-SD-NEXT: cmp w0, #39157; CHECK-SD-NEXT: cset w0, ne158; CHECK-SD-NEXT: ret159;160; CHECK-GI-LABEL: test8_4:161; CHECK-GI: ; %bb.0: ; %entry162; CHECK-GI-NEXT: sub w8, w0, #79163; CHECK-GI-NEXT: and w8, w8, #0xff164; CHECK-GI-NEXT: cmp w8, #216165; CHECK-GI-NEXT: cset w0, ne166; CHECK-GI-NEXT: ret167entry:168 %0 = add i8 %x, -79169 %1 = icmp ne i8 %0, -40170 br i1 %1, label %ret_true, label %ret_false171ret_false:172 ret i1 false173ret_true:174 ret i1 true175}176 177define zeroext i1 @test8_5(i8 zeroext %x) align 2 {178; CHECK-SD-LABEL: test8_5:179; CHECK-SD: ; %bb.0: ; %entry180; CHECK-SD-NEXT: sub w8, w0, #123181; CHECK-SD-NEXT: cmn w8, #106182; CHECK-SD-NEXT: cset w0, hi183; CHECK-SD-NEXT: ret184;185; CHECK-GI-LABEL: test8_5:186; CHECK-GI: ; %bb.0: ; %entry187; CHECK-GI-NEXT: sub w8, w0, #123188; CHECK-GI-NEXT: cmn w8, #105189; CHECK-GI-NEXT: cset w0, hs190; CHECK-GI-NEXT: ret191entry:192 %0 = add i8 %x, 133193 %1 = icmp uge i8 %0, -105194 br i1 %1, label %ret_true, label %ret_false195ret_false:196 ret i1 false197ret_true:198 ret i1 true199}200 201define zeroext i1 @test8_6(i8 zeroext %x) align 2 {202; CHECK-SD-LABEL: test8_6:203; CHECK-SD: ; %bb.0: ; %entry204; CHECK-SD-NEXT: sub w8, w0, #58205; CHECK-SD-NEXT: cmp w8, #154206; CHECK-SD-NEXT: cset w0, hi207; CHECK-SD-NEXT: ret208;209; CHECK-GI-LABEL: test8_6:210; CHECK-GI: ; %bb.0: ; %entry211; CHECK-GI-NEXT: sub w8, w0, #58212; CHECK-GI-NEXT: cmp w8, #155213; CHECK-GI-NEXT: cset w0, hs214; CHECK-GI-NEXT: ret215entry:216 %0 = add i8 %x, -58217 %1 = icmp uge i8 %0, 155218 br i1 %1, label %ret_true, label %ret_false219ret_false:220 ret i1 false221ret_true:222 ret i1 true223}224 225define zeroext i1 @test8_7(i8 zeroext %x) align 2 {226; CHECK-LABEL: test8_7:227; CHECK: ; %bb.0: ; %entry228; CHECK-NEXT: sub w8, w0, #31229; CHECK-NEXT: cmp w8, #124230; CHECK-NEXT: cset w0, lo231; CHECK-NEXT: ret232entry:233 %0 = add i8 %x, 225234 %1 = icmp ult i8 %0, 124235 br i1 %1, label %ret_true, label %ret_false236ret_false:237 ret i1 false238ret_true:239 ret i1 true240}241 242 243 244define zeroext i1 @test8_8(i8 zeroext %x) align 2 {245; CHECK-SD-LABEL: test8_8:246; CHECK-SD: ; %bb.0: ; %entry247; CHECK-SD-NEXT: cmp w0, #66248; CHECK-SD-NEXT: cset w0, ne249; CHECK-SD-NEXT: ret250;251; CHECK-GI-LABEL: test8_8:252; CHECK-GI: ; %bb.0: ; %entry253; CHECK-GI-NEXT: sub w8, w0, #66254; CHECK-GI-NEXT: cmp w8, #1255; CHECK-GI-NEXT: cset w0, hs256; CHECK-GI-NEXT: ret257entry:258 %0 = add i8 %x, 190259 %1 = icmp uge i8 %0, 1260 br i1 %1, label %ret_true, label %ret_false261ret_false:262 ret i1 false263ret_true:264 ret i1 true265}266 267define zeroext i1 @test16_0(i16 zeroext %x) align 2 {268; CHECK-SD-LABEL: test16_0:269; CHECK-SD: ; %bb.0: ; %entry270; CHECK-SD-NEXT: mov w8, #5086 ; =0x13de271; CHECK-SD-NEXT: cmp w0, w8272; CHECK-SD-NEXT: cset w0, ne273; CHECK-SD-NEXT: ret274;275; CHECK-GI-LABEL: test16_0:276; CHECK-GI: ; %bb.0: ; %entry277; CHECK-GI-NEXT: mov w8, #18547 ; =0x4873278; CHECK-GI-NEXT: mov w9, #23633 ; =0x5c51279; CHECK-GI-NEXT: add w8, w0, w8280; CHECK-GI-NEXT: cmp w9, w8, uxth281; CHECK-GI-NEXT: cset w0, ne282; CHECK-GI-NEXT: ret283entry:284 %0 = add i16 %x, -46989285 %1 = icmp ne i16 %0, -41903286 br i1 %1, label %ret_true, label %ret_false287ret_false:288 ret i1 false289ret_true:290 ret i1 true291}292 293define zeroext i1 @test16_2(i16 zeroext %x) align 2 {294; CHECK-SD-LABEL: test16_2:295; CHECK-SD: ; %bb.0: ; %entry296; CHECK-SD-NEXT: mov w8, #16882 ; =0x41f2297; CHECK-SD-NEXT: mov w9, #40700 ; =0x9efc298; CHECK-SD-NEXT: add w8, w0, w8299; CHECK-SD-NEXT: cmp w9, w8, uxth300; CHECK-SD-NEXT: cset w0, hi301; CHECK-SD-NEXT: ret302;303; CHECK-GI-LABEL: test16_2:304; CHECK-GI: ; %bb.0: ; %entry305; CHECK-GI-NEXT: mov w8, #16882 ; =0x41f2306; CHECK-GI-NEXT: mov w9, #40699 ; =0x9efb307; CHECK-GI-NEXT: add w8, w0, w8308; CHECK-GI-NEXT: cmp w9, w8, uxth309; CHECK-GI-NEXT: cset w0, hs310; CHECK-GI-NEXT: ret311entry:312 %0 = add i16 %x, 16882313 %1 = icmp ule i16 %0, -24837314 br i1 %1, label %ret_true, label %ret_false315ret_false:316 ret i1 false317ret_true:318 ret i1 true319}320 321define zeroext i1 @test16_3(i16 zeroext %x) align 2 {322; CHECK-SD-LABEL: test16_3:323; CHECK-SD: ; %bb.0: ; %entry324; CHECK-SD-NEXT: mov w8, #53200 ; =0xcfd0325; CHECK-SD-NEXT: cmp w0, w8326; CHECK-SD-NEXT: cset w0, ne327; CHECK-SD-NEXT: ret328;329; CHECK-GI-LABEL: test16_3:330; CHECK-GI: ; %bb.0: ; %entry331; CHECK-GI-NEXT: mov w8, #29283 ; =0x7263332; CHECK-GI-NEXT: mov w9, #16947 ; =0x4233333; CHECK-GI-NEXT: add w8, w0, w8334; CHECK-GI-NEXT: cmp w9, w8, uxth335; CHECK-GI-NEXT: cset w0, ne336; CHECK-GI-NEXT: ret337entry:338 %0 = add i16 %x, 29283339 %1 = icmp ne i16 %0, 16947340 br i1 %1, label %ret_true, label %ret_false341ret_false:342 ret i1 false343ret_true:344 ret i1 true345}346 347define zeroext i1 @test16_4(i16 zeroext %x) align 2 {348; CHECK-SD-LABEL: test16_4:349; CHECK-SD: ; %bb.0: ; %entry350; CHECK-SD-NEXT: mov w8, #29985 ; =0x7521351; CHECK-SD-NEXT: mov w9, #15676 ; =0x3d3c352; CHECK-SD-NEXT: add w8, w0, w8353; CHECK-SD-NEXT: cmp w9, w8, uxth354; CHECK-SD-NEXT: cset w0, lo355; CHECK-SD-NEXT: ret356;357; CHECK-GI-LABEL: test16_4:358; CHECK-GI: ; %bb.0: ; %entry359; CHECK-GI-NEXT: mov w8, #29985 ; =0x7521360; CHECK-GI-NEXT: mov w9, #15677 ; =0x3d3d361; CHECK-GI-NEXT: add w8, w0, w8362; CHECK-GI-NEXT: cmp w9, w8, uxth363; CHECK-GI-NEXT: cset w0, ls364; CHECK-GI-NEXT: ret365entry:366 %0 = add i16 %x, -35551367 %1 = icmp uge i16 %0, 15677368 br i1 %1, label %ret_true, label %ret_false369ret_false:370 ret i1 false371ret_true:372 ret i1 true373}374 375define zeroext i1 @test16_5(i16 zeroext %x) align 2 {376; CHECK-SD-LABEL: test16_5:377; CHECK-SD: ; %bb.0: ; %entry378; CHECK-SD-NEXT: mov w8, #23282 ; =0x5af2379; CHECK-SD-NEXT: cmp w0, w8380; CHECK-SD-NEXT: cset w0, ne381; CHECK-SD-NEXT: ret382;383; CHECK-GI-LABEL: test16_5:384; CHECK-GI: ; %bb.0: ; %entry385; CHECK-GI-NEXT: mov w8, #-25214 ; =0xffff9d82386; CHECK-GI-NEXT: mov w9, #63604 ; =0xf874387; CHECK-GI-NEXT: add w8, w0, w8388; CHECK-GI-NEXT: cmp w9, w8, uxth389; CHECK-GI-NEXT: cset w0, ne390; CHECK-GI-NEXT: ret391entry:392 %0 = add i16 %x, -25214393 %1 = icmp ne i16 %0, -1932394 br i1 %1, label %ret_true, label %ret_false395ret_false:396 ret i1 false397ret_true:398 ret i1 true399}400 401define zeroext i1 @test16_6(i16 zeroext %x) align 2 {402; CHECK-SD-LABEL: test16_6:403; CHECK-SD: ; %bb.0: ; %entry404; CHECK-SD-NEXT: mov w8, #-32194 ; =0xffff823e405; CHECK-SD-NEXT: mov w9, #24320 ; =0x5f00406; CHECK-SD-NEXT: add w8, w0, w8407; CHECK-SD-NEXT: cmp w8, w9408; CHECK-SD-NEXT: cset w0, hi409; CHECK-SD-NEXT: ret410;411; CHECK-GI-LABEL: test16_6:412; CHECK-GI: ; %bb.0: ; %entry413; CHECK-GI-NEXT: mov w8, #-32194 ; =0xffff823e414; CHECK-GI-NEXT: mov w9, #24321 ; =0x5f01415; CHECK-GI-NEXT: add w8, w0, w8416; CHECK-GI-NEXT: cmp w8, w9417; CHECK-GI-NEXT: cset w0, hs418; CHECK-GI-NEXT: ret419entry:420 %0 = add i16 %x, -32194421 %1 = icmp uge i16 %0, -41215422 br i1 %1, label %ret_true, label %ret_false423ret_false:424 ret i1 false425ret_true:426 ret i1 true427}428 429define zeroext i1 @test16_7(i16 zeroext %x) align 2 {430; CHECK-SD-LABEL: test16_7:431; CHECK-SD: ; %bb.0: ; %entry432; CHECK-SD-NEXT: mov w8, #9272 ; =0x2438433; CHECK-SD-NEXT: mov w9, #22619 ; =0x585b434; CHECK-SD-NEXT: add w8, w0, w8435; CHECK-SD-NEXT: cmp w9, w8, uxth436; CHECK-SD-NEXT: cset w0, lo437; CHECK-SD-NEXT: ret438;439; CHECK-GI-LABEL: test16_7:440; CHECK-GI: ; %bb.0: ; %entry441; CHECK-GI-NEXT: mov w8, #9272 ; =0x2438442; CHECK-GI-NEXT: mov w9, #22620 ; =0x585c443; CHECK-GI-NEXT: add w8, w0, w8444; CHECK-GI-NEXT: cmp w9, w8, uxth445; CHECK-GI-NEXT: cset w0, ls446; CHECK-GI-NEXT: ret447entry:448 %0 = add i16 %x, 9272449 %1 = icmp uge i16 %0, -42916450 br i1 %1, label %ret_true, label %ret_false451ret_false:452 ret i1 false453ret_true:454 ret i1 true455}456 457define zeroext i1 @test16_8(i16 zeroext %x) align 2 {458; CHECK-SD-LABEL: test16_8:459; CHECK-SD: ; %bb.0: ; %entry460; CHECK-SD-NEXT: mov w8, #4919 ; =0x1337461; CHECK-SD-NEXT: cmp w0, w8462; CHECK-SD-NEXT: cset w0, ne463; CHECK-SD-NEXT: ret464;465; CHECK-GI-LABEL: test16_8:466; CHECK-GI: ; %bb.0: ; %entry467; CHECK-GI-NEXT: mov w8, #6706 ; =0x1a32468; CHECK-GI-NEXT: add w9, w0, #1787469; CHECK-GI-NEXT: cmp w8, w9, uxth470; CHECK-GI-NEXT: cset w0, ne471; CHECK-GI-NEXT: ret472entry:473 %0 = add i16 %x, -63749474 %1 = icmp ne i16 %0, 6706475 br i1 %1, label %ret_true, label %ret_false476ret_false:477 ret i1 false478ret_true:479 ret i1 true480}481 482define i64 @pr58109(i8 signext %0) {483; CHECK-SD-LABEL: pr58109:484; CHECK-SD: ; %bb.0:485; CHECK-SD-NEXT: add w8, w0, #1486; CHECK-SD-NEXT: and w8, w8, #0xff487; CHECK-SD-NEXT: subs w8, w8, #1488; CHECK-SD-NEXT: csel w0, wzr, w8, lo489; CHECK-SD-NEXT: ret490;491; CHECK-GI-LABEL: pr58109:492; CHECK-GI: ; %bb.0:493; CHECK-GI-NEXT: add w8, w0, #1494; CHECK-GI-NEXT: and w8, w8, #0xff495; CHECK-GI-NEXT: sub w8, w8, #1496; CHECK-GI-NEXT: cmp w8, w8, uxtb497; CHECK-GI-NEXT: csel w8, wzr, w8, ne498; CHECK-GI-NEXT: and x0, x8, #0xff499; CHECK-GI-NEXT: ret500 %2 = add i8 %0, 1501 %3 = call i8 @llvm.usub.sat.i8(i8 %2, i8 1)502 %4 = zext i8 %3 to i64503 ret i64 %4504}505 506define i64 @pr58109b(i8 signext %0, i64 %a, i64 %b) {507; CHECK-SD-LABEL: pr58109b:508; CHECK-SD: ; %bb.0:509; CHECK-SD-NEXT: and w8, w0, #0xff510; CHECK-SD-NEXT: sub w8, w8, #255511; CHECK-SD-NEXT: cmn w8, #254512; CHECK-SD-NEXT: csel x0, x1, x2, lo513; CHECK-SD-NEXT: ret514;515; CHECK-GI-LABEL: pr58109b:516; CHECK-GI: ; %bb.0:517; CHECK-GI-NEXT: mov w8, #-255 ; =0xffffff01518; CHECK-GI-NEXT: add w8, w8, w0, uxtb519; CHECK-GI-NEXT: cmn w8, #254520; CHECK-GI-NEXT: csel x0, x1, x2, lo521; CHECK-GI-NEXT: ret522 %2 = add i8 %0, 1523 %3 = icmp ult i8 %2, 2524 %4 = select i1 %3, i64 %a, i64 %b525 ret i64 %4526}527 528define i64 @test_2_selects(i8 zeroext %a) {529; CHECK-LABEL: test_2_selects:530; CHECK: ; %bb.0:531; CHECK-NEXT: add w9, w0, #24532; CHECK-NEXT: mov w8, #131 ; =0x83533; CHECK-NEXT: and w9, w9, #0xff534; CHECK-NEXT: cmp w9, #81535; CHECK-NEXT: mov w9, #57 ; =0x39536; CHECK-NEXT: csel x8, x8, xzr, lo537; CHECK-NEXT: csel x9, xzr, x9, eq538; CHECK-NEXT: add x0, x8, x9539; CHECK-NEXT: ret540 %1 = add i8 %a, 24541 %2 = zext i8 %1 to i64542 %3 = icmp ult i8 %1, 81543 %4 = select i1 %3, i64 131, i64 0544 %5 = icmp eq i8 %1, 81545 %6 = select i1 %5, i64 0, i64 57546 %7 = add i64 %4, %6547 ret i64 %7548}549 550declare i8 @llvm.usub.sat.i8(i8, i8) #0551 552define i64 @and0xffffffff(i64 %a) nounwind ssp {553; CHECK-LABEL: and0xffffffff:554; CHECK: ; %bb.0: ; %entry555; CHECK-NEXT: mov w0, w0556; CHECK-NEXT: ret557entry:558 %b = and i64 %a, u0xffffffff559 ret i64 %b560}561 562define i64 @and0xfffffff0(i64 %a) nounwind ssp {563; CHECK-LABEL: and0xfffffff0:564; CHECK: ; %bb.0: ; %entry565; CHECK-NEXT: and x0, x0, #0xfffffff0566; CHECK-NEXT: ret567entry:568 %b = and i64 %a, u0xfffffff0569 ret i64 %b570}571 572define i64 @and0x7fffffff(i64 %a) nounwind ssp {573; CHECK-LABEL: and0x7fffffff:574; CHECK: ; %bb.0: ; %entry575; CHECK-NEXT: and x0, x0, #0x7fffffff576; CHECK-NEXT: ret577entry:578 %b = and i64 %a, u0x7fffffff579 ret i64 %b580}581