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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-none-elf -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64-none-elf -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define i32 @and_eq_eq(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {6; CHECK-SD-LABEL: and_eq_eq:7; CHECK-SD: // %bb.0: // %entry8; CHECK-SD-NEXT: cmp w0, w19; CHECK-SD-NEXT: ccmp w2, w3, #0, eq10; CHECK-SD-NEXT: cset w0, eq11; CHECK-SD-NEXT: ret12;13; CHECK-GI-LABEL: and_eq_eq:14; CHECK-GI: // %bb.0: // %entry15; CHECK-GI-NEXT: cmp w0, w116; CHECK-GI-NEXT: cset w8, eq17; CHECK-GI-NEXT: cmp w2, w318; CHECK-GI-NEXT: cset w9, eq19; CHECK-GI-NEXT: and w0, w8, w920; CHECK-GI-NEXT: ret21entry:22 %c0 = icmp eq i32 %s0, %s123 %c1 = icmp eq i32 %s2, %s324 %a = and i1 %c0, %c125 %z = zext i1 %a to i3226 ret i32 %z27}28 29define i32 @and_eq_ne(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {30; CHECK-SD-LABEL: and_eq_ne:31; CHECK-SD: // %bb.0: // %entry32; CHECK-SD-NEXT: cmp w0, w133; CHECK-SD-NEXT: ccmp w2, w3, #4, eq34; CHECK-SD-NEXT: cset w0, ne35; CHECK-SD-NEXT: ret36;37; CHECK-GI-LABEL: and_eq_ne:38; CHECK-GI: // %bb.0: // %entry39; CHECK-GI-NEXT: cmp w0, w140; CHECK-GI-NEXT: cset w8, eq41; CHECK-GI-NEXT: cmp w2, w342; CHECK-GI-NEXT: cset w9, ne43; CHECK-GI-NEXT: and w0, w8, w944; CHECK-GI-NEXT: ret45entry:46 %c0 = icmp eq i32 %s0, %s147 %c1 = icmp ne i32 %s2, %s348 %a = and i1 %c0, %c149 %z = zext i1 %a to i3250 ret i32 %z51}52 53define i32 @and_eq_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {54; CHECK-SD-LABEL: and_eq_ult:55; CHECK-SD: // %bb.0: // %entry56; CHECK-SD-NEXT: cmp w0, w157; CHECK-SD-NEXT: ccmp w2, w3, #2, eq58; CHECK-SD-NEXT: cset w0, lo59; CHECK-SD-NEXT: ret60;61; CHECK-GI-LABEL: and_eq_ult:62; CHECK-GI: // %bb.0: // %entry63; CHECK-GI-NEXT: cmp w0, w164; CHECK-GI-NEXT: cset w8, eq65; CHECK-GI-NEXT: cmp w2, w366; CHECK-GI-NEXT: cset w9, lo67; CHECK-GI-NEXT: and w0, w8, w968; CHECK-GI-NEXT: ret69entry:70 %c0 = icmp eq i32 %s0, %s171 %c1 = icmp ult i32 %s2, %s372 %a = and i1 %c0, %c173 %z = zext i1 %a to i3274 ret i32 %z75}76 77define i32 @and_eq_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {78; CHECK-SD-LABEL: and_eq_ule:79; CHECK-SD: // %bb.0: // %entry80; CHECK-SD-NEXT: cmp w0, w181; CHECK-SD-NEXT: ccmp w2, w3, #2, eq82; CHECK-SD-NEXT: cset w0, ls83; CHECK-SD-NEXT: ret84;85; CHECK-GI-LABEL: and_eq_ule:86; CHECK-GI: // %bb.0: // %entry87; CHECK-GI-NEXT: cmp w0, w188; CHECK-GI-NEXT: cset w8, eq89; CHECK-GI-NEXT: cmp w2, w390; CHECK-GI-NEXT: cset w9, ls91; CHECK-GI-NEXT: and w0, w8, w992; CHECK-GI-NEXT: ret93entry:94 %c0 = icmp eq i32 %s0, %s195 %c1 = icmp ule i32 %s2, %s396 %a = and i1 %c0, %c197 %z = zext i1 %a to i3298 ret i32 %z99}100 101define i32 @and_eq_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {102; CHECK-SD-LABEL: and_eq_ugt:103; CHECK-SD: // %bb.0: // %entry104; CHECK-SD-NEXT: cmp w0, w1105; CHECK-SD-NEXT: ccmp w2, w3, #0, eq106; CHECK-SD-NEXT: cset w0, hi107; CHECK-SD-NEXT: ret108;109; CHECK-GI-LABEL: and_eq_ugt:110; CHECK-GI: // %bb.0: // %entry111; CHECK-GI-NEXT: cmp w0, w1112; CHECK-GI-NEXT: cset w8, eq113; CHECK-GI-NEXT: cmp w2, w3114; CHECK-GI-NEXT: cset w9, hi115; CHECK-GI-NEXT: and w0, w8, w9116; CHECK-GI-NEXT: ret117entry:118 %c0 = icmp eq i32 %s0, %s1119 %c1 = icmp ugt i32 %s2, %s3120 %a = and i1 %c0, %c1121 %z = zext i1 %a to i32122 ret i32 %z123}124 125define i32 @and_eq_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {126; CHECK-SD-LABEL: and_eq_uge:127; CHECK-SD: // %bb.0: // %entry128; CHECK-SD-NEXT: cmp w0, w1129; CHECK-SD-NEXT: ccmp w2, w3, #0, eq130; CHECK-SD-NEXT: cset w0, hs131; CHECK-SD-NEXT: ret132;133; CHECK-GI-LABEL: and_eq_uge:134; CHECK-GI: // %bb.0: // %entry135; CHECK-GI-NEXT: cmp w0, w1136; CHECK-GI-NEXT: cset w8, eq137; CHECK-GI-NEXT: cmp w2, w3138; CHECK-GI-NEXT: cset w9, hs139; CHECK-GI-NEXT: and w0, w8, w9140; CHECK-GI-NEXT: ret141entry:142 %c0 = icmp eq i32 %s0, %s1143 %c1 = icmp uge i32 %s2, %s3144 %a = and i1 %c0, %c1145 %z = zext i1 %a to i32146 ret i32 %z147}148 149define i32 @and_eq_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {150; CHECK-SD-LABEL: and_eq_slt:151; CHECK-SD: // %bb.0: // %entry152; CHECK-SD-NEXT: cmp w0, w1153; CHECK-SD-NEXT: ccmp w2, w3, #0, eq154; CHECK-SD-NEXT: cset w0, lt155; CHECK-SD-NEXT: ret156;157; CHECK-GI-LABEL: and_eq_slt:158; CHECK-GI: // %bb.0: // %entry159; CHECK-GI-NEXT: cmp w0, w1160; CHECK-GI-NEXT: cset w8, eq161; CHECK-GI-NEXT: cmp w2, w3162; CHECK-GI-NEXT: cset w9, lt163; CHECK-GI-NEXT: and w0, w8, w9164; CHECK-GI-NEXT: ret165entry:166 %c0 = icmp eq i32 %s0, %s1167 %c1 = icmp slt i32 %s2, %s3168 %a = and i1 %c0, %c1169 %z = zext i1 %a to i32170 ret i32 %z171}172 173define i32 @and_eq_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {174; CHECK-SD-LABEL: and_eq_sle:175; CHECK-SD: // %bb.0: // %entry176; CHECK-SD-NEXT: cmp w0, w1177; CHECK-SD-NEXT: ccmp w2, w3, #0, eq178; CHECK-SD-NEXT: cset w0, le179; CHECK-SD-NEXT: ret180;181; CHECK-GI-LABEL: and_eq_sle:182; CHECK-GI: // %bb.0: // %entry183; CHECK-GI-NEXT: cmp w0, w1184; CHECK-GI-NEXT: cset w8, eq185; CHECK-GI-NEXT: cmp w2, w3186; CHECK-GI-NEXT: cset w9, le187; CHECK-GI-NEXT: and w0, w8, w9188; CHECK-GI-NEXT: ret189entry:190 %c0 = icmp eq i32 %s0, %s1191 %c1 = icmp sle i32 %s2, %s3192 %a = and i1 %c0, %c1193 %z = zext i1 %a to i32194 ret i32 %z195}196 197define i32 @and_eq_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {198; CHECK-SD-LABEL: and_eq_sgt:199; CHECK-SD: // %bb.0: // %entry200; CHECK-SD-NEXT: cmp w0, w1201; CHECK-SD-NEXT: ccmp w2, w3, #4, eq202; CHECK-SD-NEXT: cset w0, gt203; CHECK-SD-NEXT: ret204;205; CHECK-GI-LABEL: and_eq_sgt:206; CHECK-GI: // %bb.0: // %entry207; CHECK-GI-NEXT: cmp w0, w1208; CHECK-GI-NEXT: cset w8, eq209; CHECK-GI-NEXT: cmp w2, w3210; CHECK-GI-NEXT: cset w9, gt211; CHECK-GI-NEXT: and w0, w8, w9212; CHECK-GI-NEXT: ret213entry:214 %c0 = icmp eq i32 %s0, %s1215 %c1 = icmp sgt i32 %s2, %s3216 %a = and i1 %c0, %c1217 %z = zext i1 %a to i32218 ret i32 %z219}220 221define i32 @and_eq_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {222; CHECK-SD-LABEL: and_eq_sge:223; CHECK-SD: // %bb.0: // %entry224; CHECK-SD-NEXT: cmp w0, w1225; CHECK-SD-NEXT: ccmp w2, w3, #8, eq226; CHECK-SD-NEXT: cset w0, ge227; CHECK-SD-NEXT: ret228;229; CHECK-GI-LABEL: and_eq_sge:230; CHECK-GI: // %bb.0: // %entry231; CHECK-GI-NEXT: cmp w0, w1232; CHECK-GI-NEXT: cset w8, eq233; CHECK-GI-NEXT: cmp w2, w3234; CHECK-GI-NEXT: cset w9, ge235; CHECK-GI-NEXT: and w0, w8, w9236; CHECK-GI-NEXT: ret237entry:238 %c0 = icmp eq i32 %s0, %s1239 %c1 = icmp sge i32 %s2, %s3240 %a = and i1 %c0, %c1241 %z = zext i1 %a to i32242 ret i32 %z243}244 245define i32 @and_ne_eq(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {246; CHECK-SD-LABEL: and_ne_eq:247; CHECK-SD: // %bb.0: // %entry248; CHECK-SD-NEXT: cmp w0, w1249; CHECK-SD-NEXT: ccmp w2, w3, #0, ne250; CHECK-SD-NEXT: cset w0, eq251; CHECK-SD-NEXT: ret252;253; CHECK-GI-LABEL: and_ne_eq:254; CHECK-GI: // %bb.0: // %entry255; CHECK-GI-NEXT: cmp w0, w1256; CHECK-GI-NEXT: cset w8, ne257; CHECK-GI-NEXT: cmp w2, w3258; CHECK-GI-NEXT: cset w9, eq259; CHECK-GI-NEXT: and w0, w8, w9260; CHECK-GI-NEXT: ret261entry:262 %c0 = icmp ne i32 %s0, %s1263 %c1 = icmp eq i32 %s2, %s3264 %a = and i1 %c0, %c1265 %z = zext i1 %a to i32266 ret i32 %z267}268 269define i32 @and_ne_ne(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {270; CHECK-SD-LABEL: and_ne_ne:271; CHECK-SD: // %bb.0: // %entry272; CHECK-SD-NEXT: cmp w0, w1273; CHECK-SD-NEXT: ccmp w2, w3, #4, ne274; CHECK-SD-NEXT: cset w0, ne275; CHECK-SD-NEXT: ret276;277; CHECK-GI-LABEL: and_ne_ne:278; CHECK-GI: // %bb.0: // %entry279; CHECK-GI-NEXT: cmp w0, w1280; CHECK-GI-NEXT: cset w8, ne281; CHECK-GI-NEXT: cmp w2, w3282; CHECK-GI-NEXT: cset w9, ne283; CHECK-GI-NEXT: and w0, w8, w9284; CHECK-GI-NEXT: ret285entry:286 %c0 = icmp ne i32 %s0, %s1287 %c1 = icmp ne i32 %s2, %s3288 %a = and i1 %c0, %c1289 %z = zext i1 %a to i32290 ret i32 %z291}292 293define i32 @and_ne_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {294; CHECK-SD-LABEL: and_ne_ult:295; CHECK-SD: // %bb.0: // %entry296; CHECK-SD-NEXT: cmp w0, w1297; CHECK-SD-NEXT: ccmp w2, w3, #2, ne298; CHECK-SD-NEXT: cset w0, lo299; CHECK-SD-NEXT: ret300;301; CHECK-GI-LABEL: and_ne_ult:302; CHECK-GI: // %bb.0: // %entry303; CHECK-GI-NEXT: cmp w0, w1304; CHECK-GI-NEXT: cset w8, ne305; CHECK-GI-NEXT: cmp w2, w3306; CHECK-GI-NEXT: cset w9, lo307; CHECK-GI-NEXT: and w0, w8, w9308; CHECK-GI-NEXT: ret309entry:310 %c0 = icmp ne i32 %s0, %s1311 %c1 = icmp ult i32 %s2, %s3312 %a = and i1 %c0, %c1313 %z = zext i1 %a to i32314 ret i32 %z315}316 317define i32 @and_ne_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {318; CHECK-SD-LABEL: and_ne_ule:319; CHECK-SD: // %bb.0: // %entry320; CHECK-SD-NEXT: cmp w0, w1321; CHECK-SD-NEXT: ccmp w2, w3, #2, ne322; CHECK-SD-NEXT: cset w0, ls323; CHECK-SD-NEXT: ret324;325; CHECK-GI-LABEL: and_ne_ule:326; CHECK-GI: // %bb.0: // %entry327; CHECK-GI-NEXT: cmp w0, w1328; CHECK-GI-NEXT: cset w8, ne329; CHECK-GI-NEXT: cmp w2, w3330; CHECK-GI-NEXT: cset w9, ls331; CHECK-GI-NEXT: and w0, w8, w9332; CHECK-GI-NEXT: ret333entry:334 %c0 = icmp ne i32 %s0, %s1335 %c1 = icmp ule i32 %s2, %s3336 %a = and i1 %c0, %c1337 %z = zext i1 %a to i32338 ret i32 %z339}340 341define i32 @and_ne_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {342; CHECK-SD-LABEL: and_ne_ugt:343; CHECK-SD: // %bb.0: // %entry344; CHECK-SD-NEXT: cmp w0, w1345; CHECK-SD-NEXT: ccmp w2, w3, #0, ne346; CHECK-SD-NEXT: cset w0, hi347; CHECK-SD-NEXT: ret348;349; CHECK-GI-LABEL: and_ne_ugt:350; CHECK-GI: // %bb.0: // %entry351; CHECK-GI-NEXT: cmp w0, w1352; CHECK-GI-NEXT: cset w8, ne353; CHECK-GI-NEXT: cmp w2, w3354; CHECK-GI-NEXT: cset w9, hi355; CHECK-GI-NEXT: and w0, w8, w9356; CHECK-GI-NEXT: ret357entry:358 %c0 = icmp ne i32 %s0, %s1359 %c1 = icmp ugt i32 %s2, %s3360 %a = and i1 %c0, %c1361 %z = zext i1 %a to i32362 ret i32 %z363}364 365define i32 @and_ne_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {366; CHECK-SD-LABEL: and_ne_uge:367; CHECK-SD: // %bb.0: // %entry368; CHECK-SD-NEXT: cmp w0, w1369; CHECK-SD-NEXT: ccmp w2, w3, #0, ne370; CHECK-SD-NEXT: cset w0, hs371; CHECK-SD-NEXT: ret372;373; CHECK-GI-LABEL: and_ne_uge:374; CHECK-GI: // %bb.0: // %entry375; CHECK-GI-NEXT: cmp w0, w1376; CHECK-GI-NEXT: cset w8, ne377; CHECK-GI-NEXT: cmp w2, w3378; CHECK-GI-NEXT: cset w9, hs379; CHECK-GI-NEXT: and w0, w8, w9380; CHECK-GI-NEXT: ret381entry:382 %c0 = icmp ne i32 %s0, %s1383 %c1 = icmp uge i32 %s2, %s3384 %a = and i1 %c0, %c1385 %z = zext i1 %a to i32386 ret i32 %z387}388 389define i32 @and_ne_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {390; CHECK-SD-LABEL: and_ne_slt:391; CHECK-SD: // %bb.0: // %entry392; CHECK-SD-NEXT: cmp w0, w1393; CHECK-SD-NEXT: ccmp w2, w3, #0, ne394; CHECK-SD-NEXT: cset w0, lt395; CHECK-SD-NEXT: ret396;397; CHECK-GI-LABEL: and_ne_slt:398; CHECK-GI: // %bb.0: // %entry399; CHECK-GI-NEXT: cmp w0, w1400; CHECK-GI-NEXT: cset w8, ne401; CHECK-GI-NEXT: cmp w2, w3402; CHECK-GI-NEXT: cset w9, lt403; CHECK-GI-NEXT: and w0, w8, w9404; CHECK-GI-NEXT: ret405entry:406 %c0 = icmp ne i32 %s0, %s1407 %c1 = icmp slt i32 %s2, %s3408 %a = and i1 %c0, %c1409 %z = zext i1 %a to i32410 ret i32 %z411}412 413define i32 @and_ne_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {414; CHECK-SD-LABEL: and_ne_sle:415; CHECK-SD: // %bb.0: // %entry416; CHECK-SD-NEXT: cmp w0, w1417; CHECK-SD-NEXT: ccmp w2, w3, #0, ne418; CHECK-SD-NEXT: cset w0, le419; CHECK-SD-NEXT: ret420;421; CHECK-GI-LABEL: and_ne_sle:422; CHECK-GI: // %bb.0: // %entry423; CHECK-GI-NEXT: cmp w0, w1424; CHECK-GI-NEXT: cset w8, ne425; CHECK-GI-NEXT: cmp w2, w3426; CHECK-GI-NEXT: cset w9, le427; CHECK-GI-NEXT: and w0, w8, w9428; CHECK-GI-NEXT: ret429entry:430 %c0 = icmp ne i32 %s0, %s1431 %c1 = icmp sle i32 %s2, %s3432 %a = and i1 %c0, %c1433 %z = zext i1 %a to i32434 ret i32 %z435}436 437define i32 @and_ne_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {438; CHECK-SD-LABEL: and_ne_sgt:439; CHECK-SD: // %bb.0: // %entry440; CHECK-SD-NEXT: cmp w0, w1441; CHECK-SD-NEXT: ccmp w2, w3, #4, ne442; CHECK-SD-NEXT: cset w0, gt443; CHECK-SD-NEXT: ret444;445; CHECK-GI-LABEL: and_ne_sgt:446; CHECK-GI: // %bb.0: // %entry447; CHECK-GI-NEXT: cmp w0, w1448; CHECK-GI-NEXT: cset w8, ne449; CHECK-GI-NEXT: cmp w2, w3450; CHECK-GI-NEXT: cset w9, gt451; CHECK-GI-NEXT: and w0, w8, w9452; CHECK-GI-NEXT: ret453entry:454 %c0 = icmp ne i32 %s0, %s1455 %c1 = icmp sgt i32 %s2, %s3456 %a = and i1 %c0, %c1457 %z = zext i1 %a to i32458 ret i32 %z459}460 461define i32 @and_ne_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {462; CHECK-SD-LABEL: and_ne_sge:463; CHECK-SD: // %bb.0: // %entry464; CHECK-SD-NEXT: cmp w0, w1465; CHECK-SD-NEXT: ccmp w2, w3, #8, ne466; CHECK-SD-NEXT: cset w0, ge467; CHECK-SD-NEXT: ret468;469; CHECK-GI-LABEL: and_ne_sge:470; CHECK-GI: // %bb.0: // %entry471; CHECK-GI-NEXT: cmp w0, w1472; CHECK-GI-NEXT: cset w8, ne473; CHECK-GI-NEXT: cmp w2, w3474; CHECK-GI-NEXT: cset w9, ge475; CHECK-GI-NEXT: and w0, w8, w9476; CHECK-GI-NEXT: ret477entry:478 %c0 = icmp ne i32 %s0, %s1479 %c1 = icmp sge i32 %s2, %s3480 %a = and i1 %c0, %c1481 %z = zext i1 %a to i32482 ret i32 %z483}484 485define i32 @and_ult_eq(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {486; CHECK-SD-LABEL: and_ult_eq:487; CHECK-SD: // %bb.0: // %entry488; CHECK-SD-NEXT: cmp w0, w1489; CHECK-SD-NEXT: ccmp w2, w3, #0, lo490; CHECK-SD-NEXT: cset w0, eq491; CHECK-SD-NEXT: ret492;493; CHECK-GI-LABEL: and_ult_eq:494; CHECK-GI: // %bb.0: // %entry495; CHECK-GI-NEXT: cmp w0, w1496; CHECK-GI-NEXT: cset w8, lo497; CHECK-GI-NEXT: cmp w2, w3498; CHECK-GI-NEXT: cset w9, eq499; CHECK-GI-NEXT: and w0, w8, w9500; CHECK-GI-NEXT: ret501entry:502 %c0 = icmp ult i32 %s0, %s1503 %c1 = icmp eq i32 %s2, %s3504 %a = and i1 %c0, %c1505 %z = zext i1 %a to i32506 ret i32 %z507}508 509define i32 @and_ult_ne(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {510; CHECK-SD-LABEL: and_ult_ne:511; CHECK-SD: // %bb.0: // %entry512; CHECK-SD-NEXT: cmp w0, w1513; CHECK-SD-NEXT: ccmp w2, w3, #4, lo514; CHECK-SD-NEXT: cset w0, ne515; CHECK-SD-NEXT: ret516;517; CHECK-GI-LABEL: and_ult_ne:518; CHECK-GI: // %bb.0: // %entry519; CHECK-GI-NEXT: cmp w0, w1520; CHECK-GI-NEXT: cset w8, lo521; CHECK-GI-NEXT: cmp w2, w3522; CHECK-GI-NEXT: cset w9, ne523; CHECK-GI-NEXT: and w0, w8, w9524; CHECK-GI-NEXT: ret525entry:526 %c0 = icmp ult i32 %s0, %s1527 %c1 = icmp ne i32 %s2, %s3528 %a = and i1 %c0, %c1529 %z = zext i1 %a to i32530 ret i32 %z531}532 533define i32 @and_ult_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {534; CHECK-SD-LABEL: and_ult_ult:535; CHECK-SD: // %bb.0: // %entry536; CHECK-SD-NEXT: cmp w0, w1537; CHECK-SD-NEXT: ccmp w2, w3, #2, lo538; CHECK-SD-NEXT: cset w0, lo539; CHECK-SD-NEXT: ret540;541; CHECK-GI-LABEL: and_ult_ult:542; CHECK-GI: // %bb.0: // %entry543; CHECK-GI-NEXT: cmp w0, w1544; CHECK-GI-NEXT: cset w8, lo545; CHECK-GI-NEXT: cmp w2, w3546; CHECK-GI-NEXT: cset w9, lo547; CHECK-GI-NEXT: and w0, w8, w9548; CHECK-GI-NEXT: ret549entry:550 %c0 = icmp ult i32 %s0, %s1551 %c1 = icmp ult i32 %s2, %s3552 %a = and i1 %c0, %c1553 %z = zext i1 %a to i32554 ret i32 %z555}556 557define i32 @and_ult_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {558; CHECK-SD-LABEL: and_ult_ule:559; CHECK-SD: // %bb.0: // %entry560; CHECK-SD-NEXT: cmp w0, w1561; CHECK-SD-NEXT: ccmp w2, w3, #2, lo562; CHECK-SD-NEXT: cset w0, ls563; CHECK-SD-NEXT: ret564;565; CHECK-GI-LABEL: and_ult_ule:566; CHECK-GI: // %bb.0: // %entry567; CHECK-GI-NEXT: cmp w0, w1568; CHECK-GI-NEXT: cset w8, lo569; CHECK-GI-NEXT: cmp w2, w3570; CHECK-GI-NEXT: cset w9, ls571; CHECK-GI-NEXT: and w0, w8, w9572; CHECK-GI-NEXT: ret573entry:574 %c0 = icmp ult i32 %s0, %s1575 %c1 = icmp ule i32 %s2, %s3576 %a = and i1 %c0, %c1577 %z = zext i1 %a to i32578 ret i32 %z579}580 581define i32 @and_ult_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {582; CHECK-SD-LABEL: and_ult_ugt:583; CHECK-SD: // %bb.0: // %entry584; CHECK-SD-NEXT: cmp w0, w1585; CHECK-SD-NEXT: ccmp w2, w3, #0, lo586; CHECK-SD-NEXT: cset w0, hi587; CHECK-SD-NEXT: ret588;589; CHECK-GI-LABEL: and_ult_ugt:590; CHECK-GI: // %bb.0: // %entry591; CHECK-GI-NEXT: cmp w0, w1592; CHECK-GI-NEXT: cset w8, lo593; CHECK-GI-NEXT: cmp w2, w3594; CHECK-GI-NEXT: cset w9, hi595; CHECK-GI-NEXT: and w0, w8, w9596; CHECK-GI-NEXT: ret597entry:598 %c0 = icmp ult i32 %s0, %s1599 %c1 = icmp ugt i32 %s2, %s3600 %a = and i1 %c0, %c1601 %z = zext i1 %a to i32602 ret i32 %z603}604 605define i32 @and_ult_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {606; CHECK-SD-LABEL: and_ult_uge:607; CHECK-SD: // %bb.0: // %entry608; CHECK-SD-NEXT: cmp w0, w1609; CHECK-SD-NEXT: ccmp w2, w3, #0, lo610; CHECK-SD-NEXT: cset w0, hs611; CHECK-SD-NEXT: ret612;613; CHECK-GI-LABEL: and_ult_uge:614; CHECK-GI: // %bb.0: // %entry615; CHECK-GI-NEXT: cmp w0, w1616; CHECK-GI-NEXT: cset w8, lo617; CHECK-GI-NEXT: cmp w2, w3618; CHECK-GI-NEXT: cset w9, hs619; CHECK-GI-NEXT: and w0, w8, w9620; CHECK-GI-NEXT: ret621entry:622 %c0 = icmp ult i32 %s0, %s1623 %c1 = icmp uge i32 %s2, %s3624 %a = and i1 %c0, %c1625 %z = zext i1 %a to i32626 ret i32 %z627}628 629define i32 @and_ult_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {630; CHECK-SD-LABEL: and_ult_slt:631; CHECK-SD: // %bb.0: // %entry632; CHECK-SD-NEXT: cmp w0, w1633; CHECK-SD-NEXT: ccmp w2, w3, #0, lo634; CHECK-SD-NEXT: cset w0, lt635; CHECK-SD-NEXT: ret636;637; CHECK-GI-LABEL: and_ult_slt:638; CHECK-GI: // %bb.0: // %entry639; CHECK-GI-NEXT: cmp w0, w1640; CHECK-GI-NEXT: cset w8, lo641; CHECK-GI-NEXT: cmp w2, w3642; CHECK-GI-NEXT: cset w9, lt643; CHECK-GI-NEXT: and w0, w8, w9644; CHECK-GI-NEXT: ret645entry:646 %c0 = icmp ult i32 %s0, %s1647 %c1 = icmp slt i32 %s2, %s3648 %a = and i1 %c0, %c1649 %z = zext i1 %a to i32650 ret i32 %z651}652 653define i32 @and_ult_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {654; CHECK-SD-LABEL: and_ult_sle:655; CHECK-SD: // %bb.0: // %entry656; CHECK-SD-NEXT: cmp w0, w1657; CHECK-SD-NEXT: ccmp w2, w3, #0, lo658; CHECK-SD-NEXT: cset w0, le659; CHECK-SD-NEXT: ret660;661; CHECK-GI-LABEL: and_ult_sle:662; CHECK-GI: // %bb.0: // %entry663; CHECK-GI-NEXT: cmp w0, w1664; CHECK-GI-NEXT: cset w8, lo665; CHECK-GI-NEXT: cmp w2, w3666; CHECK-GI-NEXT: cset w9, le667; CHECK-GI-NEXT: and w0, w8, w9668; CHECK-GI-NEXT: ret669entry:670 %c0 = icmp ult i32 %s0, %s1671 %c1 = icmp sle i32 %s2, %s3672 %a = and i1 %c0, %c1673 %z = zext i1 %a to i32674 ret i32 %z675}676 677define i32 @and_ult_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {678; CHECK-SD-LABEL: and_ult_sgt:679; CHECK-SD: // %bb.0: // %entry680; CHECK-SD-NEXT: cmp w0, w1681; CHECK-SD-NEXT: ccmp w2, w3, #4, lo682; CHECK-SD-NEXT: cset w0, gt683; CHECK-SD-NEXT: ret684;685; CHECK-GI-LABEL: and_ult_sgt:686; CHECK-GI: // %bb.0: // %entry687; CHECK-GI-NEXT: cmp w0, w1688; CHECK-GI-NEXT: cset w8, lo689; CHECK-GI-NEXT: cmp w2, w3690; CHECK-GI-NEXT: cset w9, gt691; CHECK-GI-NEXT: and w0, w8, w9692; CHECK-GI-NEXT: ret693entry:694 %c0 = icmp ult i32 %s0, %s1695 %c1 = icmp sgt i32 %s2, %s3696 %a = and i1 %c0, %c1697 %z = zext i1 %a to i32698 ret i32 %z699}700 701define i32 @and_ult_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {702; CHECK-SD-LABEL: and_ult_sge:703; CHECK-SD: // %bb.0: // %entry704; CHECK-SD-NEXT: cmp w0, w1705; CHECK-SD-NEXT: ccmp w2, w3, #8, lo706; CHECK-SD-NEXT: cset w0, ge707; CHECK-SD-NEXT: ret708;709; CHECK-GI-LABEL: and_ult_sge:710; CHECK-GI: // %bb.0: // %entry711; CHECK-GI-NEXT: cmp w0, w1712; CHECK-GI-NEXT: cset w8, lo713; CHECK-GI-NEXT: cmp w2, w3714; CHECK-GI-NEXT: cset w9, ge715; CHECK-GI-NEXT: and w0, w8, w9716; CHECK-GI-NEXT: ret717entry:718 %c0 = icmp ult i32 %s0, %s1719 %c1 = icmp sge i32 %s2, %s3720 %a = and i1 %c0, %c1721 %z = zext i1 %a to i32722 ret i32 %z723}724 725define i32 @and_ule_eq(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {726; CHECK-SD-LABEL: and_ule_eq:727; CHECK-SD: // %bb.0: // %entry728; CHECK-SD-NEXT: cmp w0, w1729; CHECK-SD-NEXT: ccmp w2, w3, #0, ls730; CHECK-SD-NEXT: cset w0, eq731; CHECK-SD-NEXT: ret732;733; CHECK-GI-LABEL: and_ule_eq:734; CHECK-GI: // %bb.0: // %entry735; CHECK-GI-NEXT: cmp w0, w1736; CHECK-GI-NEXT: cset w8, ls737; CHECK-GI-NEXT: cmp w2, w3738; CHECK-GI-NEXT: cset w9, eq739; CHECK-GI-NEXT: and w0, w8, w9740; CHECK-GI-NEXT: ret741entry:742 %c0 = icmp ule i32 %s0, %s1743 %c1 = icmp eq i32 %s2, %s3744 %a = and i1 %c0, %c1745 %z = zext i1 %a to i32746 ret i32 %z747}748 749define i32 @and_ule_ne(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {750; CHECK-SD-LABEL: and_ule_ne:751; CHECK-SD: // %bb.0: // %entry752; CHECK-SD-NEXT: cmp w0, w1753; CHECK-SD-NEXT: ccmp w2, w3, #4, ls754; CHECK-SD-NEXT: cset w0, ne755; CHECK-SD-NEXT: ret756;757; CHECK-GI-LABEL: and_ule_ne:758; CHECK-GI: // %bb.0: // %entry759; CHECK-GI-NEXT: cmp w0, w1760; CHECK-GI-NEXT: cset w8, ls761; CHECK-GI-NEXT: cmp w2, w3762; CHECK-GI-NEXT: cset w9, ne763; CHECK-GI-NEXT: and w0, w8, w9764; CHECK-GI-NEXT: ret765entry:766 %c0 = icmp ule i32 %s0, %s1767 %c1 = icmp ne i32 %s2, %s3768 %a = and i1 %c0, %c1769 %z = zext i1 %a to i32770 ret i32 %z771}772 773define i32 @and_ule_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {774; CHECK-SD-LABEL: and_ule_ult:775; CHECK-SD: // %bb.0: // %entry776; CHECK-SD-NEXT: cmp w0, w1777; CHECK-SD-NEXT: ccmp w2, w3, #2, ls778; CHECK-SD-NEXT: cset w0, lo779; CHECK-SD-NEXT: ret780;781; CHECK-GI-LABEL: and_ule_ult:782; CHECK-GI: // %bb.0: // %entry783; CHECK-GI-NEXT: cmp w0, w1784; CHECK-GI-NEXT: cset w8, ls785; CHECK-GI-NEXT: cmp w2, w3786; CHECK-GI-NEXT: cset w9, lo787; CHECK-GI-NEXT: and w0, w8, w9788; CHECK-GI-NEXT: ret789entry:790 %c0 = icmp ule i32 %s0, %s1791 %c1 = icmp ult i32 %s2, %s3792 %a = and i1 %c0, %c1793 %z = zext i1 %a to i32794 ret i32 %z795}796 797define i32 @and_ule_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {798; CHECK-SD-LABEL: and_ule_ule:799; CHECK-SD: // %bb.0: // %entry800; CHECK-SD-NEXT: cmp w0, w1801; CHECK-SD-NEXT: ccmp w2, w3, #2, ls802; CHECK-SD-NEXT: cset w0, ls803; CHECK-SD-NEXT: ret804;805; CHECK-GI-LABEL: and_ule_ule:806; CHECK-GI: // %bb.0: // %entry807; CHECK-GI-NEXT: cmp w0, w1808; CHECK-GI-NEXT: cset w8, ls809; CHECK-GI-NEXT: cmp w2, w3810; CHECK-GI-NEXT: cset w9, ls811; CHECK-GI-NEXT: and w0, w8, w9812; CHECK-GI-NEXT: ret813entry:814 %c0 = icmp ule i32 %s0, %s1815 %c1 = icmp ule i32 %s2, %s3816 %a = and i1 %c0, %c1817 %z = zext i1 %a to i32818 ret i32 %z819}820 821define i32 @and_ule_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {822; CHECK-SD-LABEL: and_ule_ugt:823; CHECK-SD: // %bb.0: // %entry824; CHECK-SD-NEXT: cmp w0, w1825; CHECK-SD-NEXT: ccmp w2, w3, #0, ls826; CHECK-SD-NEXT: cset w0, hi827; CHECK-SD-NEXT: ret828;829; CHECK-GI-LABEL: and_ule_ugt:830; CHECK-GI: // %bb.0: // %entry831; CHECK-GI-NEXT: cmp w0, w1832; CHECK-GI-NEXT: cset w8, ls833; CHECK-GI-NEXT: cmp w2, w3834; CHECK-GI-NEXT: cset w9, hi835; CHECK-GI-NEXT: and w0, w8, w9836; CHECK-GI-NEXT: ret837entry:838 %c0 = icmp ule i32 %s0, %s1839 %c1 = icmp ugt i32 %s2, %s3840 %a = and i1 %c0, %c1841 %z = zext i1 %a to i32842 ret i32 %z843}844 845define i32 @and_ule_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {846; CHECK-SD-LABEL: and_ule_uge:847; CHECK-SD: // %bb.0: // %entry848; CHECK-SD-NEXT: cmp w0, w1849; CHECK-SD-NEXT: ccmp w2, w3, #0, ls850; CHECK-SD-NEXT: cset w0, hs851; CHECK-SD-NEXT: ret852;853; CHECK-GI-LABEL: and_ule_uge:854; CHECK-GI: // %bb.0: // %entry855; CHECK-GI-NEXT: cmp w0, w1856; CHECK-GI-NEXT: cset w8, ls857; CHECK-GI-NEXT: cmp w2, w3858; CHECK-GI-NEXT: cset w9, hs859; CHECK-GI-NEXT: and w0, w8, w9860; CHECK-GI-NEXT: ret861entry:862 %c0 = icmp ule i32 %s0, %s1863 %c1 = icmp uge i32 %s2, %s3864 %a = and i1 %c0, %c1865 %z = zext i1 %a to i32866 ret i32 %z867}868 869define i32 @and_ule_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {870; CHECK-SD-LABEL: and_ule_slt:871; CHECK-SD: // %bb.0: // %entry872; CHECK-SD-NEXT: cmp w0, w1873; CHECK-SD-NEXT: ccmp w2, w3, #0, ls874; CHECK-SD-NEXT: cset w0, lt875; CHECK-SD-NEXT: ret876;877; CHECK-GI-LABEL: and_ule_slt:878; CHECK-GI: // %bb.0: // %entry879; CHECK-GI-NEXT: cmp w0, w1880; CHECK-GI-NEXT: cset w8, ls881; CHECK-GI-NEXT: cmp w2, w3882; CHECK-GI-NEXT: cset w9, lt883; CHECK-GI-NEXT: and w0, w8, w9884; CHECK-GI-NEXT: ret885entry:886 %c0 = icmp ule i32 %s0, %s1887 %c1 = icmp slt i32 %s2, %s3888 %a = and i1 %c0, %c1889 %z = zext i1 %a to i32890 ret i32 %z891}892 893define i32 @and_ule_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {894; CHECK-SD-LABEL: and_ule_sle:895; CHECK-SD: // %bb.0: // %entry896; CHECK-SD-NEXT: cmp w0, w1897; CHECK-SD-NEXT: ccmp w2, w3, #0, ls898; CHECK-SD-NEXT: cset w0, le899; CHECK-SD-NEXT: ret900;901; CHECK-GI-LABEL: and_ule_sle:902; CHECK-GI: // %bb.0: // %entry903; CHECK-GI-NEXT: cmp w0, w1904; CHECK-GI-NEXT: cset w8, ls905; CHECK-GI-NEXT: cmp w2, w3906; CHECK-GI-NEXT: cset w9, le907; CHECK-GI-NEXT: and w0, w8, w9908; CHECK-GI-NEXT: ret909entry:910 %c0 = icmp ule i32 %s0, %s1911 %c1 = icmp sle i32 %s2, %s3912 %a = and i1 %c0, %c1913 %z = zext i1 %a to i32914 ret i32 %z915}916 917define i32 @and_ule_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {918; CHECK-SD-LABEL: and_ule_sgt:919; CHECK-SD: // %bb.0: // %entry920; CHECK-SD-NEXT: cmp w0, w1921; CHECK-SD-NEXT: ccmp w2, w3, #4, ls922; CHECK-SD-NEXT: cset w0, gt923; CHECK-SD-NEXT: ret924;925; CHECK-GI-LABEL: and_ule_sgt:926; CHECK-GI: // %bb.0: // %entry927; CHECK-GI-NEXT: cmp w0, w1928; CHECK-GI-NEXT: cset w8, ls929; CHECK-GI-NEXT: cmp w2, w3930; CHECK-GI-NEXT: cset w9, gt931; CHECK-GI-NEXT: and w0, w8, w9932; CHECK-GI-NEXT: ret933entry:934 %c0 = icmp ule i32 %s0, %s1935 %c1 = icmp sgt i32 %s2, %s3936 %a = and i1 %c0, %c1937 %z = zext i1 %a to i32938 ret i32 %z939}940 941define i32 @and_ule_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {942; CHECK-SD-LABEL: and_ule_sge:943; CHECK-SD: // %bb.0: // %entry944; CHECK-SD-NEXT: cmp w0, w1945; CHECK-SD-NEXT: ccmp w2, w3, #8, ls946; CHECK-SD-NEXT: cset w0, ge947; CHECK-SD-NEXT: ret948;949; CHECK-GI-LABEL: and_ule_sge:950; CHECK-GI: // %bb.0: // %entry951; CHECK-GI-NEXT: cmp w0, w1952; CHECK-GI-NEXT: cset w8, ls953; CHECK-GI-NEXT: cmp w2, w3954; CHECK-GI-NEXT: cset w9, ge955; CHECK-GI-NEXT: and w0, w8, w9956; CHECK-GI-NEXT: ret957entry:958 %c0 = icmp ule i32 %s0, %s1959 %c1 = icmp sge i32 %s2, %s3960 %a = and i1 %c0, %c1961 %z = zext i1 %a to i32962 ret i32 %z963}964 965define i32 @and_ugt_eq(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {966; CHECK-SD-LABEL: and_ugt_eq:967; CHECK-SD: // %bb.0: // %entry968; CHECK-SD-NEXT: cmp w0, w1969; CHECK-SD-NEXT: ccmp w2, w3, #0, hi970; CHECK-SD-NEXT: cset w0, eq971; CHECK-SD-NEXT: ret972;973; CHECK-GI-LABEL: and_ugt_eq:974; CHECK-GI: // %bb.0: // %entry975; CHECK-GI-NEXT: cmp w0, w1976; CHECK-GI-NEXT: cset w8, hi977; CHECK-GI-NEXT: cmp w2, w3978; CHECK-GI-NEXT: cset w9, eq979; CHECK-GI-NEXT: and w0, w8, w9980; CHECK-GI-NEXT: ret981entry:982 %c0 = icmp ugt i32 %s0, %s1983 %c1 = icmp eq i32 %s2, %s3984 %a = and i1 %c0, %c1985 %z = zext i1 %a to i32986 ret i32 %z987}988 989define i32 @and_ugt_ne(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {990; CHECK-SD-LABEL: and_ugt_ne:991; CHECK-SD: // %bb.0: // %entry992; CHECK-SD-NEXT: cmp w0, w1993; CHECK-SD-NEXT: ccmp w2, w3, #4, hi994; CHECK-SD-NEXT: cset w0, ne995; CHECK-SD-NEXT: ret996;997; CHECK-GI-LABEL: and_ugt_ne:998; CHECK-GI: // %bb.0: // %entry999; CHECK-GI-NEXT: cmp w0, w11000; CHECK-GI-NEXT: cset w8, hi1001; CHECK-GI-NEXT: cmp w2, w31002; CHECK-GI-NEXT: cset w9, ne1003; CHECK-GI-NEXT: and w0, w8, w91004; CHECK-GI-NEXT: ret1005entry:1006 %c0 = icmp ugt i32 %s0, %s11007 %c1 = icmp ne i32 %s2, %s31008 %a = and i1 %c0, %c11009 %z = zext i1 %a to i321010 ret i32 %z1011}1012 1013define i32 @and_ugt_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1014; CHECK-SD-LABEL: and_ugt_ult:1015; CHECK-SD: // %bb.0: // %entry1016; CHECK-SD-NEXT: cmp w0, w11017; CHECK-SD-NEXT: ccmp w2, w3, #2, hi1018; CHECK-SD-NEXT: cset w0, lo1019; CHECK-SD-NEXT: ret1020;1021; CHECK-GI-LABEL: and_ugt_ult:1022; CHECK-GI: // %bb.0: // %entry1023; CHECK-GI-NEXT: cmp w0, w11024; CHECK-GI-NEXT: cset w8, hi1025; CHECK-GI-NEXT: cmp w2, w31026; CHECK-GI-NEXT: cset w9, lo1027; CHECK-GI-NEXT: and w0, w8, w91028; CHECK-GI-NEXT: ret1029entry:1030 %c0 = icmp ugt i32 %s0, %s11031 %c1 = icmp ult i32 %s2, %s31032 %a = and i1 %c0, %c11033 %z = zext i1 %a to i321034 ret i32 %z1035}1036 1037define i32 @and_ugt_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1038; CHECK-SD-LABEL: and_ugt_ule:1039; CHECK-SD: // %bb.0: // %entry1040; CHECK-SD-NEXT: cmp w0, w11041; CHECK-SD-NEXT: ccmp w2, w3, #2, hi1042; CHECK-SD-NEXT: cset w0, ls1043; CHECK-SD-NEXT: ret1044;1045; CHECK-GI-LABEL: and_ugt_ule:1046; CHECK-GI: // %bb.0: // %entry1047; CHECK-GI-NEXT: cmp w0, w11048; CHECK-GI-NEXT: cset w8, hi1049; CHECK-GI-NEXT: cmp w2, w31050; CHECK-GI-NEXT: cset w9, ls1051; CHECK-GI-NEXT: and w0, w8, w91052; CHECK-GI-NEXT: ret1053entry:1054 %c0 = icmp ugt i32 %s0, %s11055 %c1 = icmp ule i32 %s2, %s31056 %a = and i1 %c0, %c11057 %z = zext i1 %a to i321058 ret i32 %z1059}1060 1061define i32 @and_ugt_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1062; CHECK-SD-LABEL: and_ugt_ugt:1063; CHECK-SD: // %bb.0: // %entry1064; CHECK-SD-NEXT: cmp w0, w11065; CHECK-SD-NEXT: ccmp w2, w3, #0, hi1066; CHECK-SD-NEXT: cset w0, hi1067; CHECK-SD-NEXT: ret1068;1069; CHECK-GI-LABEL: and_ugt_ugt:1070; CHECK-GI: // %bb.0: // %entry1071; CHECK-GI-NEXT: cmp w0, w11072; CHECK-GI-NEXT: cset w8, hi1073; CHECK-GI-NEXT: cmp w2, w31074; CHECK-GI-NEXT: cset w9, hi1075; CHECK-GI-NEXT: and w0, w8, w91076; CHECK-GI-NEXT: ret1077entry:1078 %c0 = icmp ugt i32 %s0, %s11079 %c1 = icmp ugt i32 %s2, %s31080 %a = and i1 %c0, %c11081 %z = zext i1 %a to i321082 ret i32 %z1083}1084 1085define i32 @and_ugt_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1086; CHECK-SD-LABEL: and_ugt_uge:1087; CHECK-SD: // %bb.0: // %entry1088; CHECK-SD-NEXT: cmp w0, w11089; CHECK-SD-NEXT: ccmp w2, w3, #0, hi1090; CHECK-SD-NEXT: cset w0, hs1091; CHECK-SD-NEXT: ret1092;1093; CHECK-GI-LABEL: and_ugt_uge:1094; CHECK-GI: // %bb.0: // %entry1095; CHECK-GI-NEXT: cmp w0, w11096; CHECK-GI-NEXT: cset w8, hi1097; CHECK-GI-NEXT: cmp w2, w31098; CHECK-GI-NEXT: cset w9, hs1099; CHECK-GI-NEXT: and w0, w8, w91100; CHECK-GI-NEXT: ret1101entry:1102 %c0 = icmp ugt i32 %s0, %s11103 %c1 = icmp uge i32 %s2, %s31104 %a = and i1 %c0, %c11105 %z = zext i1 %a to i321106 ret i32 %z1107}1108 1109define i32 @and_ugt_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1110; CHECK-SD-LABEL: and_ugt_slt:1111; CHECK-SD: // %bb.0: // %entry1112; CHECK-SD-NEXT: cmp w0, w11113; CHECK-SD-NEXT: ccmp w2, w3, #0, hi1114; CHECK-SD-NEXT: cset w0, lt1115; CHECK-SD-NEXT: ret1116;1117; CHECK-GI-LABEL: and_ugt_slt:1118; CHECK-GI: // %bb.0: // %entry1119; CHECK-GI-NEXT: cmp w0, w11120; CHECK-GI-NEXT: cset w8, hi1121; CHECK-GI-NEXT: cmp w2, w31122; CHECK-GI-NEXT: cset w9, lt1123; CHECK-GI-NEXT: and w0, w8, w91124; CHECK-GI-NEXT: ret1125entry:1126 %c0 = icmp ugt i32 %s0, %s11127 %c1 = icmp slt i32 %s2, %s31128 %a = and i1 %c0, %c11129 %z = zext i1 %a to i321130 ret i32 %z1131}1132 1133define i32 @and_ugt_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1134; CHECK-SD-LABEL: and_ugt_sle:1135; CHECK-SD: // %bb.0: // %entry1136; CHECK-SD-NEXT: cmp w0, w11137; CHECK-SD-NEXT: ccmp w2, w3, #0, hi1138; CHECK-SD-NEXT: cset w0, le1139; CHECK-SD-NEXT: ret1140;1141; CHECK-GI-LABEL: and_ugt_sle:1142; CHECK-GI: // %bb.0: // %entry1143; CHECK-GI-NEXT: cmp w0, w11144; CHECK-GI-NEXT: cset w8, hi1145; CHECK-GI-NEXT: cmp w2, w31146; CHECK-GI-NEXT: cset w9, le1147; CHECK-GI-NEXT: and w0, w8, w91148; CHECK-GI-NEXT: ret1149entry:1150 %c0 = icmp ugt i32 %s0, %s11151 %c1 = icmp sle i32 %s2, %s31152 %a = and i1 %c0, %c11153 %z = zext i1 %a to i321154 ret i32 %z1155}1156 1157define i32 @and_ugt_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1158; CHECK-SD-LABEL: and_ugt_sgt:1159; CHECK-SD: // %bb.0: // %entry1160; CHECK-SD-NEXT: cmp w0, w11161; CHECK-SD-NEXT: ccmp w2, w3, #4, hi1162; CHECK-SD-NEXT: cset w0, gt1163; CHECK-SD-NEXT: ret1164;1165; CHECK-GI-LABEL: and_ugt_sgt:1166; CHECK-GI: // %bb.0: // %entry1167; CHECK-GI-NEXT: cmp w0, w11168; CHECK-GI-NEXT: cset w8, hi1169; CHECK-GI-NEXT: cmp w2, w31170; CHECK-GI-NEXT: cset w9, gt1171; CHECK-GI-NEXT: and w0, w8, w91172; CHECK-GI-NEXT: ret1173entry:1174 %c0 = icmp ugt i32 %s0, %s11175 %c1 = icmp sgt i32 %s2, %s31176 %a = and i1 %c0, %c11177 %z = zext i1 %a to i321178 ret i32 %z1179}1180 1181define i32 @and_ugt_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1182; CHECK-SD-LABEL: and_ugt_sge:1183; CHECK-SD: // %bb.0: // %entry1184; CHECK-SD-NEXT: cmp w0, w11185; CHECK-SD-NEXT: ccmp w2, w3, #8, hi1186; CHECK-SD-NEXT: cset w0, ge1187; CHECK-SD-NEXT: ret1188;1189; CHECK-GI-LABEL: and_ugt_sge:1190; CHECK-GI: // %bb.0: // %entry1191; CHECK-GI-NEXT: cmp w0, w11192; CHECK-GI-NEXT: cset w8, hi1193; CHECK-GI-NEXT: cmp w2, w31194; CHECK-GI-NEXT: cset w9, ge1195; CHECK-GI-NEXT: and w0, w8, w91196; CHECK-GI-NEXT: ret1197entry:1198 %c0 = icmp ugt i32 %s0, %s11199 %c1 = icmp sge i32 %s2, %s31200 %a = and i1 %c0, %c11201 %z = zext i1 %a to i321202 ret i32 %z1203}1204 1205define i32 @and_uge_eq(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1206; CHECK-SD-LABEL: and_uge_eq:1207; CHECK-SD: // %bb.0: // %entry1208; CHECK-SD-NEXT: cmp w0, w11209; CHECK-SD-NEXT: ccmp w2, w3, #0, hs1210; CHECK-SD-NEXT: cset w0, eq1211; CHECK-SD-NEXT: ret1212;1213; CHECK-GI-LABEL: and_uge_eq:1214; CHECK-GI: // %bb.0: // %entry1215; CHECK-GI-NEXT: cmp w0, w11216; CHECK-GI-NEXT: cset w8, hs1217; CHECK-GI-NEXT: cmp w2, w31218; CHECK-GI-NEXT: cset w9, eq1219; CHECK-GI-NEXT: and w0, w8, w91220; CHECK-GI-NEXT: ret1221entry:1222 %c0 = icmp uge i32 %s0, %s11223 %c1 = icmp eq i32 %s2, %s31224 %a = and i1 %c0, %c11225 %z = zext i1 %a to i321226 ret i32 %z1227}1228 1229define i32 @and_uge_ne(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1230; CHECK-SD-LABEL: and_uge_ne:1231; CHECK-SD: // %bb.0: // %entry1232; CHECK-SD-NEXT: cmp w0, w11233; CHECK-SD-NEXT: ccmp w2, w3, #4, hs1234; CHECK-SD-NEXT: cset w0, ne1235; CHECK-SD-NEXT: ret1236;1237; CHECK-GI-LABEL: and_uge_ne:1238; CHECK-GI: // %bb.0: // %entry1239; CHECK-GI-NEXT: cmp w0, w11240; CHECK-GI-NEXT: cset w8, hs1241; CHECK-GI-NEXT: cmp w2, w31242; CHECK-GI-NEXT: cset w9, ne1243; CHECK-GI-NEXT: and w0, w8, w91244; CHECK-GI-NEXT: ret1245entry:1246 %c0 = icmp uge i32 %s0, %s11247 %c1 = icmp ne i32 %s2, %s31248 %a = and i1 %c0, %c11249 %z = zext i1 %a to i321250 ret i32 %z1251}1252 1253define i32 @and_uge_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1254; CHECK-SD-LABEL: and_uge_ult:1255; CHECK-SD: // %bb.0: // %entry1256; CHECK-SD-NEXT: cmp w0, w11257; CHECK-SD-NEXT: ccmp w2, w3, #2, hs1258; CHECK-SD-NEXT: cset w0, lo1259; CHECK-SD-NEXT: ret1260;1261; CHECK-GI-LABEL: and_uge_ult:1262; CHECK-GI: // %bb.0: // %entry1263; CHECK-GI-NEXT: cmp w0, w11264; CHECK-GI-NEXT: cset w8, hs1265; CHECK-GI-NEXT: cmp w2, w31266; CHECK-GI-NEXT: cset w9, lo1267; CHECK-GI-NEXT: and w0, w8, w91268; CHECK-GI-NEXT: ret1269entry:1270 %c0 = icmp uge i32 %s0, %s11271 %c1 = icmp ult i32 %s2, %s31272 %a = and i1 %c0, %c11273 %z = zext i1 %a to i321274 ret i32 %z1275}1276 1277define i32 @and_uge_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1278; CHECK-SD-LABEL: and_uge_ule:1279; CHECK-SD: // %bb.0: // %entry1280; CHECK-SD-NEXT: cmp w0, w11281; CHECK-SD-NEXT: ccmp w2, w3, #2, hs1282; CHECK-SD-NEXT: cset w0, ls1283; CHECK-SD-NEXT: ret1284;1285; CHECK-GI-LABEL: and_uge_ule:1286; CHECK-GI: // %bb.0: // %entry1287; CHECK-GI-NEXT: cmp w0, w11288; CHECK-GI-NEXT: cset w8, hs1289; CHECK-GI-NEXT: cmp w2, w31290; CHECK-GI-NEXT: cset w9, ls1291; CHECK-GI-NEXT: and w0, w8, w91292; CHECK-GI-NEXT: ret1293entry:1294 %c0 = icmp uge i32 %s0, %s11295 %c1 = icmp ule i32 %s2, %s31296 %a = and i1 %c0, %c11297 %z = zext i1 %a to i321298 ret i32 %z1299}1300 1301define i32 @and_uge_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1302; CHECK-SD-LABEL: and_uge_ugt:1303; CHECK-SD: // %bb.0: // %entry1304; CHECK-SD-NEXT: cmp w0, w11305; CHECK-SD-NEXT: ccmp w2, w3, #0, hs1306; CHECK-SD-NEXT: cset w0, hi1307; CHECK-SD-NEXT: ret1308;1309; CHECK-GI-LABEL: and_uge_ugt:1310; CHECK-GI: // %bb.0: // %entry1311; CHECK-GI-NEXT: cmp w0, w11312; CHECK-GI-NEXT: cset w8, hs1313; CHECK-GI-NEXT: cmp w2, w31314; CHECK-GI-NEXT: cset w9, hi1315; CHECK-GI-NEXT: and w0, w8, w91316; CHECK-GI-NEXT: ret1317entry:1318 %c0 = icmp uge i32 %s0, %s11319 %c1 = icmp ugt i32 %s2, %s31320 %a = and i1 %c0, %c11321 %z = zext i1 %a to i321322 ret i32 %z1323}1324 1325define i32 @and_uge_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1326; CHECK-SD-LABEL: and_uge_uge:1327; CHECK-SD: // %bb.0: // %entry1328; CHECK-SD-NEXT: cmp w0, w11329; CHECK-SD-NEXT: ccmp w2, w3, #0, hs1330; CHECK-SD-NEXT: cset w0, hs1331; CHECK-SD-NEXT: ret1332;1333; CHECK-GI-LABEL: and_uge_uge:1334; CHECK-GI: // %bb.0: // %entry1335; CHECK-GI-NEXT: cmp w0, w11336; CHECK-GI-NEXT: cset w8, hs1337; CHECK-GI-NEXT: cmp w2, w31338; CHECK-GI-NEXT: cset w9, hs1339; CHECK-GI-NEXT: and w0, w8, w91340; CHECK-GI-NEXT: ret1341entry:1342 %c0 = icmp uge i32 %s0, %s11343 %c1 = icmp uge i32 %s2, %s31344 %a = and i1 %c0, %c11345 %z = zext i1 %a to i321346 ret i32 %z1347}1348 1349define i32 @and_uge_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1350; CHECK-SD-LABEL: and_uge_slt:1351; CHECK-SD: // %bb.0: // %entry1352; CHECK-SD-NEXT: cmp w0, w11353; CHECK-SD-NEXT: ccmp w2, w3, #0, hs1354; CHECK-SD-NEXT: cset w0, lt1355; CHECK-SD-NEXT: ret1356;1357; CHECK-GI-LABEL: and_uge_slt:1358; CHECK-GI: // %bb.0: // %entry1359; CHECK-GI-NEXT: cmp w0, w11360; CHECK-GI-NEXT: cset w8, hs1361; CHECK-GI-NEXT: cmp w2, w31362; CHECK-GI-NEXT: cset w9, lt1363; CHECK-GI-NEXT: and w0, w8, w91364; CHECK-GI-NEXT: ret1365entry:1366 %c0 = icmp uge i32 %s0, %s11367 %c1 = icmp slt i32 %s2, %s31368 %a = and i1 %c0, %c11369 %z = zext i1 %a to i321370 ret i32 %z1371}1372 1373define i32 @and_uge_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1374; CHECK-SD-LABEL: and_uge_sle:1375; CHECK-SD: // %bb.0: // %entry1376; CHECK-SD-NEXT: cmp w0, w11377; CHECK-SD-NEXT: ccmp w2, w3, #0, hs1378; CHECK-SD-NEXT: cset w0, le1379; CHECK-SD-NEXT: ret1380;1381; CHECK-GI-LABEL: and_uge_sle:1382; CHECK-GI: // %bb.0: // %entry1383; CHECK-GI-NEXT: cmp w0, w11384; CHECK-GI-NEXT: cset w8, hs1385; CHECK-GI-NEXT: cmp w2, w31386; CHECK-GI-NEXT: cset w9, le1387; CHECK-GI-NEXT: and w0, w8, w91388; CHECK-GI-NEXT: ret1389entry:1390 %c0 = icmp uge i32 %s0, %s11391 %c1 = icmp sle i32 %s2, %s31392 %a = and i1 %c0, %c11393 %z = zext i1 %a to i321394 ret i32 %z1395}1396 1397define i32 @and_uge_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1398; CHECK-SD-LABEL: and_uge_sgt:1399; CHECK-SD: // %bb.0: // %entry1400; CHECK-SD-NEXT: cmp w0, w11401; CHECK-SD-NEXT: ccmp w2, w3, #4, hs1402; CHECK-SD-NEXT: cset w0, gt1403; CHECK-SD-NEXT: ret1404;1405; CHECK-GI-LABEL: and_uge_sgt:1406; CHECK-GI: // %bb.0: // %entry1407; CHECK-GI-NEXT: cmp w0, w11408; CHECK-GI-NEXT: cset w8, hs1409; CHECK-GI-NEXT: cmp w2, w31410; CHECK-GI-NEXT: cset w9, gt1411; CHECK-GI-NEXT: and w0, w8, w91412; CHECK-GI-NEXT: ret1413entry:1414 %c0 = icmp uge i32 %s0, %s11415 %c1 = icmp sgt i32 %s2, %s31416 %a = and i1 %c0, %c11417 %z = zext i1 %a to i321418 ret i32 %z1419}1420 1421define i32 @and_uge_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1422; CHECK-SD-LABEL: and_uge_sge:1423; CHECK-SD: // %bb.0: // %entry1424; CHECK-SD-NEXT: cmp w0, w11425; CHECK-SD-NEXT: ccmp w2, w3, #8, hs1426; CHECK-SD-NEXT: cset w0, ge1427; CHECK-SD-NEXT: ret1428;1429; CHECK-GI-LABEL: and_uge_sge:1430; CHECK-GI: // %bb.0: // %entry1431; CHECK-GI-NEXT: cmp w0, w11432; CHECK-GI-NEXT: cset w8, hs1433; CHECK-GI-NEXT: cmp w2, w31434; CHECK-GI-NEXT: cset w9, ge1435; CHECK-GI-NEXT: and w0, w8, w91436; CHECK-GI-NEXT: ret1437entry:1438 %c0 = icmp uge i32 %s0, %s11439 %c1 = icmp sge i32 %s2, %s31440 %a = and i1 %c0, %c11441 %z = zext i1 %a to i321442 ret i32 %z1443}1444 1445define i32 @and_slt_eq(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1446; CHECK-SD-LABEL: and_slt_eq:1447; CHECK-SD: // %bb.0: // %entry1448; CHECK-SD-NEXT: cmp w0, w11449; CHECK-SD-NEXT: ccmp w2, w3, #0, lt1450; CHECK-SD-NEXT: cset w0, eq1451; CHECK-SD-NEXT: ret1452;1453; CHECK-GI-LABEL: and_slt_eq:1454; CHECK-GI: // %bb.0: // %entry1455; CHECK-GI-NEXT: cmp w0, w11456; CHECK-GI-NEXT: cset w8, lt1457; CHECK-GI-NEXT: cmp w2, w31458; CHECK-GI-NEXT: cset w9, eq1459; CHECK-GI-NEXT: and w0, w8, w91460; CHECK-GI-NEXT: ret1461entry:1462 %c0 = icmp slt i32 %s0, %s11463 %c1 = icmp eq i32 %s2, %s31464 %a = and i1 %c0, %c11465 %z = zext i1 %a to i321466 ret i32 %z1467}1468 1469define i32 @and_slt_ne(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1470; CHECK-SD-LABEL: and_slt_ne:1471; CHECK-SD: // %bb.0: // %entry1472; CHECK-SD-NEXT: cmp w0, w11473; CHECK-SD-NEXT: ccmp w2, w3, #4, lt1474; CHECK-SD-NEXT: cset w0, ne1475; CHECK-SD-NEXT: ret1476;1477; CHECK-GI-LABEL: and_slt_ne:1478; CHECK-GI: // %bb.0: // %entry1479; CHECK-GI-NEXT: cmp w0, w11480; CHECK-GI-NEXT: cset w8, lt1481; CHECK-GI-NEXT: cmp w2, w31482; CHECK-GI-NEXT: cset w9, ne1483; CHECK-GI-NEXT: and w0, w8, w91484; CHECK-GI-NEXT: ret1485entry:1486 %c0 = icmp slt i32 %s0, %s11487 %c1 = icmp ne i32 %s2, %s31488 %a = and i1 %c0, %c11489 %z = zext i1 %a to i321490 ret i32 %z1491}1492 1493define i32 @and_slt_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1494; CHECK-SD-LABEL: and_slt_ult:1495; CHECK-SD: // %bb.0: // %entry1496; CHECK-SD-NEXT: cmp w0, w11497; CHECK-SD-NEXT: ccmp w2, w3, #2, lt1498; CHECK-SD-NEXT: cset w0, lo1499; CHECK-SD-NEXT: ret1500;1501; CHECK-GI-LABEL: and_slt_ult:1502; CHECK-GI: // %bb.0: // %entry1503; CHECK-GI-NEXT: cmp w0, w11504; CHECK-GI-NEXT: cset w8, lt1505; CHECK-GI-NEXT: cmp w2, w31506; CHECK-GI-NEXT: cset w9, lo1507; CHECK-GI-NEXT: and w0, w8, w91508; CHECK-GI-NEXT: ret1509entry:1510 %c0 = icmp slt i32 %s0, %s11511 %c1 = icmp ult i32 %s2, %s31512 %a = and i1 %c0, %c11513 %z = zext i1 %a to i321514 ret i32 %z1515}1516 1517define i32 @and_slt_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1518; CHECK-SD-LABEL: and_slt_ule:1519; CHECK-SD: // %bb.0: // %entry1520; CHECK-SD-NEXT: cmp w0, w11521; CHECK-SD-NEXT: ccmp w2, w3, #2, lt1522; CHECK-SD-NEXT: cset w0, ls1523; CHECK-SD-NEXT: ret1524;1525; CHECK-GI-LABEL: and_slt_ule:1526; CHECK-GI: // %bb.0: // %entry1527; CHECK-GI-NEXT: cmp w0, w11528; CHECK-GI-NEXT: cset w8, lt1529; CHECK-GI-NEXT: cmp w2, w31530; CHECK-GI-NEXT: cset w9, ls1531; CHECK-GI-NEXT: and w0, w8, w91532; CHECK-GI-NEXT: ret1533entry:1534 %c0 = icmp slt i32 %s0, %s11535 %c1 = icmp ule i32 %s2, %s31536 %a = and i1 %c0, %c11537 %z = zext i1 %a to i321538 ret i32 %z1539}1540 1541define i32 @and_slt_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1542; CHECK-SD-LABEL: and_slt_ugt:1543; CHECK-SD: // %bb.0: // %entry1544; CHECK-SD-NEXT: cmp w0, w11545; CHECK-SD-NEXT: ccmp w2, w3, #0, lt1546; CHECK-SD-NEXT: cset w0, hi1547; CHECK-SD-NEXT: ret1548;1549; CHECK-GI-LABEL: and_slt_ugt:1550; CHECK-GI: // %bb.0: // %entry1551; CHECK-GI-NEXT: cmp w0, w11552; CHECK-GI-NEXT: cset w8, lt1553; CHECK-GI-NEXT: cmp w2, w31554; CHECK-GI-NEXT: cset w9, hi1555; CHECK-GI-NEXT: and w0, w8, w91556; CHECK-GI-NEXT: ret1557entry:1558 %c0 = icmp slt i32 %s0, %s11559 %c1 = icmp ugt i32 %s2, %s31560 %a = and i1 %c0, %c11561 %z = zext i1 %a to i321562 ret i32 %z1563}1564 1565define i32 @and_slt_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1566; CHECK-SD-LABEL: and_slt_uge:1567; CHECK-SD: // %bb.0: // %entry1568; CHECK-SD-NEXT: cmp w0, w11569; CHECK-SD-NEXT: ccmp w2, w3, #0, lt1570; CHECK-SD-NEXT: cset w0, hs1571; CHECK-SD-NEXT: ret1572;1573; CHECK-GI-LABEL: and_slt_uge:1574; CHECK-GI: // %bb.0: // %entry1575; CHECK-GI-NEXT: cmp w0, w11576; CHECK-GI-NEXT: cset w8, lt1577; CHECK-GI-NEXT: cmp w2, w31578; CHECK-GI-NEXT: cset w9, hs1579; CHECK-GI-NEXT: and w0, w8, w91580; CHECK-GI-NEXT: ret1581entry:1582 %c0 = icmp slt i32 %s0, %s11583 %c1 = icmp uge i32 %s2, %s31584 %a = and i1 %c0, %c11585 %z = zext i1 %a to i321586 ret i32 %z1587}1588 1589define i32 @and_slt_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1590; CHECK-SD-LABEL: and_slt_slt:1591; CHECK-SD: // %bb.0: // %entry1592; CHECK-SD-NEXT: cmp w0, w11593; CHECK-SD-NEXT: ccmp w2, w3, #0, lt1594; CHECK-SD-NEXT: cset w0, lt1595; CHECK-SD-NEXT: ret1596;1597; CHECK-GI-LABEL: and_slt_slt:1598; CHECK-GI: // %bb.0: // %entry1599; CHECK-GI-NEXT: cmp w0, w11600; CHECK-GI-NEXT: cset w8, lt1601; CHECK-GI-NEXT: cmp w2, w31602; CHECK-GI-NEXT: cset w9, lt1603; CHECK-GI-NEXT: and w0, w8, w91604; CHECK-GI-NEXT: ret1605entry:1606 %c0 = icmp slt i32 %s0, %s11607 %c1 = icmp slt i32 %s2, %s31608 %a = and i1 %c0, %c11609 %z = zext i1 %a to i321610 ret i32 %z1611}1612 1613define i32 @and_slt_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1614; CHECK-SD-LABEL: and_slt_sle:1615; CHECK-SD: // %bb.0: // %entry1616; CHECK-SD-NEXT: cmp w0, w11617; CHECK-SD-NEXT: ccmp w2, w3, #0, lt1618; CHECK-SD-NEXT: cset w0, le1619; CHECK-SD-NEXT: ret1620;1621; CHECK-GI-LABEL: and_slt_sle:1622; CHECK-GI: // %bb.0: // %entry1623; CHECK-GI-NEXT: cmp w0, w11624; CHECK-GI-NEXT: cset w8, lt1625; CHECK-GI-NEXT: cmp w2, w31626; CHECK-GI-NEXT: cset w9, le1627; CHECK-GI-NEXT: and w0, w8, w91628; CHECK-GI-NEXT: ret1629entry:1630 %c0 = icmp slt i32 %s0, %s11631 %c1 = icmp sle i32 %s2, %s31632 %a = and i1 %c0, %c11633 %z = zext i1 %a to i321634 ret i32 %z1635}1636 1637define i32 @and_slt_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1638; CHECK-SD-LABEL: and_slt_sgt:1639; CHECK-SD: // %bb.0: // %entry1640; CHECK-SD-NEXT: cmp w0, w11641; CHECK-SD-NEXT: ccmp w2, w3, #4, lt1642; CHECK-SD-NEXT: cset w0, gt1643; CHECK-SD-NEXT: ret1644;1645; CHECK-GI-LABEL: and_slt_sgt:1646; CHECK-GI: // %bb.0: // %entry1647; CHECK-GI-NEXT: cmp w0, w11648; CHECK-GI-NEXT: cset w8, lt1649; CHECK-GI-NEXT: cmp w2, w31650; CHECK-GI-NEXT: cset w9, gt1651; CHECK-GI-NEXT: and w0, w8, w91652; CHECK-GI-NEXT: ret1653entry:1654 %c0 = icmp slt i32 %s0, %s11655 %c1 = icmp sgt i32 %s2, %s31656 %a = and i1 %c0, %c11657 %z = zext i1 %a to i321658 ret i32 %z1659}1660 1661define i32 @and_slt_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1662; CHECK-SD-LABEL: and_slt_sge:1663; CHECK-SD: // %bb.0: // %entry1664; CHECK-SD-NEXT: cmp w0, w11665; CHECK-SD-NEXT: ccmp w2, w3, #8, lt1666; CHECK-SD-NEXT: cset w0, ge1667; CHECK-SD-NEXT: ret1668;1669; CHECK-GI-LABEL: and_slt_sge:1670; CHECK-GI: // %bb.0: // %entry1671; CHECK-GI-NEXT: cmp w0, w11672; CHECK-GI-NEXT: cset w8, lt1673; CHECK-GI-NEXT: cmp w2, w31674; CHECK-GI-NEXT: cset w9, ge1675; CHECK-GI-NEXT: and w0, w8, w91676; CHECK-GI-NEXT: ret1677entry:1678 %c0 = icmp slt i32 %s0, %s11679 %c1 = icmp sge i32 %s2, %s31680 %a = and i1 %c0, %c11681 %z = zext i1 %a to i321682 ret i32 %z1683}1684 1685define i32 @and_sle_eq(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1686; CHECK-SD-LABEL: and_sle_eq:1687; CHECK-SD: // %bb.0: // %entry1688; CHECK-SD-NEXT: cmp w0, w11689; CHECK-SD-NEXT: ccmp w2, w3, #0, le1690; CHECK-SD-NEXT: cset w0, eq1691; CHECK-SD-NEXT: ret1692;1693; CHECK-GI-LABEL: and_sle_eq:1694; CHECK-GI: // %bb.0: // %entry1695; CHECK-GI-NEXT: cmp w0, w11696; CHECK-GI-NEXT: cset w8, le1697; CHECK-GI-NEXT: cmp w2, w31698; CHECK-GI-NEXT: cset w9, eq1699; CHECK-GI-NEXT: and w0, w8, w91700; CHECK-GI-NEXT: ret1701entry:1702 %c0 = icmp sle i32 %s0, %s11703 %c1 = icmp eq i32 %s2, %s31704 %a = and i1 %c0, %c11705 %z = zext i1 %a to i321706 ret i32 %z1707}1708 1709define i32 @and_sle_ne(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1710; CHECK-SD-LABEL: and_sle_ne:1711; CHECK-SD: // %bb.0: // %entry1712; CHECK-SD-NEXT: cmp w0, w11713; CHECK-SD-NEXT: ccmp w2, w3, #4, le1714; CHECK-SD-NEXT: cset w0, ne1715; CHECK-SD-NEXT: ret1716;1717; CHECK-GI-LABEL: and_sle_ne:1718; CHECK-GI: // %bb.0: // %entry1719; CHECK-GI-NEXT: cmp w0, w11720; CHECK-GI-NEXT: cset w8, le1721; CHECK-GI-NEXT: cmp w2, w31722; CHECK-GI-NEXT: cset w9, ne1723; CHECK-GI-NEXT: and w0, w8, w91724; CHECK-GI-NEXT: ret1725entry:1726 %c0 = icmp sle i32 %s0, %s11727 %c1 = icmp ne i32 %s2, %s31728 %a = and i1 %c0, %c11729 %z = zext i1 %a to i321730 ret i32 %z1731}1732 1733define i32 @and_sle_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1734; CHECK-SD-LABEL: and_sle_ult:1735; CHECK-SD: // %bb.0: // %entry1736; CHECK-SD-NEXT: cmp w0, w11737; CHECK-SD-NEXT: ccmp w2, w3, #2, le1738; CHECK-SD-NEXT: cset w0, lo1739; CHECK-SD-NEXT: ret1740;1741; CHECK-GI-LABEL: and_sle_ult:1742; CHECK-GI: // %bb.0: // %entry1743; CHECK-GI-NEXT: cmp w0, w11744; CHECK-GI-NEXT: cset w8, le1745; CHECK-GI-NEXT: cmp w2, w31746; CHECK-GI-NEXT: cset w9, lo1747; CHECK-GI-NEXT: and w0, w8, w91748; CHECK-GI-NEXT: ret1749entry:1750 %c0 = icmp sle i32 %s0, %s11751 %c1 = icmp ult i32 %s2, %s31752 %a = and i1 %c0, %c11753 %z = zext i1 %a to i321754 ret i32 %z1755}1756 1757define i32 @and_sle_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1758; CHECK-SD-LABEL: and_sle_ule:1759; CHECK-SD: // %bb.0: // %entry1760; CHECK-SD-NEXT: cmp w0, w11761; CHECK-SD-NEXT: ccmp w2, w3, #2, le1762; CHECK-SD-NEXT: cset w0, ls1763; CHECK-SD-NEXT: ret1764;1765; CHECK-GI-LABEL: and_sle_ule:1766; CHECK-GI: // %bb.0: // %entry1767; CHECK-GI-NEXT: cmp w0, w11768; CHECK-GI-NEXT: cset w8, le1769; CHECK-GI-NEXT: cmp w2, w31770; CHECK-GI-NEXT: cset w9, ls1771; CHECK-GI-NEXT: and w0, w8, w91772; CHECK-GI-NEXT: ret1773entry:1774 %c0 = icmp sle i32 %s0, %s11775 %c1 = icmp ule i32 %s2, %s31776 %a = and i1 %c0, %c11777 %z = zext i1 %a to i321778 ret i32 %z1779}1780 1781define i32 @and_sle_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1782; CHECK-SD-LABEL: and_sle_ugt:1783; CHECK-SD: // %bb.0: // %entry1784; CHECK-SD-NEXT: cmp w0, w11785; CHECK-SD-NEXT: ccmp w2, w3, #0, le1786; CHECK-SD-NEXT: cset w0, hi1787; CHECK-SD-NEXT: ret1788;1789; CHECK-GI-LABEL: and_sle_ugt:1790; CHECK-GI: // %bb.0: // %entry1791; CHECK-GI-NEXT: cmp w0, w11792; CHECK-GI-NEXT: cset w8, le1793; CHECK-GI-NEXT: cmp w2, w31794; CHECK-GI-NEXT: cset w9, hi1795; CHECK-GI-NEXT: and w0, w8, w91796; CHECK-GI-NEXT: ret1797entry:1798 %c0 = icmp sle i32 %s0, %s11799 %c1 = icmp ugt i32 %s2, %s31800 %a = and i1 %c0, %c11801 %z = zext i1 %a to i321802 ret i32 %z1803}1804 1805define i32 @and_sle_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1806; CHECK-SD-LABEL: and_sle_uge:1807; CHECK-SD: // %bb.0: // %entry1808; CHECK-SD-NEXT: cmp w0, w11809; CHECK-SD-NEXT: ccmp w2, w3, #0, le1810; CHECK-SD-NEXT: cset w0, hs1811; CHECK-SD-NEXT: ret1812;1813; CHECK-GI-LABEL: and_sle_uge:1814; CHECK-GI: // %bb.0: // %entry1815; CHECK-GI-NEXT: cmp w0, w11816; CHECK-GI-NEXT: cset w8, le1817; CHECK-GI-NEXT: cmp w2, w31818; CHECK-GI-NEXT: cset w9, hs1819; CHECK-GI-NEXT: and w0, w8, w91820; CHECK-GI-NEXT: ret1821entry:1822 %c0 = icmp sle i32 %s0, %s11823 %c1 = icmp uge i32 %s2, %s31824 %a = and i1 %c0, %c11825 %z = zext i1 %a to i321826 ret i32 %z1827}1828 1829define i32 @and_sle_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1830; CHECK-SD-LABEL: and_sle_slt:1831; CHECK-SD: // %bb.0: // %entry1832; CHECK-SD-NEXT: cmp w0, w11833; CHECK-SD-NEXT: ccmp w2, w3, #0, le1834; CHECK-SD-NEXT: cset w0, lt1835; CHECK-SD-NEXT: ret1836;1837; CHECK-GI-LABEL: and_sle_slt:1838; CHECK-GI: // %bb.0: // %entry1839; CHECK-GI-NEXT: cmp w0, w11840; CHECK-GI-NEXT: cset w8, le1841; CHECK-GI-NEXT: cmp w2, w31842; CHECK-GI-NEXT: cset w9, lt1843; CHECK-GI-NEXT: and w0, w8, w91844; CHECK-GI-NEXT: ret1845entry:1846 %c0 = icmp sle i32 %s0, %s11847 %c1 = icmp slt i32 %s2, %s31848 %a = and i1 %c0, %c11849 %z = zext i1 %a to i321850 ret i32 %z1851}1852 1853define i32 @and_sle_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1854; CHECK-SD-LABEL: and_sle_sle:1855; CHECK-SD: // %bb.0: // %entry1856; CHECK-SD-NEXT: cmp w0, w11857; CHECK-SD-NEXT: ccmp w2, w3, #0, le1858; CHECK-SD-NEXT: cset w0, le1859; CHECK-SD-NEXT: ret1860;1861; CHECK-GI-LABEL: and_sle_sle:1862; CHECK-GI: // %bb.0: // %entry1863; CHECK-GI-NEXT: cmp w0, w11864; CHECK-GI-NEXT: cset w8, le1865; CHECK-GI-NEXT: cmp w2, w31866; CHECK-GI-NEXT: cset w9, le1867; CHECK-GI-NEXT: and w0, w8, w91868; CHECK-GI-NEXT: ret1869entry:1870 %c0 = icmp sle i32 %s0, %s11871 %c1 = icmp sle i32 %s2, %s31872 %a = and i1 %c0, %c11873 %z = zext i1 %a to i321874 ret i32 %z1875}1876 1877define i32 @and_sle_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1878; CHECK-SD-LABEL: and_sle_sgt:1879; CHECK-SD: // %bb.0: // %entry1880; CHECK-SD-NEXT: cmp w0, w11881; CHECK-SD-NEXT: ccmp w2, w3, #4, le1882; CHECK-SD-NEXT: cset w0, gt1883; CHECK-SD-NEXT: ret1884;1885; CHECK-GI-LABEL: and_sle_sgt:1886; CHECK-GI: // %bb.0: // %entry1887; CHECK-GI-NEXT: cmp w0, w11888; CHECK-GI-NEXT: cset w8, le1889; CHECK-GI-NEXT: cmp w2, w31890; CHECK-GI-NEXT: cset w9, gt1891; CHECK-GI-NEXT: and w0, w8, w91892; CHECK-GI-NEXT: ret1893entry:1894 %c0 = icmp sle i32 %s0, %s11895 %c1 = icmp sgt i32 %s2, %s31896 %a = and i1 %c0, %c11897 %z = zext i1 %a to i321898 ret i32 %z1899}1900 1901define i32 @and_sle_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1902; CHECK-SD-LABEL: and_sle_sge:1903; CHECK-SD: // %bb.0: // %entry1904; CHECK-SD-NEXT: cmp w0, w11905; CHECK-SD-NEXT: ccmp w2, w3, #8, le1906; CHECK-SD-NEXT: cset w0, ge1907; CHECK-SD-NEXT: ret1908;1909; CHECK-GI-LABEL: and_sle_sge:1910; CHECK-GI: // %bb.0: // %entry1911; CHECK-GI-NEXT: cmp w0, w11912; CHECK-GI-NEXT: cset w8, le1913; CHECK-GI-NEXT: cmp w2, w31914; CHECK-GI-NEXT: cset w9, ge1915; CHECK-GI-NEXT: and w0, w8, w91916; CHECK-GI-NEXT: ret1917entry:1918 %c0 = icmp sle i32 %s0, %s11919 %c1 = icmp sge i32 %s2, %s31920 %a = and i1 %c0, %c11921 %z = zext i1 %a to i321922 ret i32 %z1923}1924 1925define i32 @and_sgt_eq(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1926; CHECK-SD-LABEL: and_sgt_eq:1927; CHECK-SD: // %bb.0: // %entry1928; CHECK-SD-NEXT: cmp w0, w11929; CHECK-SD-NEXT: ccmp w2, w3, #0, gt1930; CHECK-SD-NEXT: cset w0, eq1931; CHECK-SD-NEXT: ret1932;1933; CHECK-GI-LABEL: and_sgt_eq:1934; CHECK-GI: // %bb.0: // %entry1935; CHECK-GI-NEXT: cmp w0, w11936; CHECK-GI-NEXT: cset w8, gt1937; CHECK-GI-NEXT: cmp w2, w31938; CHECK-GI-NEXT: cset w9, eq1939; CHECK-GI-NEXT: and w0, w8, w91940; CHECK-GI-NEXT: ret1941entry:1942 %c0 = icmp sgt i32 %s0, %s11943 %c1 = icmp eq i32 %s2, %s31944 %a = and i1 %c0, %c11945 %z = zext i1 %a to i321946 ret i32 %z1947}1948 1949define i32 @and_sgt_ne(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1950; CHECK-SD-LABEL: and_sgt_ne:1951; CHECK-SD: // %bb.0: // %entry1952; CHECK-SD-NEXT: cmp w0, w11953; CHECK-SD-NEXT: ccmp w2, w3, #4, gt1954; CHECK-SD-NEXT: cset w0, ne1955; CHECK-SD-NEXT: ret1956;1957; CHECK-GI-LABEL: and_sgt_ne:1958; CHECK-GI: // %bb.0: // %entry1959; CHECK-GI-NEXT: cmp w0, w11960; CHECK-GI-NEXT: cset w8, gt1961; CHECK-GI-NEXT: cmp w2, w31962; CHECK-GI-NEXT: cset w9, ne1963; CHECK-GI-NEXT: and w0, w8, w91964; CHECK-GI-NEXT: ret1965entry:1966 %c0 = icmp sgt i32 %s0, %s11967 %c1 = icmp ne i32 %s2, %s31968 %a = and i1 %c0, %c11969 %z = zext i1 %a to i321970 ret i32 %z1971}1972 1973define i32 @and_sgt_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1974; CHECK-SD-LABEL: and_sgt_ult:1975; CHECK-SD: // %bb.0: // %entry1976; CHECK-SD-NEXT: cmp w0, w11977; CHECK-SD-NEXT: ccmp w2, w3, #2, gt1978; CHECK-SD-NEXT: cset w0, lo1979; CHECK-SD-NEXT: ret1980;1981; CHECK-GI-LABEL: and_sgt_ult:1982; CHECK-GI: // %bb.0: // %entry1983; CHECK-GI-NEXT: cmp w0, w11984; CHECK-GI-NEXT: cset w8, gt1985; CHECK-GI-NEXT: cmp w2, w31986; CHECK-GI-NEXT: cset w9, lo1987; CHECK-GI-NEXT: and w0, w8, w91988; CHECK-GI-NEXT: ret1989entry:1990 %c0 = icmp sgt i32 %s0, %s11991 %c1 = icmp ult i32 %s2, %s31992 %a = and i1 %c0, %c11993 %z = zext i1 %a to i321994 ret i32 %z1995}1996 1997define i32 @and_sgt_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {1998; CHECK-SD-LABEL: and_sgt_ule:1999; CHECK-SD: // %bb.0: // %entry2000; CHECK-SD-NEXT: cmp w0, w12001; CHECK-SD-NEXT: ccmp w2, w3, #2, gt2002; CHECK-SD-NEXT: cset w0, ls2003; CHECK-SD-NEXT: ret2004;2005; CHECK-GI-LABEL: and_sgt_ule:2006; CHECK-GI: // %bb.0: // %entry2007; CHECK-GI-NEXT: cmp w0, w12008; CHECK-GI-NEXT: cset w8, gt2009; CHECK-GI-NEXT: cmp w2, w32010; CHECK-GI-NEXT: cset w9, ls2011; CHECK-GI-NEXT: and w0, w8, w92012; CHECK-GI-NEXT: ret2013entry:2014 %c0 = icmp sgt i32 %s0, %s12015 %c1 = icmp ule i32 %s2, %s32016 %a = and i1 %c0, %c12017 %z = zext i1 %a to i322018 ret i32 %z2019}2020 2021define i32 @and_sgt_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {2022; CHECK-SD-LABEL: and_sgt_ugt:2023; CHECK-SD: // %bb.0: // %entry2024; CHECK-SD-NEXT: cmp w0, w12025; CHECK-SD-NEXT: ccmp w2, w3, #0, gt2026; CHECK-SD-NEXT: cset w0, hi2027; CHECK-SD-NEXT: ret2028;2029; CHECK-GI-LABEL: and_sgt_ugt:2030; CHECK-GI: // %bb.0: // %entry2031; CHECK-GI-NEXT: cmp w0, w12032; CHECK-GI-NEXT: cset w8, gt2033; CHECK-GI-NEXT: cmp w2, w32034; CHECK-GI-NEXT: cset w9, hi2035; CHECK-GI-NEXT: and w0, w8, w92036; CHECK-GI-NEXT: ret2037entry:2038 %c0 = icmp sgt i32 %s0, %s12039 %c1 = icmp ugt i32 %s2, %s32040 %a = and i1 %c0, %c12041 %z = zext i1 %a to i322042 ret i32 %z2043}2044 2045define i32 @and_sgt_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {2046; CHECK-SD-LABEL: and_sgt_uge:2047; CHECK-SD: // %bb.0: // %entry2048; CHECK-SD-NEXT: cmp w0, w12049; CHECK-SD-NEXT: ccmp w2, w3, #0, gt2050; CHECK-SD-NEXT: cset w0, hs2051; CHECK-SD-NEXT: ret2052;2053; CHECK-GI-LABEL: and_sgt_uge:2054; CHECK-GI: // %bb.0: // %entry2055; CHECK-GI-NEXT: cmp w0, w12056; CHECK-GI-NEXT: cset w8, gt2057; CHECK-GI-NEXT: cmp w2, w32058; CHECK-GI-NEXT: cset w9, hs2059; CHECK-GI-NEXT: and w0, w8, w92060; CHECK-GI-NEXT: ret2061entry:2062 %c0 = icmp sgt i32 %s0, %s12063 %c1 = icmp uge i32 %s2, %s32064 %a = and i1 %c0, %c12065 %z = zext i1 %a to i322066 ret i32 %z2067}2068 2069define i32 @and_sgt_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {2070; CHECK-SD-LABEL: and_sgt_slt:2071; CHECK-SD: // %bb.0: // %entry2072; CHECK-SD-NEXT: cmp w0, w12073; CHECK-SD-NEXT: ccmp w2, w3, #0, gt2074; CHECK-SD-NEXT: cset w0, lt2075; CHECK-SD-NEXT: ret2076;2077; CHECK-GI-LABEL: and_sgt_slt:2078; CHECK-GI: // %bb.0: // %entry2079; CHECK-GI-NEXT: cmp w0, w12080; CHECK-GI-NEXT: cset w8, gt2081; CHECK-GI-NEXT: cmp w2, w32082; CHECK-GI-NEXT: cset w9, lt2083; CHECK-GI-NEXT: and w0, w8, w92084; CHECK-GI-NEXT: ret2085entry:2086 %c0 = icmp sgt i32 %s0, %s12087 %c1 = icmp slt i32 %s2, %s32088 %a = and i1 %c0, %c12089 %z = zext i1 %a to i322090 ret i32 %z2091}2092 2093define i32 @and_sgt_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {2094; CHECK-SD-LABEL: and_sgt_sle:2095; CHECK-SD: // %bb.0: // %entry2096; CHECK-SD-NEXT: cmp w0, w12097; CHECK-SD-NEXT: ccmp w2, w3, #0, gt2098; CHECK-SD-NEXT: cset w0, le2099; CHECK-SD-NEXT: ret2100;2101; CHECK-GI-LABEL: and_sgt_sle:2102; CHECK-GI: // %bb.0: // %entry2103; CHECK-GI-NEXT: cmp w0, w12104; CHECK-GI-NEXT: cset w8, gt2105; CHECK-GI-NEXT: cmp w2, w32106; CHECK-GI-NEXT: cset w9, le2107; CHECK-GI-NEXT: and w0, w8, w92108; CHECK-GI-NEXT: ret2109entry:2110 %c0 = icmp sgt i32 %s0, %s12111 %c1 = icmp sle i32 %s2, %s32112 %a = and i1 %c0, %c12113 %z = zext i1 %a to i322114 ret i32 %z2115}2116 2117define i32 @and_sgt_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {2118; CHECK-SD-LABEL: and_sgt_sgt:2119; CHECK-SD: // %bb.0: // %entry2120; CHECK-SD-NEXT: cmp w0, w12121; CHECK-SD-NEXT: ccmp w2, w3, #4, gt2122; CHECK-SD-NEXT: cset w0, gt2123; CHECK-SD-NEXT: ret2124;2125; CHECK-GI-LABEL: and_sgt_sgt:2126; CHECK-GI: // %bb.0: // %entry2127; CHECK-GI-NEXT: cmp w0, w12128; CHECK-GI-NEXT: cset w8, gt2129; CHECK-GI-NEXT: cmp w2, w32130; CHECK-GI-NEXT: cset w9, gt2131; CHECK-GI-NEXT: and w0, w8, w92132; CHECK-GI-NEXT: ret2133entry:2134 %c0 = icmp sgt i32 %s0, %s12135 %c1 = icmp sgt i32 %s2, %s32136 %a = and i1 %c0, %c12137 %z = zext i1 %a to i322138 ret i32 %z2139}2140 2141define i32 @and_sgt_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {2142; CHECK-SD-LABEL: and_sgt_sge:2143; CHECK-SD: // %bb.0: // %entry2144; CHECK-SD-NEXT: cmp w0, w12145; CHECK-SD-NEXT: ccmp w2, w3, #8, gt2146; CHECK-SD-NEXT: cset w0, ge2147; CHECK-SD-NEXT: ret2148;2149; CHECK-GI-LABEL: and_sgt_sge:2150; CHECK-GI: // %bb.0: // %entry2151; CHECK-GI-NEXT: cmp w0, w12152; CHECK-GI-NEXT: cset w8, gt2153; CHECK-GI-NEXT: cmp w2, w32154; CHECK-GI-NEXT: cset w9, ge2155; CHECK-GI-NEXT: and w0, w8, w92156; CHECK-GI-NEXT: ret2157entry:2158 %c0 = icmp sgt i32 %s0, %s12159 %c1 = icmp sge i32 %s2, %s32160 %a = and i1 %c0, %c12161 %z = zext i1 %a to i322162 ret i32 %z2163}2164 2165define i32 @and_sge_eq(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {2166; CHECK-SD-LABEL: and_sge_eq:2167; CHECK-SD: // %bb.0: // %entry2168; CHECK-SD-NEXT: cmp w0, w12169; CHECK-SD-NEXT: ccmp w2, w3, #0, ge2170; CHECK-SD-NEXT: cset w0, eq2171; CHECK-SD-NEXT: ret2172;2173; CHECK-GI-LABEL: and_sge_eq:2174; CHECK-GI: // %bb.0: // %entry2175; CHECK-GI-NEXT: cmp w0, w12176; CHECK-GI-NEXT: cset w8, ge2177; CHECK-GI-NEXT: cmp w2, w32178; CHECK-GI-NEXT: cset w9, eq2179; CHECK-GI-NEXT: and w0, w8, w92180; CHECK-GI-NEXT: ret2181entry:2182 %c0 = icmp sge i32 %s0, %s12183 %c1 = icmp eq i32 %s2, %s32184 %a = and i1 %c0, %c12185 %z = zext i1 %a to i322186 ret i32 %z2187}2188 2189define i32 @and_sge_ne(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {2190; CHECK-SD-LABEL: and_sge_ne:2191; CHECK-SD: // %bb.0: // %entry2192; CHECK-SD-NEXT: cmp w0, w12193; CHECK-SD-NEXT: ccmp w2, w3, #4, ge2194; CHECK-SD-NEXT: cset w0, ne2195; CHECK-SD-NEXT: ret2196;2197; CHECK-GI-LABEL: and_sge_ne:2198; CHECK-GI: // %bb.0: // %entry2199; CHECK-GI-NEXT: cmp w0, w12200; CHECK-GI-NEXT: cset w8, ge2201; CHECK-GI-NEXT: cmp w2, w32202; CHECK-GI-NEXT: cset w9, ne2203; CHECK-GI-NEXT: and w0, w8, w92204; CHECK-GI-NEXT: ret2205entry:2206 %c0 = icmp sge i32 %s0, %s12207 %c1 = icmp ne i32 %s2, %s32208 %a = and i1 %c0, %c12209 %z = zext i1 %a to i322210 ret i32 %z2211}2212 2213define i32 @and_sge_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {2214; CHECK-SD-LABEL: and_sge_ult:2215; CHECK-SD: // %bb.0: // %entry2216; CHECK-SD-NEXT: cmp w0, w12217; CHECK-SD-NEXT: ccmp w2, w3, #2, ge2218; CHECK-SD-NEXT: cset w0, lo2219; CHECK-SD-NEXT: ret2220;2221; CHECK-GI-LABEL: and_sge_ult:2222; CHECK-GI: // %bb.0: // %entry2223; CHECK-GI-NEXT: cmp w0, w12224; CHECK-GI-NEXT: cset w8, ge2225; CHECK-GI-NEXT: cmp w2, w32226; CHECK-GI-NEXT: cset w9, lo2227; CHECK-GI-NEXT: and w0, w8, w92228; CHECK-GI-NEXT: ret2229entry:2230 %c0 = icmp sge i32 %s0, %s12231 %c1 = icmp ult i32 %s2, %s32232 %a = and i1 %c0, %c12233 %z = zext i1 %a to i322234 ret i32 %z2235}2236 2237define i32 @and_sge_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {2238; CHECK-SD-LABEL: and_sge_ule:2239; CHECK-SD: // %bb.0: // %entry2240; CHECK-SD-NEXT: cmp w0, w12241; CHECK-SD-NEXT: ccmp w2, w3, #2, ge2242; CHECK-SD-NEXT: cset w0, ls2243; CHECK-SD-NEXT: ret2244;2245; CHECK-GI-LABEL: and_sge_ule:2246; CHECK-GI: // %bb.0: // %entry2247; CHECK-GI-NEXT: cmp w0, w12248; CHECK-GI-NEXT: cset w8, ge2249; CHECK-GI-NEXT: cmp w2, w32250; CHECK-GI-NEXT: cset w9, ls2251; CHECK-GI-NEXT: and w0, w8, w92252; CHECK-GI-NEXT: ret2253entry:2254 %c0 = icmp sge i32 %s0, %s12255 %c1 = icmp ule i32 %s2, %s32256 %a = and i1 %c0, %c12257 %z = zext i1 %a to i322258 ret i32 %z2259}2260 2261define i32 @and_sge_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {2262; CHECK-SD-LABEL: and_sge_ugt:2263; CHECK-SD: // %bb.0: // %entry2264; CHECK-SD-NEXT: cmp w0, w12265; CHECK-SD-NEXT: ccmp w2, w3, #0, ge2266; CHECK-SD-NEXT: cset w0, hi2267; CHECK-SD-NEXT: ret2268;2269; CHECK-GI-LABEL: and_sge_ugt:2270; CHECK-GI: // %bb.0: // %entry2271; CHECK-GI-NEXT: cmp w0, w12272; CHECK-GI-NEXT: cset w8, ge2273; CHECK-GI-NEXT: cmp w2, w32274; CHECK-GI-NEXT: cset w9, hi2275; CHECK-GI-NEXT: and w0, w8, w92276; CHECK-GI-NEXT: ret2277entry:2278 %c0 = icmp sge i32 %s0, %s12279 %c1 = icmp ugt i32 %s2, %s32280 %a = and i1 %c0, %c12281 %z = zext i1 %a to i322282 ret i32 %z2283}2284 2285define i32 @and_sge_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {2286; CHECK-SD-LABEL: and_sge_uge:2287; CHECK-SD: // %bb.0: // %entry2288; CHECK-SD-NEXT: cmp w0, w12289; CHECK-SD-NEXT: ccmp w2, w3, #0, ge2290; CHECK-SD-NEXT: cset w0, hs2291; CHECK-SD-NEXT: ret2292;2293; CHECK-GI-LABEL: and_sge_uge:2294; CHECK-GI: // %bb.0: // %entry2295; CHECK-GI-NEXT: cmp w0, w12296; CHECK-GI-NEXT: cset w8, ge2297; CHECK-GI-NEXT: cmp w2, w32298; CHECK-GI-NEXT: cset w9, hs2299; CHECK-GI-NEXT: and w0, w8, w92300; CHECK-GI-NEXT: ret2301entry:2302 %c0 = icmp sge i32 %s0, %s12303 %c1 = icmp uge i32 %s2, %s32304 %a = and i1 %c0, %c12305 %z = zext i1 %a to i322306 ret i32 %z2307}2308 2309define i32 @and_sge_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {2310; CHECK-SD-LABEL: and_sge_slt:2311; CHECK-SD: // %bb.0: // %entry2312; CHECK-SD-NEXT: cmp w0, w12313; CHECK-SD-NEXT: ccmp w2, w3, #0, ge2314; CHECK-SD-NEXT: cset w0, lt2315; CHECK-SD-NEXT: ret2316;2317; CHECK-GI-LABEL: and_sge_slt:2318; CHECK-GI: // %bb.0: // %entry2319; CHECK-GI-NEXT: cmp w0, w12320; CHECK-GI-NEXT: cset w8, ge2321; CHECK-GI-NEXT: cmp w2, w32322; CHECK-GI-NEXT: cset w9, lt2323; CHECK-GI-NEXT: and w0, w8, w92324; CHECK-GI-NEXT: ret2325entry:2326 %c0 = icmp sge i32 %s0, %s12327 %c1 = icmp slt i32 %s2, %s32328 %a = and i1 %c0, %c12329 %z = zext i1 %a to i322330 ret i32 %z2331}2332 2333define i32 @and_sge_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {2334; CHECK-SD-LABEL: and_sge_sle:2335; CHECK-SD: // %bb.0: // %entry2336; CHECK-SD-NEXT: cmp w0, w12337; CHECK-SD-NEXT: ccmp w2, w3, #0, ge2338; CHECK-SD-NEXT: cset w0, le2339; CHECK-SD-NEXT: ret2340;2341; CHECK-GI-LABEL: and_sge_sle:2342; CHECK-GI: // %bb.0: // %entry2343; CHECK-GI-NEXT: cmp w0, w12344; CHECK-GI-NEXT: cset w8, ge2345; CHECK-GI-NEXT: cmp w2, w32346; CHECK-GI-NEXT: cset w9, le2347; CHECK-GI-NEXT: and w0, w8, w92348; CHECK-GI-NEXT: ret2349entry:2350 %c0 = icmp sge i32 %s0, %s12351 %c1 = icmp sle i32 %s2, %s32352 %a = and i1 %c0, %c12353 %z = zext i1 %a to i322354 ret i32 %z2355}2356 2357define i32 @and_sge_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {2358; CHECK-SD-LABEL: and_sge_sgt:2359; CHECK-SD: // %bb.0: // %entry2360; CHECK-SD-NEXT: cmp w0, w12361; CHECK-SD-NEXT: ccmp w2, w3, #4, ge2362; CHECK-SD-NEXT: cset w0, gt2363; CHECK-SD-NEXT: ret2364;2365; CHECK-GI-LABEL: and_sge_sgt:2366; CHECK-GI: // %bb.0: // %entry2367; CHECK-GI-NEXT: cmp w0, w12368; CHECK-GI-NEXT: cset w8, ge2369; CHECK-GI-NEXT: cmp w2, w32370; CHECK-GI-NEXT: cset w9, gt2371; CHECK-GI-NEXT: and w0, w8, w92372; CHECK-GI-NEXT: ret2373entry:2374 %c0 = icmp sge i32 %s0, %s12375 %c1 = icmp sgt i32 %s2, %s32376 %a = and i1 %c0, %c12377 %z = zext i1 %a to i322378 ret i32 %z2379}2380 2381define i32 @and_sge_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {2382; CHECK-SD-LABEL: and_sge_sge:2383; CHECK-SD: // %bb.0: // %entry2384; CHECK-SD-NEXT: cmp w0, w12385; CHECK-SD-NEXT: ccmp w2, w3, #8, ge2386; CHECK-SD-NEXT: cset w0, ge2387; CHECK-SD-NEXT: ret2388;2389; CHECK-GI-LABEL: and_sge_sge:2390; CHECK-GI: // %bb.0: // %entry2391; CHECK-GI-NEXT: cmp w0, w12392; CHECK-GI-NEXT: cset w8, ge2393; CHECK-GI-NEXT: cmp w2, w32394; CHECK-GI-NEXT: cset w9, ge2395; CHECK-GI-NEXT: and w0, w8, w92396; CHECK-GI-NEXT: ret2397entry:2398 %c0 = icmp sge i32 %s0, %s12399 %c1 = icmp sge i32 %s2, %s32400 %a = and i1 %c0, %c12401 %z = zext i1 %a to i322402 ret i32 %z2403}2404 2405define i32 @cmp_to_ands1(i32 %num) {2406; CHECK-SD-LABEL: cmp_to_ands1:2407; CHECK-SD: // %bb.0:2408; CHECK-SD-NEXT: and w8, w0, #0xff2409; CHECK-SD-NEXT: tst w0, #0xfe2410; CHECK-SD-NEXT: csel w0, w8, wzr, ne2411; CHECK-SD-NEXT: ret2412;2413; CHECK-GI-LABEL: cmp_to_ands1:2414; CHECK-GI: // %bb.0:2415; CHECK-GI-NEXT: and w8, w0, #0xff2416; CHECK-GI-NEXT: cmp w8, #12417; CHECK-GI-NEXT: csel w0, w8, wzr, hi2418; CHECK-GI-NEXT: ret2419 %and = and i32 %num, 2552420 %cmp = icmp ugt i32 %and, 12421 %r = select i1 %cmp, i32 %and, i32 02422 ret i32 %r2423}2424 2425define i32 @cmp_to_ands2(i32 %num) {2426; CHECK-SD-LABEL: cmp_to_ands2:2427; CHECK-SD: // %bb.0:2428; CHECK-SD-NEXT: and w8, w0, #0xfe2429; CHECK-SD-NEXT: tst w0, #0xc02430; CHECK-SD-NEXT: csel w0, w8, wzr, ne2431; CHECK-SD-NEXT: ret2432;2433; CHECK-GI-LABEL: cmp_to_ands2:2434; CHECK-GI: // %bb.0:2435; CHECK-GI-NEXT: and w8, w0, #0xfe2436; CHECK-GI-NEXT: cmp w8, #632437; CHECK-GI-NEXT: csel w0, w8, wzr, hi2438; CHECK-GI-NEXT: ret2439 %and = and i32 %num, 2542440 %cmp = icmp ugt i32 %and, 632441 %r = select i1 %cmp, i32 %and, i32 02442 ret i32 %r2443}2444 2445define i32 @cmp_to_ands3(i32 %num, i32 %a) {2446; CHECK-SD-LABEL: cmp_to_ands3:2447; CHECK-SD: // %bb.0:2448; CHECK-SD-NEXT: tst w0, #0x102449; CHECK-SD-NEXT: csel w0, w1, wzr, ne2450; CHECK-SD-NEXT: ret2451;2452; CHECK-GI-LABEL: cmp_to_ands3:2453; CHECK-GI: // %bb.0:2454; CHECK-GI-NEXT: mov w8, #23 // =0x172455; CHECK-GI-NEXT: and w8, w0, w82456; CHECK-GI-NEXT: cmp w8, #72457; CHECK-GI-NEXT: csel w0, w1, wzr, hi2458; CHECK-GI-NEXT: ret2459 %and = and i32 %num, 232460 %cmp = icmp ugt i32 %and, 72461 %r = select i1 %cmp, i32 %a, i32 02462 ret i32 %r2463}2464 2465define i32 @cmp_to_ands4(i32 %num, i32 %a) {2466; CHECK-SD-LABEL: cmp_to_ands4:2467; CHECK-SD: // %bb.0:2468; CHECK-SD-NEXT: and w8, w0, #0x302469; CHECK-SD-NEXT: tst w0, #0x202470; CHECK-SD-NEXT: csel w0, w8, w1, eq2471; CHECK-SD-NEXT: ret2472;2473; CHECK-GI-LABEL: cmp_to_ands4:2474; CHECK-GI: // %bb.0:2475; CHECK-GI-NEXT: and w8, w0, #0x302476; CHECK-GI-NEXT: cmp w8, #312477; CHECK-GI-NEXT: csel w0, w8, w1, ls2478; CHECK-GI-NEXT: ret2479 %and = and i32 %num, 482480 %cmp = icmp ule i32 %and, 312481 %r = select i1 %cmp, i32 %and, i32 %a2482 ret i32 %r2483}2484 2485define i32 @cmp_to_ands5(i32 %num, i32 %a) {2486; CHECK-SD-LABEL: cmp_to_ands5:2487; CHECK-SD: // %bb.0:2488; CHECK-SD-NEXT: and w8, w0, #0xf82489; CHECK-SD-NEXT: tst w0, #0xc02490; CHECK-SD-NEXT: csel w0, w8, w1, eq2491; CHECK-SD-NEXT: ret2492;2493; CHECK-GI-LABEL: cmp_to_ands5:2494; CHECK-GI: // %bb.0:2495; CHECK-GI-NEXT: and w8, w0, #0xf82496; CHECK-GI-NEXT: cmp w8, #642497; CHECK-GI-NEXT: csel w0, w8, w1, lo2498; CHECK-GI-NEXT: ret2499 %and = and i32 %num, 2482500 %cmp = icmp ult i32 %and, 642501 %r = select i1 %cmp, i32 %and, i32 %a2502 ret i32 %r2503}2504 2505define i32 @cmp_to_ands6(i32 %num) {2506; CHECK-SD-LABEL: cmp_to_ands6:2507; CHECK-SD: // %bb.0:2508; CHECK-SD-NEXT: and w8, w0, #0xfe2509; CHECK-SD-NEXT: tst w0, #0xf02510; CHECK-SD-NEXT: csel w0, w8, wzr, ne2511; CHECK-SD-NEXT: ret2512;2513; CHECK-GI-LABEL: cmp_to_ands6:2514; CHECK-GI: // %bb.0:2515; CHECK-GI-NEXT: and w8, w0, #0xfe2516; CHECK-GI-NEXT: cmp w8, #162517; CHECK-GI-NEXT: csel w0, w8, wzr, hs2518; CHECK-GI-NEXT: ret2519 %and = and i32 %num, 2542520 %cmp = icmp uge i32 %and, 162521 %r = select i1 %cmp, i32 %and, i32 02522 ret i32 %r2523}2524 2525define i1 @and_fcmp(float %0, float %1) {2526; CHECK-SD-LABEL: and_fcmp:2527; CHECK-SD: // %bb.0:2528; CHECK-SD-NEXT: fcmp s1, s12529; CHECK-SD-NEXT: fccmp s0, s0, #0, vs2530; CHECK-SD-NEXT: cset w0, vs2531; CHECK-SD-NEXT: ret2532;2533; CHECK-GI-LABEL: and_fcmp:2534; CHECK-GI: // %bb.0:2535; CHECK-GI-NEXT: fcmp s0, #0.02536; CHECK-GI-NEXT: cset w8, vs2537; CHECK-GI-NEXT: fcmp s1, #0.02538; CHECK-GI-NEXT: cset w9, vs2539; CHECK-GI-NEXT: and w0, w8, w92540; CHECK-GI-NEXT: ret2541 2542 %3 = fcmp uno float %0, 0.000000e+002543 %4 = fcmp uno float %1, 0.000000e+002544 %5 = and i1 %3, %42545 ret i1 %52546}2547 2548 2549;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:2550; CHECK: {{.*}}2551