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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-none-elf -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64-none-elf -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5declare void @dummy()6 7define i32 @and_eq_ne_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, ptr %p) {8; CHECK-SD-LABEL: and_eq_ne_ult:9; CHECK-SD: // %bb.0: // %entry10; CHECK-SD-NEXT: cmp w2, w311; CHECK-SD-NEXT: ccmp w0, w1, #0, ne12; CHECK-SD-NEXT: b.eq .LBB0_313; CHECK-SD-NEXT: // %bb.1: // %entry14; CHECK-SD-NEXT: cmp w4, w515; CHECK-SD-NEXT: b.lo .LBB0_316; CHECK-SD-NEXT: // %bb.2:17; CHECK-SD-NEXT: mov w0, wzr18; CHECK-SD-NEXT: ret19; CHECK-SD-NEXT: .LBB0_3: // %if20; CHECK-SD-NEXT: mov w0, #1 // =0x121; CHECK-SD-NEXT: str w0, [x6]22; CHECK-SD-NEXT: ret23;24; CHECK-GI-LABEL: and_eq_ne_ult:25; CHECK-GI: // %bb.0: // %entry26; CHECK-GI-NEXT: cmp w0, w127; CHECK-GI-NEXT: cset w8, eq28; CHECK-GI-NEXT: cmp w2, w329; CHECK-GI-NEXT: cset w9, ne30; CHECK-GI-NEXT: and w8, w8, w931; CHECK-GI-NEXT: tbnz w8, #0, .LBB0_332; CHECK-GI-NEXT: // %bb.1: // %entry33; CHECK-GI-NEXT: cmp w4, w534; CHECK-GI-NEXT: mov w0, wzr35; CHECK-GI-NEXT: b.lo .LBB0_336; CHECK-GI-NEXT: // %bb.2: // %common.ret37; CHECK-GI-NEXT: ret38; CHECK-GI-NEXT: .LBB0_3: // %if39; CHECK-GI-NEXT: mov w0, #1 // =0x140; CHECK-GI-NEXT: str w0, [x6]41; CHECK-GI-NEXT: ret42entry:43 %c0 = icmp eq i32 %s0, %s144 %c1 = icmp ne i32 %s2, %s345 %a = and i1 %c0, %c146 %c2 = icmp ult i32 %s4, %s547 %o = or i1 %a, %c248 br i1 %o, label %if, label %else49 50if:51 store i32 1, ptr %p52 ret i32 153 54else:55 ret i32 056}57 58define i32 @and_ne_ult_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, ptr %p) {59; CHECK-SD-LABEL: and_ne_ult_ule:60; CHECK-SD: // %bb.0: // %entry61; CHECK-SD-NEXT: cmp w2, w362; CHECK-SD-NEXT: ccmp w0, w1, #4, lo63; CHECK-SD-NEXT: b.ne .LBB1_364; CHECK-SD-NEXT: // %bb.1: // %entry65; CHECK-SD-NEXT: cmp w4, w566; CHECK-SD-NEXT: b.ls .LBB1_367; CHECK-SD-NEXT: // %bb.2:68; CHECK-SD-NEXT: mov w0, wzr69; CHECK-SD-NEXT: ret70; CHECK-SD-NEXT: .LBB1_3: // %if71; CHECK-SD-NEXT: mov w0, #1 // =0x172; CHECK-SD-NEXT: str w0, [x6]73; CHECK-SD-NEXT: ret74;75; CHECK-GI-LABEL: and_ne_ult_ule:76; CHECK-GI: // %bb.0: // %entry77; CHECK-GI-NEXT: cmp w0, w178; CHECK-GI-NEXT: cset w8, ne79; CHECK-GI-NEXT: cmp w2, w380; CHECK-GI-NEXT: cset w9, lo81; CHECK-GI-NEXT: and w8, w8, w982; CHECK-GI-NEXT: tbnz w8, #0, .LBB1_383; CHECK-GI-NEXT: // %bb.1: // %entry84; CHECK-GI-NEXT: cmp w4, w585; CHECK-GI-NEXT: mov w0, wzr86; CHECK-GI-NEXT: b.ls .LBB1_387; CHECK-GI-NEXT: // %bb.2: // %common.ret88; CHECK-GI-NEXT: ret89; CHECK-GI-NEXT: .LBB1_3: // %if90; CHECK-GI-NEXT: mov w0, #1 // =0x191; CHECK-GI-NEXT: str w0, [x6]92; CHECK-GI-NEXT: ret93entry:94 %c0 = icmp ne i32 %s0, %s195 %c1 = icmp ult i32 %s2, %s396 %a = and i1 %c0, %c197 %c2 = icmp ule i32 %s4, %s598 %o = or i1 %a, %c299 br i1 %o, label %if, label %else100 101if:102 store i32 1, ptr %p103 ret i32 1104 105else:106 ret i32 0107}108 109define i32 @and_ult_ule_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, ptr %p) {110; CHECK-SD-LABEL: and_ult_ule_ugt:111; CHECK-SD: // %bb.0: // %entry112; CHECK-SD-NEXT: cmp w2, w3113; CHECK-SD-NEXT: ccmp w0, w1, #2, ls114; CHECK-SD-NEXT: b.lo .LBB2_3115; CHECK-SD-NEXT: // %bb.1: // %entry116; CHECK-SD-NEXT: cmp w4, w5117; CHECK-SD-NEXT: b.hi .LBB2_3118; CHECK-SD-NEXT: // %bb.2:119; CHECK-SD-NEXT: mov w0, wzr120; CHECK-SD-NEXT: ret121; CHECK-SD-NEXT: .LBB2_3: // %if122; CHECK-SD-NEXT: mov w0, #1 // =0x1123; CHECK-SD-NEXT: str w0, [x6]124; CHECK-SD-NEXT: ret125;126; CHECK-GI-LABEL: and_ult_ule_ugt:127; CHECK-GI: // %bb.0: // %entry128; CHECK-GI-NEXT: cmp w0, w1129; CHECK-GI-NEXT: cset w8, lo130; CHECK-GI-NEXT: cmp w2, w3131; CHECK-GI-NEXT: cset w9, ls132; CHECK-GI-NEXT: and w8, w8, w9133; CHECK-GI-NEXT: tbnz w8, #0, .LBB2_3134; CHECK-GI-NEXT: // %bb.1: // %entry135; CHECK-GI-NEXT: cmp w4, w5136; CHECK-GI-NEXT: mov w0, wzr137; CHECK-GI-NEXT: b.hi .LBB2_3138; CHECK-GI-NEXT: // %bb.2: // %common.ret139; CHECK-GI-NEXT: ret140; CHECK-GI-NEXT: .LBB2_3: // %if141; CHECK-GI-NEXT: mov w0, #1 // =0x1142; CHECK-GI-NEXT: str w0, [x6]143; CHECK-GI-NEXT: ret144entry:145 %c0 = icmp ult i32 %s0, %s1146 %c1 = icmp ule i32 %s2, %s3147 %a = and i1 %c0, %c1148 %c2 = icmp ugt i32 %s4, %s5149 %o = or i1 %a, %c2150 br i1 %o, label %if, label %else151 152if:153 store i32 1, ptr %p154 ret i32 1155 156else:157 ret i32 0158}159 160define i32 @and_ule_ugt_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, ptr %p) {161; CHECK-SD-LABEL: and_ule_ugt_uge:162; CHECK-SD: // %bb.0: // %entry163; CHECK-SD-NEXT: cmp w2, w3164; CHECK-SD-NEXT: ccmp w0, w1, #2, hi165; CHECK-SD-NEXT: b.ls .LBB3_3166; CHECK-SD-NEXT: // %bb.1: // %entry167; CHECK-SD-NEXT: cmp w4, w5168; CHECK-SD-NEXT: b.hs .LBB3_3169; CHECK-SD-NEXT: // %bb.2:170; CHECK-SD-NEXT: mov w0, wzr171; CHECK-SD-NEXT: ret172; CHECK-SD-NEXT: .LBB3_3: // %if173; CHECK-SD-NEXT: mov w0, #1 // =0x1174; CHECK-SD-NEXT: str w0, [x6]175; CHECK-SD-NEXT: ret176;177; CHECK-GI-LABEL: and_ule_ugt_uge:178; CHECK-GI: // %bb.0: // %entry179; CHECK-GI-NEXT: cmp w0, w1180; CHECK-GI-NEXT: cset w8, ls181; CHECK-GI-NEXT: cmp w2, w3182; CHECK-GI-NEXT: cset w9, hi183; CHECK-GI-NEXT: and w8, w8, w9184; CHECK-GI-NEXT: tbnz w8, #0, .LBB3_3185; CHECK-GI-NEXT: // %bb.1: // %entry186; CHECK-GI-NEXT: cmp w4, w5187; CHECK-GI-NEXT: mov w0, wzr188; CHECK-GI-NEXT: b.hs .LBB3_3189; CHECK-GI-NEXT: // %bb.2: // %common.ret190; CHECK-GI-NEXT: ret191; CHECK-GI-NEXT: .LBB3_3: // %if192; CHECK-GI-NEXT: mov w0, #1 // =0x1193; CHECK-GI-NEXT: str w0, [x6]194; CHECK-GI-NEXT: ret195entry:196 %c0 = icmp ule i32 %s0, %s1197 %c1 = icmp ugt i32 %s2, %s3198 %a = and i1 %c0, %c1199 %c2 = icmp uge i32 %s4, %s5200 %o = or i1 %a, %c2201 br i1 %o, label %if, label %else202 203if:204 store i32 1, ptr %p205 ret i32 1206 207else:208 ret i32 0209}210 211define i32 @and_ugt_uge_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, ptr %p) {212; CHECK-SD-LABEL: and_ugt_uge_slt:213; CHECK-SD: // %bb.0: // %entry214; CHECK-SD-NEXT: cmp w2, w3215; CHECK-SD-NEXT: ccmp w0, w1, #0, hs216; CHECK-SD-NEXT: b.hi .LBB4_3217; CHECK-SD-NEXT: // %bb.1: // %entry218; CHECK-SD-NEXT: cmp w4, w5219; CHECK-SD-NEXT: b.lt .LBB4_3220; CHECK-SD-NEXT: // %bb.2:221; CHECK-SD-NEXT: mov w0, wzr222; CHECK-SD-NEXT: ret223; CHECK-SD-NEXT: .LBB4_3: // %if224; CHECK-SD-NEXT: mov w0, #1 // =0x1225; CHECK-SD-NEXT: str w0, [x6]226; CHECK-SD-NEXT: ret227;228; CHECK-GI-LABEL: and_ugt_uge_slt:229; CHECK-GI: // %bb.0: // %entry230; CHECK-GI-NEXT: cmp w0, w1231; CHECK-GI-NEXT: cset w8, hi232; CHECK-GI-NEXT: cmp w2, w3233; CHECK-GI-NEXT: cset w9, hs234; CHECK-GI-NEXT: and w8, w8, w9235; CHECK-GI-NEXT: tbnz w8, #0, .LBB4_3236; CHECK-GI-NEXT: // %bb.1: // %entry237; CHECK-GI-NEXT: cmp w4, w5238; CHECK-GI-NEXT: mov w0, wzr239; CHECK-GI-NEXT: b.lt .LBB4_3240; CHECK-GI-NEXT: // %bb.2: // %common.ret241; CHECK-GI-NEXT: ret242; CHECK-GI-NEXT: .LBB4_3: // %if243; CHECK-GI-NEXT: mov w0, #1 // =0x1244; CHECK-GI-NEXT: str w0, [x6]245; CHECK-GI-NEXT: ret246entry:247 %c0 = icmp ugt i32 %s0, %s1248 %c1 = icmp uge i32 %s2, %s3249 %a = and i1 %c0, %c1250 %c2 = icmp slt i32 %s4, %s5251 %o = or i1 %a, %c2252 br i1 %o, label %if, label %else253 254if:255 store i32 1, ptr %p256 ret i32 1257 258else:259 ret i32 0260}261 262define i32 @and_uge_slt_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, ptr %p) {263; CHECK-SD-LABEL: and_uge_slt_sle:264; CHECK-SD: // %bb.0: // %entry265; CHECK-SD-NEXT: cmp w2, w3266; CHECK-SD-NEXT: ccmp w0, w1, #0, lt267; CHECK-SD-NEXT: b.hs .LBB5_3268; CHECK-SD-NEXT: // %bb.1: // %entry269; CHECK-SD-NEXT: cmp w4, w5270; CHECK-SD-NEXT: b.le .LBB5_3271; CHECK-SD-NEXT: // %bb.2:272; CHECK-SD-NEXT: mov w0, wzr273; CHECK-SD-NEXT: ret274; CHECK-SD-NEXT: .LBB5_3: // %if275; CHECK-SD-NEXT: mov w0, #1 // =0x1276; CHECK-SD-NEXT: str w0, [x6]277; CHECK-SD-NEXT: ret278;279; CHECK-GI-LABEL: and_uge_slt_sle:280; CHECK-GI: // %bb.0: // %entry281; CHECK-GI-NEXT: cmp w0, w1282; CHECK-GI-NEXT: cset w8, hs283; CHECK-GI-NEXT: cmp w2, w3284; CHECK-GI-NEXT: cset w9, lt285; CHECK-GI-NEXT: and w8, w8, w9286; CHECK-GI-NEXT: tbnz w8, #0, .LBB5_3287; CHECK-GI-NEXT: // %bb.1: // %entry288; CHECK-GI-NEXT: cmp w4, w5289; CHECK-GI-NEXT: mov w0, wzr290; CHECK-GI-NEXT: b.le .LBB5_3291; CHECK-GI-NEXT: // %bb.2: // %common.ret292; CHECK-GI-NEXT: ret293; CHECK-GI-NEXT: .LBB5_3: // %if294; CHECK-GI-NEXT: mov w0, #1 // =0x1295; CHECK-GI-NEXT: str w0, [x6]296; CHECK-GI-NEXT: ret297entry:298 %c0 = icmp uge i32 %s0, %s1299 %c1 = icmp slt i32 %s2, %s3300 %a = and i1 %c0, %c1301 %c2 = icmp sle i32 %s4, %s5302 %o = or i1 %a, %c2303 br i1 %o, label %if, label %else304 305if:306 store i32 1, ptr %p307 ret i32 1308 309else:310 ret i32 0311}312 313define i32 @and_slt_sle_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, ptr %p) {314; CHECK-SD-LABEL: and_slt_sle_sgt:315; CHECK-SD: // %bb.0: // %entry316; CHECK-SD-NEXT: cmp w2, w3317; CHECK-SD-NEXT: ccmp w0, w1, #0, le318; CHECK-SD-NEXT: b.lt .LBB6_3319; CHECK-SD-NEXT: // %bb.1: // %entry320; CHECK-SD-NEXT: cmp w4, w5321; CHECK-SD-NEXT: b.gt .LBB6_3322; CHECK-SD-NEXT: // %bb.2:323; CHECK-SD-NEXT: mov w0, wzr324; CHECK-SD-NEXT: ret325; CHECK-SD-NEXT: .LBB6_3: // %if326; CHECK-SD-NEXT: mov w0, #1 // =0x1327; CHECK-SD-NEXT: str w0, [x6]328; CHECK-SD-NEXT: ret329;330; CHECK-GI-LABEL: and_slt_sle_sgt:331; CHECK-GI: // %bb.0: // %entry332; CHECK-GI-NEXT: cmp w0, w1333; CHECK-GI-NEXT: cset w8, lt334; CHECK-GI-NEXT: cmp w2, w3335; CHECK-GI-NEXT: cset w9, le336; CHECK-GI-NEXT: and w8, w8, w9337; CHECK-GI-NEXT: tbnz w8, #0, .LBB6_3338; CHECK-GI-NEXT: // %bb.1: // %entry339; CHECK-GI-NEXT: cmp w4, w5340; CHECK-GI-NEXT: mov w0, wzr341; CHECK-GI-NEXT: b.gt .LBB6_3342; CHECK-GI-NEXT: // %bb.2: // %common.ret343; CHECK-GI-NEXT: ret344; CHECK-GI-NEXT: .LBB6_3: // %if345; CHECK-GI-NEXT: mov w0, #1 // =0x1346; CHECK-GI-NEXT: str w0, [x6]347; CHECK-GI-NEXT: ret348entry:349 %c0 = icmp slt i32 %s0, %s1350 %c1 = icmp sle i32 %s2, %s3351 %a = and i1 %c0, %c1352 %c2 = icmp sgt i32 %s4, %s5353 %o = or i1 %a, %c2354 br i1 %o, label %if, label %else355 356if:357 store i32 1, ptr %p358 ret i32 1359 360else:361 ret i32 0362}363 364define i32 @and_sle_sgt_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, ptr %p) {365; CHECK-SD-LABEL: and_sle_sgt_sge:366; CHECK-SD: // %bb.0: // %entry367; CHECK-SD-NEXT: cmp w2, w3368; CHECK-SD-NEXT: ccmp w0, w1, #0, gt369; CHECK-SD-NEXT: b.le .LBB7_3370; CHECK-SD-NEXT: // %bb.1: // %entry371; CHECK-SD-NEXT: cmp w4, w5372; CHECK-SD-NEXT: b.ge .LBB7_3373; CHECK-SD-NEXT: // %bb.2:374; CHECK-SD-NEXT: mov w0, wzr375; CHECK-SD-NEXT: ret376; CHECK-SD-NEXT: .LBB7_3: // %if377; CHECK-SD-NEXT: mov w0, #1 // =0x1378; CHECK-SD-NEXT: str w0, [x6]379; CHECK-SD-NEXT: ret380;381; CHECK-GI-LABEL: and_sle_sgt_sge:382; CHECK-GI: // %bb.0: // %entry383; CHECK-GI-NEXT: cmp w0, w1384; CHECK-GI-NEXT: cset w8, le385; CHECK-GI-NEXT: cmp w2, w3386; CHECK-GI-NEXT: cset w9, gt387; CHECK-GI-NEXT: and w8, w8, w9388; CHECK-GI-NEXT: tbnz w8, #0, .LBB7_3389; CHECK-GI-NEXT: // %bb.1: // %entry390; CHECK-GI-NEXT: cmp w4, w5391; CHECK-GI-NEXT: mov w0, wzr392; CHECK-GI-NEXT: b.ge .LBB7_3393; CHECK-GI-NEXT: // %bb.2: // %common.ret394; CHECK-GI-NEXT: ret395; CHECK-GI-NEXT: .LBB7_3: // %if396; CHECK-GI-NEXT: mov w0, #1 // =0x1397; CHECK-GI-NEXT: str w0, [x6]398; CHECK-GI-NEXT: ret399entry:400 %c0 = icmp sle i32 %s0, %s1401 %c1 = icmp sgt i32 %s2, %s3402 %a = and i1 %c0, %c1403 %c2 = icmp sge i32 %s4, %s5404 %o = or i1 %a, %c2405 br i1 %o, label %if, label %else406 407if:408 store i32 1, ptr %p409 ret i32 1410 411else:412 ret i32 0413}414;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:415; CHECK: {{.*}}416