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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=apple -aarch64-enable-simd-scalar=true | FileCheck %s -check-prefix=CHECK3; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=generic -aarch64-enable-simd-scalar=true | FileCheck %s -check-prefix=GENERIC4 5define <2 x i64> @bar(<2 x i64> %a, <2 x i64> %b) nounwind readnone {6; CHECK-LABEL: bar:7; CHECK: // %bb.0:8; CHECK-NEXT: add.2d v0, v0, v19; CHECK-NEXT: sub d2, d0, d110; CHECK-NEXT: add d0, d0, d111; CHECK-NEXT: fmov x8, d212; CHECK-NEXT: mov.d v0[1], x813; CHECK-NEXT: ret14;15; GENERIC-LABEL: bar:16; GENERIC: // %bb.0:17; GENERIC-NEXT: add v0.2d, v0.2d, v1.2d18; GENERIC-NEXT: sub d2, d0, d119; GENERIC-NEXT: add d0, d0, d120; GENERIC-NEXT: fmov x8, d221; GENERIC-NEXT: mov v0.d[1], x822; GENERIC-NEXT: ret23 %add = add <2 x i64> %a, %b24 %vgetq_lane = extractelement <2 x i64> %add, i32 025 %vgetq_lane2 = extractelement <2 x i64> %b, i32 026 %add3 = add i64 %vgetq_lane, %vgetq_lane227 %sub = sub i64 %vgetq_lane, %vgetq_lane228 %vecinit = insertelement <2 x i64> undef, i64 %add3, i32 029 %vecinit8 = insertelement <2 x i64> %vecinit, i64 %sub, i32 130 ret <2 x i64> %vecinit831}32 33define double @subdd_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone {34; CHECK-LABEL: subdd_su64:35; CHECK: // %bb.0:36; CHECK-NEXT: sub d0, d1, d037; CHECK-NEXT: ret38;39; GENERIC-LABEL: subdd_su64:40; GENERIC: // %bb.0:41; GENERIC-NEXT: sub d0, d1, d042; GENERIC-NEXT: ret43 %vecext = extractelement <2 x i64> %a, i32 044 %vecext1 = extractelement <2 x i64> %b, i32 045 %sub.i = sub nsw i64 %vecext1, %vecext46 %retval = bitcast i64 %sub.i to double47 ret double %retval48}49 50define double @vaddd_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone {51; CHECK-LABEL: vaddd_su64:52; CHECK: // %bb.0:53; CHECK-NEXT: add d0, d1, d054; CHECK-NEXT: ret55;56; GENERIC-LABEL: vaddd_su64:57; GENERIC: // %bb.0:58; GENERIC-NEXT: add d0, d1, d059; GENERIC-NEXT: ret60 %vecext = extractelement <2 x i64> %a, i32 061 %vecext1 = extractelement <2 x i64> %b, i32 062 %add.i = add nsw i64 %vecext1, %vecext63 %retval = bitcast i64 %add.i to double64 ret double %retval65}66 67; sub MI doesn't access dsub register.68define double @add_sub_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone {69; CHECK-LABEL: add_sub_su64:70; CHECK: // %bb.0:71; CHECK-NEXT: add d0, d1, d072; CHECK-NEXT: movi d1, #000000000000000073; CHECK-NEXT: sub d0, d1, d074; CHECK-NEXT: ret75;76; GENERIC-LABEL: add_sub_su64:77; GENERIC: // %bb.0:78; GENERIC-NEXT: add d0, d1, d079; GENERIC-NEXT: movi d1, #000000000000000080; GENERIC-NEXT: sub d0, d1, d081; GENERIC-NEXT: ret82 %vecext = extractelement <2 x i64> %a, i32 083 %vecext1 = extractelement <2 x i64> %b, i32 084 %add.i = add i64 %vecext1, %vecext85 %sub.i = sub i64 0, %add.i86 %retval = bitcast i64 %sub.i to double87 ret double %retval88}89define double @and_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone {90; CHECK-LABEL: and_su64:91; CHECK: // %bb.0:92; CHECK-NEXT: and.8b v0, v1, v093; CHECK-NEXT: ret94;95; GENERIC-LABEL: and_su64:96; GENERIC: // %bb.0:97; GENERIC-NEXT: and v0.8b, v1.8b, v0.8b98; GENERIC-NEXT: ret99 %vecext = extractelement <2 x i64> %a, i32 0100 %vecext1 = extractelement <2 x i64> %b, i32 0101 %or.i = and i64 %vecext1, %vecext102 %retval = bitcast i64 %or.i to double103 ret double %retval104}105 106define double @orr_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone {107; CHECK-LABEL: orr_su64:108; CHECK: // %bb.0:109; CHECK-NEXT: orr.8b v0, v1, v0110; CHECK-NEXT: ret111;112; GENERIC-LABEL: orr_su64:113; GENERIC: // %bb.0:114; GENERIC-NEXT: orr v0.8b, v1.8b, v0.8b115; GENERIC-NEXT: ret116 %vecext = extractelement <2 x i64> %a, i32 0117 %vecext1 = extractelement <2 x i64> %b, i32 0118 %or.i = or i64 %vecext1, %vecext119 %retval = bitcast i64 %or.i to double120 ret double %retval121}122 123define double @xorr_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone {124; CHECK-LABEL: xorr_su64:125; CHECK: // %bb.0:126; CHECK-NEXT: eor.8b v0, v1, v0127; CHECK-NEXT: ret128;129; GENERIC-LABEL: xorr_su64:130; GENERIC: // %bb.0:131; GENERIC-NEXT: eor v0.8b, v1.8b, v0.8b132; GENERIC-NEXT: ret133 %vecext = extractelement <2 x i64> %a, i32 0134 %vecext1 = extractelement <2 x i64> %b, i32 0135 %xor.i = xor i64 %vecext1, %vecext136 %retval = bitcast i64 %xor.i to double137 ret double %retval138}139