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1; RUN: llc -mtriple=arm64-linux-gnu -enable-misched=false -disable-post-ra < %s | FileCheck %s2 3@var = dso_local global i32 0, align 44 5; CHECK-LABEL: @test_i128_align6define dso_local i128 @test_i128_align(i32, i128 %arg, i32 %after) {7 store i32 %after, ptr @var, align 48; CHECK-DAG: str w4, [{{x[0-9]+}}, :lo12:var]9 10 ret i128 %arg11; CHECK-DAG: mov x0, x212; CHECK-DAG: mov x1, x313}14 15; CHECK-LABEL: @test_i64x2_align16define [2 x i64] @test_i64x2_align(i32, [2 x i64] %arg, i32 %after) {17 store i32 %after, ptr @var, align 418; CHECK-DAG: str w3, [{{x[0-9]+}}, :lo12:var]19 20 ret [2 x i64] %arg21; CHECK-DAG: mov x0, x122; CHECK: mov x1, x223}24 25@var64 = dso_local global i64 0, align 826 27; Check stack slots are 64-bit at all times.28define dso_local void @test_stack_slots([8 x i64], i1 %bool, i8 %char, i16 %short,29 i32 %int, i64 %long) {30; CHECK-LABEL: test_stack_slots:31; CHECK-DAG: ldr w[[ext1:[0-9]+]], [sp, #24]32; CHECK-DAG: ldrh w[[ext2:[0-9]+]], [sp, #16]33; CHECK-DAG: ldrb w[[ext3:[0-9]+]], [sp, #8]34; CHECK-DAG: ldr x[[ext4:[0-9]+]], [sp, #32]35; CHECK-DAG: ldrb w[[ext5:[0-9]+]], [sp]36 37 %ext_bool = zext i1 %bool to i6438 store volatile i64 %ext_bool, ptr @var64, align 839; CHECK: str x[[ext5]], [{{x[0-9]+}}, :lo12:var64]40 41 %ext_char = zext i8 %char to i6442 store volatile i64 %ext_char, ptr @var64, align 843; CHECK: str x[[ext3]], [{{x[0-9]+}}, :lo12:var64]44 45 %ext_short = zext i16 %short to i6446 store volatile i64 %ext_short, ptr @var64, align 847; CHECK: str x[[ext2]], [{{x[0-9]+}}, :lo12:var64]48 49 %ext_int = zext i32 %int to i6450 store volatile i64 %ext_int, ptr @var64, align 851; CHECK: str x[[ext1]], [{{x[0-9]+}}, :lo12:var64]52 53 store volatile i64 %long, ptr @var64, align 854; CHECK: str x[[ext4]], [{{x[0-9]+}}, :lo12:var64]55 56 ret void57}58 59; Make sure the callee does extensions (in the absence of zext/sext60; keyword on args) while we're here.61 62define dso_local void @test_extension(i1 %bool, i8 %char, i16 %short, i32 %int) {63 %ext_bool = zext i1 %bool to i6464 store volatile i64 %ext_bool, ptr @var6465; CHECK: and [[EXT:x[0-9]+]], x0, #0x166; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]67 68 %ext_char = sext i8 %char to i6469 store volatile i64 %ext_char, ptr @var6470; CHECK: sxtb [[EXT:x[0-9]+]], w171; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]72 73 %ext_short = zext i16 %short to i6474 store volatile i64 %ext_short, ptr @var6475; CHECK: and [[EXT:x[0-9]+]], x2, #0xffff76; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]77 78 %ext_int = zext i32 %int to i6479 store volatile i64 %ext_int, ptr @var6480; CHECK: mov w[[EXT:[0-9]+]], w381; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]82 83 ret void84}85 86declare void @variadic(i32 %a, ...)87 88 ; Under AAPCS variadic functions have the same calling convention as89 ; others. The extra arguments should go in registers rather than on the stack.90define dso_local void @test_variadic() {91 call void(i32, ...) @variadic(i32 0, i64 1, double 2.0)92; CHECK: mov w1, #193; CHECK: fmov d0, #2.094; CHECK: bl variadic95 ret void96}97 98; We weren't marking x7 as used after deciding that the i128 didn't fit into99; registers and putting the first half on the stack, so the *second* half went100; into x7. Yuck!101define dso_local i128 @test_i128_shadow([7 x i64] %x0_x6, i128 %sp) {102; CHECK-LABEL: test_i128_shadow:103; CHECK: ldp x0, x1, [sp]104 105 ret i128 %sp106}107 108; This test is to check if fp128 can be correctly handled on stack.109define fp128 @test_fp128([8 x float] %arg0, fp128 %arg1) {110; CHECK-LABEL: test_fp128:111; CHECK: ldr {{q[0-9]+}}, [sp]112 ret fp128 %arg1113}114 115; Check if VPR can be correctly pass by stack.116define dso_local <2 x double> @test_vreg_stack([8 x <2 x double>], <2 x double> %varg_stack) {117entry:118; CHECK-LABEL: test_vreg_stack:119; CHECK: ldr {{q[0-9]+}}, [sp]120 ret <2 x double> %varg_stack;121}122 123; Check that f16 can be passed and returned (ACLE 2.0 extension)124define half @test_half(float, half %arg) {125; CHECK-LABEL: test_half:126; CHECK: fmov s0, s1127 ret half %arg;128}129 130; Check that f16 constants are materialized correctly131define half @test_half_const() {132; CHECK-LABEL: test_half_const:133; CHECK: ldr h0, [x{{[0-9]+}}, :lo12:{{.*}}]134 ret half 0xH4248135}136 137; Check that v4f16 can be passed and returned in registers138define dso_local <4 x half> @test_v4_half_register(float, <4 x half> %arg) {139; CHECK-LABEL: test_v4_half_register:140; CHECK: fmov d0, d1141 ret <4 x half> %arg;142}143 144; Check that v8f16 can be passed and returned in registers145define dso_local <8 x half> @test_v8_half_register(float, <8 x half> %arg) {146; CHECK-LABEL: test_v8_half_register:147; CHECK: mov v0.16b, v1.16b148 ret <8 x half> %arg;149}150 151; Check that v4f16 can be passed and returned on the stack152define dso_local <4 x half> @test_v4_half_stack([8 x <2 x double>], <4 x half> %arg) {153; CHECK-LABEL: test_v4_half_stack:154; CHECK: ldr d0, [sp]155 ret <4 x half> %arg;156}157 158; Check that v8f16 can be passed and returned on the stack159define dso_local <8 x half> @test_v8_half_stack([8 x <2 x double>], <8 x half> %arg) {160; CHECK-LABEL: test_v8_half_stack:161; CHECK: ldr q0, [sp]162 ret <8 x half> %arg;163}164